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Part Manufacturer Description Datasheet Download Buy Part
LT1016CS8#PBF Linear Technology LT1016 - Ultra Fast Precision 10ns Comparator; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LT1016CS8#TRPBF Linear Technology LT1016 - Ultra Fast Precision 10ns Comparator; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LT1016IS8 Linear Technology LT1016 - Ultra Fast Precision 10ns Comparator; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C
LT1016IN8#PBF Linear Technology LT1016 - Ultra Fast Precision 10ns Comparator; Package: PDIP; Pins: 8; Temperature Range: -40°C to 85°C
LT1016IS8#PBF Linear Technology LT1016 - Ultra Fast Precision 10ns Comparator; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C
LT1016IS8#TR Linear Technology LT1016 - Ultra Fast Precision 10ns Comparator; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C

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A-31

Abstract: VAC068 LD31
Text: * Valid to PAS* (L) (Setup Time) 10ns 2. LD [31:16] Valid to PAS* (L) (Setup Time) 5ns 3. PAS* (L) to DSACKi* (L) 1T 4. PAS* (H) to DSACKi* (H) 0ns 10ns 5. PAS* (H) to LA [31:8], FC [2:0], R/W* (Hold Time) 5ns 6. PAS* (H) to LD [31:16] invalid 0ns 10ns 1T - One CPUCLK , Time) 10ns 2. PAS* (L) to DSACKi* (L) 0.5T 3. PAS* (L) to LD[31:16] Valid 4. PAS* (H) to DSACKi* (H) 0ns 10ns 5. PAS* (H) to LA [31:8], FC [2:0], Ft/W* (Hold Time) 5ns 6. PAS* (H) to LD [31


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PDF VAC068 A-31 LD31
Not Available

Abstract: No abstract text available
Text: * (L) (Setup Time) Typ Max 10ns 2. LD [31:16] Valid to PAS* (L) (Setup Time) 5ns 3 , . 46 input 10ns 10ns Figure 7.3: VAC068 Register Read Locai Bus Signals: Direction , Min 1. LA [31:8], FC [2:0], R/W* Valid to PAS* (L) (Setup Time) Max 10ns 2. PAS* (L) to , 10ns 0.5T = One half of a CPUCLK period. 10ns Input VAC068 Specification - Preliminary , ], FC [2:0], R/W* to PAS* (L) (Setup Time) 10ns 2. PAS* (L) to ASIZ [1,0]*, WORD Valid 0ns


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PDF VAC068
Not Available

Abstract: No abstract text available
Text: ; M5M4V64S30ATP- 8A / 8 /1 0 x l6 ; M5M4V64S40ATP- 8A / 8 /1 0 2, 3 1, 2, 4, 8 100 / 100MHz - / 10ns - / 6ns 3ns 3ns Ins random 4 LVTTL 66 / 100MHz 15 / 10ns 9 / 8ns 3ns 3ns Ins A . MITSUBISHI ELECTRIC , 360.2ms 0.8 0.6 0.1 0.1 0.2 0.4 0.4 6.0 0.0 0.0 0.1 0.1 0.1 0.0 0.0 0.1 62.0 tRC=70ns,tCLK= 10ns , V dd=3.6 V,T a=25' C tRC=90ns,tCLK= 10ns , V dd=3.6 V,T a=25' C all banks idle,tCLK= 10ns ,Vdd=3.6V,Ta=25'C all banks idle,tCLK= 10ns ,Vdd=3.6V,Ta=25'C all banks active,tCLK= 10ns ,Vdd=3.6V,Ta=25'C all banks active


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PDF L-21028-0B 64MSDRAM L-21024-0A M5M4V64S20ATP 16Mx4 400mil 54pin M5M4V64S30ATP M5M4V64S40ATP
HYM7V64801

Abstract: No abstract text available
Text: 80h 256 Bytes SDRAM 2 Banks; 13 9 1 Bank 64 Bits LVTTL tCLK (A) 10ns (B) 12ns (C) 15ns tAC (A) 8ns (B) 9ns (C) 10ns None 15.625µs 08h 04h 0Dh 09h 01h 40h 00h 01h BYTE1 , Time from Clock @ /CAS Latency=3, @Cycle Time= 10ns @ /CAS Latency=3, @Cycle Time=12ns @ /CAS Latency , DESCRIBED FUNCTION SDRAM Access Time from Clock tAC (A) 9ns (B) 9ns (C) 10ns tCLK (A) 30ns (B , =30ns BYTE27 Minimum Row Pre-charge Time @/CAS Latency=3, @Cycle Time= 10ns @/CAS Latency=3, @Cycle Time


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PDF 8Mx64 HYM7V64800/ HYM7V64801/ HYM7V64830/ HYM7V64831 54-pin 168-pin HYM7V64801
1997 - AN07

Abstract: PDM31516 PDM41532 RC336 TMS320 RCDL56 accelerator rockwell modem
Text: 10ns 10ns 12ns 15ns 15ns 20ns 20ns PDM41532 PDM41532 PDM41532 PDM41532 PDM41532 PDM41532 PDM41532 10ns 10ns 12ns 15ns 15ns 20ns 20ns 32Kx16, 3 volt 10ns PDM31516 10ns PDM31516 12ns PDM31516 15ns PDM31516 15ns PDM31516 20ns PDM31516 20ns PDM31516 32Kx16, 5 volt 10ns PDM41516 10ns PDM41516 12ns PDM41516 15ns , PDM31256 PDM31256 PDM31256 PDM31256 PDM31256 10ns 10ns 12ns 15ns 15ns 20ns


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PDF AN-07 40-Bit 64Kx16 20KWord AN07 PDM31516 PDM41532 RC336 TMS320 RCDL56 accelerator rockwell modem
1998 - hym7v64801

Abstract: No abstract text available
Text: Banks; 13 9 1 Bank 64 Bits LVTTL tCLK (A) 10ns (B) 12ns (C) 15ns tAC (A) 8ns (B) 9ns (C) 10ns None 15.625µs 08h 04h 0Dh 09h 01h 40h 00h 01h BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 , =3, @Cycle Time= 10ns @ /CAS Latency=3, @Cycle Time=12ns @ /CAS Latency=3, @Cycle Time=15ns BYTE11 , from Clock tAC (A) 9ns (B) 9ns (C) 10ns tCLK (A) 30ns (B) 30ns (C) 30ns tAC (A) 24ns (B , Pre-charge Time @/CAS Latency=3, @Cycle Time= 10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency


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PDF 8Mx64 HYM7V64800/ HYM7V64801/ HYM7V64830/ HYM7V64831 54-pin 144-pin hym7v64801
1998 - HYM7V72A801

Abstract: HYM7V72A830
Text: tCLK (A) 10ns (B) 12ns (C) 15ns tAC (A) 8ns (B) 9ns (C) 10ns ECC 15.625µs 08h 04h 0Dh , Latency=3 BYTE10 SDRAM Access Time from Clock @ /CAS Latency=3, @Cycle Time= 10ns @ /CAS Latency , tAC (A) 9ns (B) 9ns (C) 10ns tCLK (A) 30ns (B) 30ns (C) 30ns tAC (A) 24ns (B) 24ns (C) 24ns , Time= 10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency=3, @Cycle Time=15ns BYTE28 Minimum Row Active to Row Active Delay @/CAS Latency=3, @Cycle Time= 10ns @/CAS Latency=3, @Cycle Time


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PDF 8Mx72 HYM7V72A800/ HYM7V72A801/ HYM7V72A830/ HYM7V72A831 72A801/ 72A830/ 72A831 54-pin HYM7V72A801 HYM7V72A830
HYM7V641601

Abstract: HYM7V641630
Text: 256 Bytes SDRAM 2 Banks; 13 10 1 Bank 64 Bits LVTTL tCLK (A) 10ns (B) 12ns (C) 15ns tAC (A) 8ns (B) 9ns (C) 10ns None 15.625µs 08h 04h 0Dh 0Ah 01h 40h 00h 01h BYTE1 BYTE2 , Clock @ /CAS Latency=3, @Cycle Time= 10ns @ /CAS Latency=3, @Cycle Time=12ns @ /CAS Latency=3, @Cycle , ] FUNCTION DESCRIBED FUNCTION SDRAM Access Time from Clock tAC (A) 9ns (B) 9ns (C) 10ns tCLK (A , Time=30ns BYTE27 Minimum Row Pre-charge Time @/CAS Latency=3, @Cycle Time= 10ns @/CAS Latency


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PDF 16Mx64 16Mx4 HYM7V641600/ HYM7V641601/ HYM7V641630/ HYM7V641631 54-pin 168-pin HYM7V641601 HYM7V641630
1998 - HYM7V641601

Abstract: No abstract text available
Text: Bytes 256 Bytes SDRAM 2 Banks; 13 9 2 Banks 64 Bits LVTTL tCLK (A) 10ns (B) 12ns (C) 15ns tAC (A) 8ns (B) 9ns (C) 10ns None 15.625µs / Self Refresh Supported 80h 08h 04h 0Dh 09h 02h 40h 00h 01h (A) A0h (B , ) F0h (C) F0h 2 1 3 BYTE10 SDRAM Access Time from Clock @ /CAS Latency=3, @Cycle Time= 10ns , Time @/CAS Latency=3, @Cycle Time= 10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency=3, @Cycle Time=15ns BYTE28 Minimum Row Active to Row Active Delay @/CAS Latency=3, @Cycle Time= 10ns @/CAS Latency


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PDF 16Mx64 HYM7V641600/ HYM7V641601/ HYM7V641630/ HYM7V641631 54-pin 168-pin HYM7V641601
2012 - DS-1135

Abstract: No abstract text available
Text: TOLERANCE (Note 1) ± 1.0ns ± 1.0ns ± 1.0ns ± 1.0ns ± 1.0ns ± 1.0ns ±1.5ns ±1.5ns TOLERANCE OVER TEMP AND VOLTAGE (Note 2) 0°C to +70°C -40°C to +85°C ± 1.0ns ±1.5ns ± 1.0ns ±1.5ns ± 1.0ns ±1.5ns ± 1.0ns ±1.5ns


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PDF DS1135 DS1135L DS1013 DS1035 DS1135Z DS1135 DS-1135
2002 - DS1135-20

Abstract: DS1135U DS1135M DS1135L DS1135-8 DS1135-6 DS1135-10 DS1135 DS1035 DS1013
Text: /30/30 INITIAL TOLERANCE (Note 1) ± 1.0ns ± 1.0ns ± 1.0ns ± 1.0ns ± 1.0ns ± 1.0ns ±1.5ns ±1.5ns TOLERANCE OVER TEMP AND VOLTAGE (Note 2) 0°C to +70°C -40°C to +85°C ± 1.0ns ±1.5ns ± 1.0ns ±1.5ns ± 1.0ns ±1.5ns ± 1.0ns ±1.5ns ±1.5ns ±2ns ±1.5ns ±2ns ±1.5ns ±2ns ±1.5ns ±2ns NOTES: 1


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PDF DS1135 150-mil) 118-mil) DS1135L) DS1013 DS1035 DS1135M DS1135-20 DS1135U DS1135L DS1135-8 DS1135-6 DS1135-10 DS1135 DS1035
1998 - HYM7V641601

Abstract: HYM7V641630
Text: 128 Bytes 80h 256 Bytes SDRAM 2 Banks; 13 9 2 Banks 64 Bits LVTTL tCLK (A) 10ns (B) 12ns (C) 15ns tAC (A) 8ns (B) 9ns (C) 10ns None 15.625µs 08h 04h 0Dh 09h 02h 40h 00h , SDRAM Access Time from Clock @ /CAS Latency=3, @Cycle Time= 10ns @ /CAS Latency=3, @Cycle Time=12ns @ , ) 9ns (C) 10ns tCLK (A) 30ns (B) 30ns (C) 30ns tAC (A) 24ns (B) 24ns (C) 24ns tRP (A) 30ns , /CAS Latency=1, @Cycle Time=30ns BYTE27 Minimum Row Pre-charge Time @/CAS Latency=3, @Cycle Time= 10ns


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PDF 16Mx64 HYM7V641600/ HYM7V641601/ HYM7V641630/ HYM7V641631 54-pin 168-pin HYM7V641601 HYM7V641630
1998 - HYM7V64400

Abstract: HYM7V64401 byte24 HYM7V64431
Text: tCLK (A) 10ns (B) 12ns (C) 15ns tAC (A) 8ns (B) 9ns (C) 10ns None 15.625µs 08h 04h 0Dh , Latency=3 BYTE10 SDRAM Access Time from Clock @ /CAS Latency=3, @Cycle Time= 10ns @ /CAS Latency , tAC (A) 9ns (B) 9ns (C) 10ns tCLK (A) 30ns (B) 30ns (C) 30ns tAC (A) 24ns (B) 24ns (C) 24ns , Time= 10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency=3, @Cycle Time=15ns BYTE28 Minimum Row Active to Row Active Delay @/CAS Latency=3, @Cycle Time= 10ns @/CAS Latency=3, @Cycle Time


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PDF 4Mx64 4Mx16 HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 54-pin 144-pin HYM7V64400 HYM7V64401 byte24 HYM7V64431
Not Available

Abstract: No abstract text available
Text: Latency=3 1 LVTTL tCLK 3 (A) 10ns (B) 12ns (C) 15ns tAC BYTE10 SDRAM Access Time from Clock @ /CAS Latervcy=3, @Cycle Time= 10ns @ /CAS Latency=3. @Cycle Time=12ns @ /CAS Latency=3, @Cycle , ) 8ns (B) 9ns (C) 10ns ECC 15.625ms / Self Refresh Supported x8 x8 tccD- 1 Latency 1,2,4,8,Full Page 2 , ) 9ns (C) 10ns tCLK (A) 30ns (B) 30ns 10ns @


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PDF 16MX72 HYM7V72A1600/ HYM7V72A1601/ HYM7V72A1630/ HYM7V72A1631 HVM7V72A1600/ 72A1601/ 72A1630/ 54-pin 168-pin
Not Available

Abstract: No abstract text available
Text: (A) 10ns (B) 12ns (C)15ns tAC 3 (A) AOh (B) COh (C) FOh 3 (A) 80h (B) 90h (C) AOh 00h 80h 08h 00h , Time= 10ns @ /CAS Latency=3, @Cycle Time=12ns @ /CAS Latency=3, @Cycle Time=15ns DIMM Configuration Type , (C) 10ns None 15.625(is / Self Refresh Supported x8 None tc c D = 1 Latency 1,2,4,8,Full Page 2 Banks , Latency=2, ©Cycle Time=15ns SDRAM Cycle Time @ /CAS Latency=1 FUNCTION tAC (A) 9ns (B) 9ns (C) 10ns , =3, @Cycle Time= 10ns @/CAS Lateney=3, @Cycle Time=12ns @/CAS Latency=3, ©Cycle Time=15ns Minimum Row Active


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PDF 16MX64 HYM7V641600/ HYM7V641601/ HYM7V64163Q/ HYM7V641631 HYM7V6416SX 54-pin 168-pin 7V64180
2005 - Not Available

Abstract: No abstract text available
Text: Number 20mA 20mA 20mA 10ns 10ns 10ns 10ns 10ns 10ns 40/60% 40/60% 40/60% IQVCXO-172 IQVCXO , -174 IQVCXO-174I 5V±0.25V 5V±0.25V 5V±0.25V ±50ppm min ±100ppm min ±200ppm min 40mA 40mA 40mA 10ns 10ns 10ns 10ns 10ns 10ns 40/60% 40/60% 40/60% Ordering Example Frequency Model number


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PDF IQVCXO-172, 15pF/10LS 25ppm, 50ppm 100ppm IQVCXO-172 50ppm, 100ppm IN4148
1998 - Not Available

Abstract: No abstract text available
Text: Time @ /CAS Latency=3 128 Bytes 256 Bytes SDRAM 2 Banks; 13 9 1 Bank 64 Bits LVTTL tCLK (A) 10ns (B) 12ns (C) 15ns tAC (A) 8ns (B) 9ns (C) 10ns None 15.625µs / Self Refresh Supported 80h 08h 04h 0Dh , /CAS Latency=3, @Cycle Time= 10ns @ /CAS Latency=3, @Cycle Time=12ns @ /CAS Latency=3, @Cycle Time , Pre-charge Time @/CAS Latency=3, @Cycle Time= 10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency=3, @Cycle Time=15ns BYTE28 Minimum Row Active to Row Active Delay @/CAS Latency=3, @Cycle Time= 10ns @/CAS


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PDF 8Mx64 HYM7V64800/ HYM7V64801/ HYM7V64830/ HYM7V64831 54-pin 168-pin
1998 - Not Available

Abstract: No abstract text available
Text: Bits LVTTL tCLK (A) 10ns (B) 12ns (C) 15ns tAC (A) 8ns (B) 9ns (C) 10ns ECC 15.625µs / Self Refresh , Access Time from Clock @ /CAS Latency=3, @Cycle Time= 10ns @ /CAS Latency=3, @Cycle Time=12ns @ /CAS , Time=30ns BYTE27 Minimum Row Pre-charge Time @/CAS Latency=3, @Cycle Time= 10ns @/CAS Latency , /CAS Latency=3, @Cycle Time= 10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency=3, @Cycle Time=15ns BYTE29 Minimum /RAS to /CAS Delay @/CAS Latency=3, @Cycle Time= 10ns @/CAS Latency=3, @Cycle Time


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PDF 16Mx72 HYM7V72A1600/ HYM7V72A1601/ HYM7V72A1630/ HYM7V72A1631 72A1601/ 72A1630/ 54-pin 168-pin
OP037

Abstract: st0006
Text: ) COh (C) FOh 3 (A) 80h (B) 90h (C) AOh OOh 80h 08h 00h 01h 8Fh 02h 07h 01 h 01h 00h 06h 2 (A) 10ns (B) 12ns (C) 15ns tAC BYTE10 SDRAM Access Time from Clock @ /CAS Latency=3, ©Cycle Time= 10ns @ , BYTE13 BYTE14 BYTE15 BYTE16 BYTE17 BYTE18 BYTE19 BYTE20 BYTE21 BYTE22 (A) 8ns (B) 9ns (C) 10ns None , [ HYM7V64800/HYM7V64830 F-Series; 2 Banks: Continued ] FUNCTION tAC (A) 9ns (B) 9ns (C) 10ns tCLK (A) 30ns (B , =30ns @ /CAS Latency=1, @Cycle Time=30ns Minimum Row Pre-charge Time @/CAS Latency=3, ©Cycle Time= 10ns @


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PDF 8MX64 HYM7V64800/ HYM7V64801/ HYM7V64830/ HYM7V64831 54-pin 168-pin 0022uF OP037 st0006
2001 - DS1013

Abstract: DS1135U DS1135M DS1135L DS1135-8 DS1135-6 DS1135-10 DS1135 DS1035 DS1135Z
Text: /30/30 INITIAL TOLERANCE (Note 1) ± 1.0ns ± 1.0ns ± 1.0ns ± 1.0ns ± 1.0ns ± 1.0ns ±1.5ns ±1.5ns TOLERANCE OVER TEMP AND VOLTAGE (Note 2) 0°C to +70°C -40°C to +85°C ± 1.0ns ±1.5ns ± 1.0ns ±1.5ns ± 1.0ns ±1.5ns ± 1.0ns ±1.5ns ±1.5ns ±2ns ±1.5ns ±2ns ±1.5ns ±2ns ±1.5ns ±2ns NOTES: 1


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PDF DS1135 150-mil) 118-mil) DS1135L) DS1013 DS1035 DS1135M DS1135U DS1135L DS1135-8 DS1135-6 DS1135-10 DS1135 DS1035 DS1135Z
HYM7V641601

Abstract: No abstract text available
Text: ) 90h (C) AOh 00h 80h 04h 00h 01h 8Fh 02h 07h 01 h 01 h 00h 06h 2 (A) 10ns (B) 12ns (C) 15ns tAC BYTE10 SDRAM Access Time from Clock @ /CAS Latency=3, @Cycle Time= 10ns @ /CAS Latency=3, @Cycle Time , , Precharge All, Auto Préchargé ) (A) 8ns (B) 9ns (C) 10ns None 15.625ns / Se# Refresh Supported x4 None , Row Pre-charge Time @/CAS Latency=3, ©Cycle Time= 10ns @/CAS Latency=3, ©Cycle Time=12ns ©/CAS Latency=3, @Cycle Time=15ns Minimum Row Active to Row Active Delay @/CAS Latency=3, ©Cycle Time= 10ns @/CAS Latency


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PDF 16MX64 64160Q S41631 7V641600/ 16Mx4 54-pin 168-pin 0022uF HYM7V841 HYM7V641601
1998 - BYTE18

Abstract: HYM7V72A1601 time-10ns tras 36ns
Text: tCLK (A) 10ns (B) 12ns (C) 15ns tAC (A) 8ns (B) 9ns (C) 10ns ECC 15.625µs 08h 04h 0Dh , Latency=3 BYTE10 SDRAM Access Time from Clock @ /CAS Latency=3, @Cycle Time= 10ns @ /CAS Latency , tAC (A) 9ns (B) 9ns (C) 10ns tCLK (A) 30ns (B) 30ns (C) 30ns tAC (A) 24ns (B) 24ns (C) 24ns , Time= 10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency=3, @Cycle Time=15ns BYTE28 Minimum Row Active to Row Active Delay @/CAS Latency=3, @Cycle Time= 10ns @/CAS Latency=3, @Cycle Time


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PDF 16Mx72 HYM7V72A1600/ HYM7V72A1601/ HYM7V72A1630/ HYM7V72A1631 72A1601/ 72A1630/ 54-pin 168-pin BYTE18 HYM7V72A1601 time-10ns tras 36ns
hym7v64801

Abstract: No abstract text available
Text: 80h 256 Bytes SDRAM 2 Banks; 13 8 2 Banks 64 Bits LVTTL tCLK (A) 10ns (B) 12ns (C) 15ns tAC (A) 8ns (B) 9ns (C) 10ns None 15.625µs 08h 04h 0Dh 08h 02h 40h 00h 01h BYTE1 , Time from Clock @ /CAS Latency=3, @Cycle Time= 10ns @ /CAS Latency=3, @Cycle Time=12ns @ /CAS Latency , DESCRIBED FUNCTION SDRAM Access Time from Clock tAC (A) 9ns (B) 9ns (C) 10ns tCLK (A) 30ns (B , =30ns BYTE27 Minimum Row Pre-charge Time @/CAS Latency=3, @Cycle Time= 10ns @/CAS Latency=3, @Cycle Time


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PDF 8Mx64 4Mx16 HYM7V64800/ HYM7V64801/ HYM7V64830/ HYM7V64831 54-pin 168-pin hym7v64801
HYM7V64801TFG1

Abstract: No abstract text available
Text: ) FOh NOTE 1 LVTTL tCLK 3 (A) 10ns (B) 12ns (C) 15ns tAC BYTE10 SDRAM Access Time from Clock @ /CAS Latency=3, @Cycle Time= 10ns @ /CAS Latency=3, @Cycle Time=12ns @ /CAS Latency , BYTE22 (A) 8ns (B) 9ns (C) 10ns None 15.625ns / Self Refresh Supported x8 None tccD=l Latency 1,2,4,8 , (C) AOh NOTE 3 (A) 9ns (B) 9ns (C) 10ns tCLK BYTE25 3 (A) 78h (B) 78h (C) 78h 3 (A) 60h , =30ns @ /CAS Latency=1, ©Cycle Time=30ns Minimum Row Pre-charge Time @/CAS Latency=3, @Cycle Time= 10ns @


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PDF 8MX64 HYM7V64800/ HYM7V64801/ HYM7V64830/ HYM7V64831 54-pin 168-pin 0022fiF HYM7V64801TFG1
HYM7V64401TRG -10

Abstract: HYM7V64401
Text: 10h OOh 01h 8Fh 02h 07h 01 h 01 h OOh 06h 2 (A) 10ns (B) 12ns (C)15ns tAC BYTE10 SDRAM Access Time from Clock @ /CAS Latency=3, @Cycle Time= 10ns @ /CAS Lateney=3, ©Cycle Time=12ns @ /CAS , BYTE19 BYTE20 BYTE21 BYTE22 (A) 8ns (B) 9ns (C) 10ns None 15.625ns / Self Refresh Supported x16 None , Latency=2, ©Cycle Time=15ns SDRAM Cycle Time @ /CAS Latency=1 BYTE25 (A) 9ns (B) 9ns (C) 10ns tCLK (A , Latency=3, ©Cycle Time= 10ns ©/CAS Latency=3, ©Cycle Time=12ns @/CAS Latency=3, ©Cycle Time=15ns Minimum


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PDF 4MX64 4Mx16 HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 54-pin TSQP11 HYM7V64401TRG -10 HYM7V64401
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