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T2059402101-000 TE Connectivity (T2059402101-000) HEEE-040-M
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th 20594

Abstract: HA 17723 30976 1982U 22024U
Text: 479.11 mU 2.5983 U 2.4497 U 2.3012 U 2.1201 U 2.0594 U 1.9705 U 1.8575 U 1.7848 U 1.722 U 6 NEC , production of the application system. No part of th is docum ent may be copied or reproduced in any form or by any m eans w ith o u t th e prio r w ritte n consent of NEC C orporation. NEC C orporation assum es no re sp o n sib ility fo r any e rro rs w h ich may appear in th is docum ent. NEC C orporation does not assum e any lia b ility fo r in frin g e m e n t of patents, c o p yrig h ts or o th e r


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PDF 2SC5288 2SC5288 SC-61 2SC5288-T1 th 20594 HA 17723 30976 1982U 22024U
2012 - th 20594

Abstract: mbc602
Text: following rules should be followed: V on RMS V th on V off RMS V th off (5) (6) Von(RMS) and


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PDF PCF8532 PCF8532 th 20594 mbc602
2012 - Not Available

Abstract: No abstract text available
Text: th  on  (5) V off  RMS   V th  off  (6) Von(RMS) and Voff(RMS) are


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PDF PCF8532 PCF8532
2012 - Not Available

Abstract: No abstract text available
Text: th  on  (5) V off  RMS   V th  off  (6) Von(RMS) and Voff(RMS) are


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PDF PCF85132 PCF85132
2012 - th 20594

Abstract: s130 x
Text: following rules should be followed: V on RMS V th on V off RMS V th off (5) (6) Von(RMS) and


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PDF PCA85132 PCA85132 th 20594 s130 x
2012 - th 20594

Abstract: serial LCD 27977
Text: following rules should be followed: V on RMS V th on V off RMS V th off (5) (6) Von(RMS) and


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PDF PCA85232 PCA85232 th 20594 serial LCD 27977
2012 - th 20594

Abstract: marking S125 serial LCD 27977
Text: following rules should be followed: V on RMS V th on V off RMS V th off (5) (6) Von(RMS) and


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PDF PCF85132 PCF85132 th 20594 marking S125 serial LCD 27977
2013 - Not Available

Abstract: No abstract text available
Text: following rules should be followed: V on RMS V th on V off RMS V th off (5) (6) Von(RMS) and


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PDF PCF85132 PCF85132
2013 - Not Available

Abstract: No abstract text available
Text: on RMS V th on V off RMS V th off (5) (6) Von(RMS) and Voff(RMS) are properties of the


Original
PDF PCF8532 PCF8532
2013 - Not Available

Abstract: No abstract text available
Text: following rules should be followed: V on RMS V th on V off RMS V th off (5) (6) Von(RMS) and


Original
PDF PCA85232 PCA85232 AEC-Q100
2013 - Not Available

Abstract: No abstract text available
Text: following rules should be followed: V on RMS V th on V off RMS V th off (5) (6) Von(RMS) and


Original
PDF PCA85132 PCA85132 AEC-Q100
2012 - Not Available

Abstract: No abstract text available
Text: th  on  (5) V off  RMS   V th  off  (6) Von(RMS) and Voff(RMS) are


Original
PDF PCA85132 PCA85132
Not Available

Abstract: No abstract text available
Text: th e e ig h t b its, PA 0-PA 1 can be set as I/O pins or buzzer outputs by m ask op­ tion. PA3 can , 8-bit Schm itt trigger in p u t port. Each b it on port are pull-high resistor. O f th e eight bits , capability. On th e port, such can be configured as CMOS output or NMOS input/output w ith or w ithout , ) for th e in te rn a l system clock. In th e case of RC operation, OSC2 is th e output term in al for , ratin g s only. Stresses exceeding th e range specified u n der "Absolute Maxi­ m um R atings" m ay


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PDF HT49C50
Not Available

Abstract: No abstract text available
Text: This c h a p te r describes two closely re la te d subjects, bus signals (Sections 5.1 and 5.2) and th , describe only th e a rc h ite c tu ra l c h aracteristics and functions of th e signals and bus cycles. The processor d ata sh e et defines th e setup and hold tim es for signals. T hroughout th is ch ap ter, unless otherw ise sta te d , th e term clock re fe rs to bus-clock (CLK) cycles, not , m ean th a t a signal is sam pled a sserted or sam pled n e g ated by its ta rg e t on th e signalâ


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PDF 18524C/0-Novi A31-A3 D63-D0
Not Available

Abstract: No abstract text available
Text: RGB624/RGB624DB 1.0 Microprocessor Access As seen on th e m icroprocessor bus th e re are eight I/O addresses, selected by RS[2:0]. Two indirect schemes are used to access all of th e in te rn a l registers and arrays through th ese eight prim ary I/O addresses. The first scheme is stan d ard VGA, and operates w hen RS[2] = 0. Of th e four I/O addresses th e n available w ith RS[1:0], only one address directly accesses a register, th e Pixel Mask. The oth er th re e addresses are used


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PDF RGB624/RGB624DB 256x8
Not Available

Abstract: No abstract text available
Text: HMCS6800 periph­ eral CMOS device w hich includes th e unique MOTEL concept for use w ith various micro­ processors, m icrocom puters, and large com ­ puters. This p art com bines th ree unique features: a com , uses. First, it is designed as b a tte y pow ered CMOS p art including all th e com mon b attery backed-up functions such as RAM, tim e, and calender. Secondly, th e HD146818A m ay be used w ith a CMOS microprocessor to relieve th e softw are of tim ekeeping w orkload and to ex ten d th e available RAM of an MPU


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PDF HD146818A--------------- HD146818A HMCS6800 FP-24) HD6801, HD6301 HD146818A HD146818A.
Not Available

Abstract: No abstract text available
Text: . Flexible control of co nstant-current or cu rren t-lim ited charging supply allows th e bq2004H to be th e , ffic ie n c y s w itc h e d c o n sta n t-c u rre n t re g u la tio n is ac complished using th e , application of Vcc to the bq2004H, rep lacem ent of th e b attery , or use of th e INH pin. F or safety, fast charge is inhibited u n til th e b a tte ry te m p e ra tu re and voltage are w ith in configured lim its. T em perature, voltage, and tim e are m onitored th ro u g h o u t fa st charge. F a s t charge is


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PDF 150-mil bq2004 bq2004H
BQ2011K

Abstract: No abstract text available
Text: discharge ac­ tivity of th e battery. The bq2011K is designed for systems such as power tools with very , e r a tu r e a n d r a t e of charge or discharge are applied to th e c h a r g e , d i s c h a r , g e of operating conditions. In itial b a tte ry capacity is se t using th e PROG 1-4 an d SPFC pins. A ctual b a tte ry c ap a c ity is a u to m a tic a lly “le a r n e d ” in th e c o u rse o f a d is ­ charge cycle from full to em pty and m ay be displayed depending on th e display mode


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PDF bq2011K 16-pin
Not Available

Abstract: No abstract text available
Text: , integrating th e 8 -b it AD converter based on th e TLCS-470 series. Part No. TM P47C660AN TMP47C660AF TM , pulse w id th m easurem ent mode W atchdog Tim er · · · · · · For a discussion o f ho w th e reliab ility o f m icrocontrollers can be predicted, please refer to Section 1.3 o f th e ch , rkin g to im prove th e q u ality and reliab ility o f its products. Nevertheless, semiconductor devices in general can m alfunction or fail due to th e ir in heren t electrical sensitivity and vu lnerab


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PDF TMP47C660A/860A P47C660AN P47C860AN TMP47C660AF, TMP47C860AF P47C660A/860A TLCS-470 TMP47C660AF
2012 - Not Available

Abstract: No abstract text available
Text: th  on  (5) V off  RMS   V th  off  (6) Von(RMS) and Voff(RMS) are


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PDF PCA85232 PCA85232
Not Available

Abstract: No abstract text available
Text: strong ally in fault-tolerant software. nless th e softw are in a m icroprocessorbased product can to , tte r how well th e h ard w are system is designed, some electrical noise alw ays gets through to cause softw are upsets. Also, no m a tte r how well th e softw are h as been tested and de bugged, softw , , som etim es th e processor sim ply locks up and all of the o u tp u ts freeze in th e ir cu rren t state. In o th er cases, th e p ro gram s continue to function b u t w ith erroneous a n d p o s s i b


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PDF e5-222. AP125,
Not Available

Abstract: No abstract text available
Text: variety of m em ory a n d I/O devices. P articu lar care h a s b e e n ta k e n in th e definition of th e control signals available to th e system designer. T hese signals allow th e system designer to im plem ent a m em ory interface appropriate to th e cost and perform ance goals of th e end application. T his c h a p te r includes b o th a n overview of th e read interface a n d provides detailed tim ing diagram s of th e read interface. TYPES OF READ TRANSACTIONS The m ajority of th e


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PDF R3041
RRU 3936

Abstract: TH 82420
Text: size: 3600 x 3940 (|_im)2 * The IC su b strate should be connected to VSS in th e PCB layout artw ork , su b strate should be connected to VSS in th e PCB layout artw ork. 5 July 16, 1999 HBLTEK , determ ine th e NMOS open drain output or schm itt trigger input. — N egative power supply, GND , structions determ ine th e CMOS output or schm itt I/O or None trigger in p u t w ith or w ithout a , Bidirectional 8-bit In p ut/O utput port. Software in ­ Pull-high structions determ ine th e CMOS output or


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PDF HT99C810/HT99C811 16-bit 224x8 RRU 3936 TH 82420
0x0016

Abstract: No abstract text available
Text: RGB526/RGB526DB 2.0 2.1 Clocking Clock Generators This causes th e SYSCLK s ta rt up , locked loop (PLL). The pixel clock generator provides th e fundam ental "dot" tim ings; it serves generally as th e clock both for in te rn a l chip clocking and for on-card CRT tim ings. The system clock generator is provided for th e conve nience of th e graphics subsystem design. No in te rn a l use is m ade of th is clock; th e clock generator simply drives th e SYSCLK o u tp u t of th e chip. FS[1:0] 00


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PDF RGB526/RGB526DB 0x008e 0x008f 0x008c 0x008d 0x0016
Not Available

Abstract: No abstract text available
Text: Description The MT8931B Subscriber N etw o rk Interface Circuit (SNIC) implements th e CCITT I.430 and ANSI T1.605 Recommendations fo r th e ISDN S and T reference points. Providing p o in t-to -p o in t a n d p o in t-to m u ltip o in t d ig ita l transm ission, th e SNIC may be used at eith er end o f th , which half o f th e S-interface fram e is currently being w ritte n /re a d over th e ST-BUS (HALF = 0 sampled on th e falling edge o f C4b w ith in th e fram e pulse lo w w in d o w , identifies th e in fo


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PDF MT8931B IS02-C 9161-002-171-NA
Supplyframe Tracking Pixel