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Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC3707EGN-SYNC#TR Linear Technology LTC3707-SYNC - High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C
LTC3707EGN-SYNC#PBF Linear Technology LTC3707-SYNC - High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C
LTC3707EGN-SYNC Linear Technology LTC3707-SYNC - High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C
LTC3707IGN-SYNC#PBF Linear Technology LTC3707-SYNC - High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C
LTC3707IGN-SYNC#TRPBF Linear Technology LTC3707-SYNC - High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C
LTC3707EGN-SYNC#TRPBF Linear Technology LTC3707-SYNC - High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C

sync video Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
AN6310

Abstract: S47k I3900 vtr modulator TS1514 Pre emphasis FM
Text: Input . 5 Clamp Input 17 Ree. VcC(Rec-) 6 ISIfflfl-f-tti^ Sync . Sep. Output 18 t-rtry-rtati Video Amp. Output 7 T—X GND 19 Video Amp. Input 8 Sync . Sep. Filter 20 MMWI± Vcc 9 FMitì^l FM Output 21 , =12V, Video Signal 0.5VP_P 0.45 1.05 Vp-p AGC illicit ¿»oiagc.24) 2 VCC= 12V, 0.25-1.0Vp_p 2 dB Sync , Oscillo-scop S5 Pin©aiÌJA;iE'Bl; iÜä i è iOPin© Aft fife ( Sync : Video =4:10) ■S6 AÌJ0.4Vp_p Test , _ 72C 08058 .D t^^ffllC AN6310 AN6310 77-47-// VTRfBlil&#if^&iI[aS&/VTR Recording Video


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PDF AN6310 AN63io AN6310 25-1-24-Lead 640pF b132A5a 47//F S47k I3900 vtr modulator TS1514 Pre emphasis FM
ZNA234

Abstract: ZNA234E Msi device* zna234 mixing video vertical diagram circuit diagram video receiver
Text: a minimum of external components for mixing the video , sync and blanking pulses to give a composite video signal. This can either be injected directly into the video stages of a receiver, or used to drive , MIXED MIXED SYNC . VIDEO BLANKING W CRYSTAL OSCILLATOR INPUT 2 555! System Diagram 28 , 525 line operation Crosshatch Dot • Sync and Blanking outputs to CCIR or IEA ., . standard , Greyscale Mixed Sync • Field reference output Mjxed vjdeo B,an|


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PDF ZNA234E ZNA234 ZNA234E Msi device* zna234 mixing video vertical diagram circuit diagram video receiver
ax464

Abstract: No abstract text available
Text: ~ 14 ^AAAr 7 5n FR O M O TH ER M AX484S Figure 7. Higher-Order RGB + Sync Video Multiplexer J , Figure 8. 1-of-4 RGB + Sync Video Multiplexer 8-36 AI^XIVM Two-Channel, Triple/Quad RGB Video Sw itches an d Buffers _ A pplications Inform ation H igher-O rder RGB + Sync Video M ultiplexing , Figure 8 shows a 1-of-4 RGB + sync video mux/amp circuit. The 1ki2 disabled output resistance limits the , Sync Video Multiplexing, above. MAX463-MAX4 70 8 Pin Configurations (continued) A I/X IA 1


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PDF witX465 MAX466 MAX464CWI MAX464C/D MAX464ENI MAX464EWI MAX465CNG MAX465CWG MAX465C/D MAX465ENG ax464
2012 - BD82HM76

Abstract: No abstract text available
Text: visual features, including Intel® Clear Video HD technology and Intel® Quick Sync Video , mean smoother visual quality, improved ability to decode and transcode simultaneous video streams, and , 4000: Enhanced, high-end media and graphics capabilities and performance. Intel® Quick Sync Video , for I decoding, encoding, and transcoding workloads with hardware acceleration of video codecs. Intel® Quick Sync Video 2.0 • mproved ability to decode and transcode simultaneous video streams


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PDF 0512/KSC/OCG/XX/PDF 327130-002US BD82HM76
AN6310

Abstract: fm modulator panasonic fk 32aS2
Text: fftr yr&J] Video Amp. Output 7 7—X GND 19 Video Amp. Input 8 Sync . Sep. Filter 20 Vcc 9 , »(XAGC24) Aftflt^O.SVp-p • ^WAGC24) Aflft-f 0.25VP-P, lVp-p« i è n&tlglt, ( Sync : Video =4:i0) Test , ©aiÌJA;iE'Bl; iÜä i è iOPin© Aft fife ( Sync : Video =4:10) ■S6 AÌJ0.4Vp_p Test Circuit 4 (GV2i , _ 72C 08058 .D t^^ffllC AN6310 AN6310 77-J7V/ YTR ^^iIIIIS&/VTR Recording Video Signal , functions consist of '• Video signal AGC circuit Pre-emphasis circuit FM modulator Synchro separator


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PDF AN6310 77-J7V/ AN63io AN6310IÃ -24-Lead 640pF 01//F AN6310 fm modulator panasonic fk 32aS2
video power line communication

Abstract: cameralink connector MDR-26 triad-01 camera-link 26PINS
Text: serial CameraLink video data, sync video data, sync SERTC SERFG serial CameraLink Duplicator CameraLink video slave output video data, sync Technical Specifications CameraLink , CameraLink Base video interface up to 24-bit data (Tap A, B and C) up to 66 MHz pixel clock duplicates a CameraLink video input stream into two video output streams: master and slave · master video output stream includes: video data and synchronisation one RS-232 channel control signals · slave video output stream


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PDF 24-bit RS-232 CL-24 24-bit 26-pins video power line communication cameralink connector MDR-26 triad-01 camera-link 26PINS
1999 - CONVERTER

Abstract: composite video converter sync to HSYNC and VSYNC converter HSYNC and VSYNC to sync converter component composite converter rgb to hsync vsync Hsync Vsync decoder RGB to composite video RGB signal converting to video signal Hsync Vsync generator
Text: Internal digital oscillator (no crystal required) Sync Video Timming Generator CLK Composite , W9950P digital video encoder converts digital R,G,B 24-bit data and YCrCb (4:2:2) 16-bit data into analog composite video and Y/C video signals. The video format is 525-line (M) NTSC or 625-line (B,D,G , generates the required video timing signals HSYNC and VSYNC and a FIELD signal according to the specified NTSC/PAL video standard. In slave mode, it accepts HSYNC and VSYNC input signals to synchronize with


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PDF W9950P W9950P 24-bit 16-bit 525-line 625-line CONVERTER composite video converter sync to HSYNC and VSYNC converter HSYNC and VSYNC to sync converter component composite converter rgb to hsync vsync Hsync Vsync decoder RGB to composite video RGB signal converting to video signal Hsync Vsync generator
2011 - max470cpe

Abstract: Video Switches arrays 5 transistor dip.16 MAX470CWE
Text: FROM OTHER MAX464s 75 Figure 7. Higher-Order RGB + Sync Video Multiplexer , GND IN3B V+ OUT3 +5V 75 13 14 15 22 75 Figure 8. 1-of-4 RGB + Sync Video , + Sync Video Multiplexing Higher-order RGB video multiplexers can be realized by paralleling , Switch 1-of-4 RGB + Sync Signal Inputs Figure 8 shows a 1-of-4 RGB + sync video mux/amp circuit. The 1k , section Higher Order RGB + Sync Video Multiplexing, above. MAX463­MAX470


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PDF 100MHz 90MHz MAX463 MAX470 MAX464CNI MAX465 MAX466 MAX466 MAX464CWI MAX464C/D max470cpe Video Switches arrays 5 transistor dip.16 MAX470CWE
2014 - Not Available

Abstract: No abstract text available
Text: / ITU 624-4 blackburst SMPTE 274M / SMPTE 296M tri-level sync Video Processing Performance Signal , reference. The reference signal can be an analog blackburst, trilevel sync or the internal URS frame , video signals at the output of a router and prevent downstream video glitches. Using the appropriate , video input format Flexible external reference or internal URS frame reference input Clean output on video input “hot switches” within a 10-line window • • • • Output timing can be


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PDF LNS-3901 LNS-3901 REF-1801. LNS-3901-3SRP LNS-3901-3SRP-R GVB-1-0401B-EN-DS
Block diagram on monochrome tv receiver

Abstract: AY-3-9735 BC box TS01 TS10 TS11 earth leakage rd2
Text: of video is approximately 16/js after the negative edge of line sync . 37 Comp Sync Output Open-drain , Input The composite sync input monitors the composite sync / video being received and extracts , Video Generator is aware of the status of the mixed sync at all times the chip can detect frame sync , is defined below. Line Sync — The Composite Video Input must be negative for greater than 3/js. Frame Sync — The Composite Video Input-must be negative for greater than 12/asand at least 310 lines


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PDF AY-3-9735 -32aiA 320juA 100pf Block diagram on monochrome tv receiver AY-3-9735 BC box TS01 TS10 TS11 earth leakage rd2
Block diagram of monochrome tv receiver

Abstract: MR9735 PIC1650-532
Text: Com posite sync , input monitors the composite sync / video being received and extracts synchronising , trans mission. Because the Video Generator is aware of the status of the mixed sync , at all times the , to the television, either composite sync , signals or video being acceptable. As the Composite Sync , chip. A typical Interface Circuit is shown in Fig.3. COMPOSITE SYNC / VIDEO (TELEVISION) COMPOSITE SYNC , negative for greater than 3jus. 2. Frame Sync . The Com p. Video Input must be negative for greater


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PDF 000T3S3 MR9735 Block diagram of monochrome tv receiver MR9735 PIC1650-532
MN67762

Abstract: GRITT-2 Polygon sync video MN6776 graphics processor Am3 diagram
Text: Interlace to progressive conversion Video sync . Video pixel format 8, 16, 32 bit/pixel Color , GRiTT-2 MN67762 Video Output (Analog/Digital) Geometry Processor (FPU) Video-Out Engine , Display Video Input 1 Video Input 2 Audio I/F HOST I/F PCI I/F Memory (Main) Memory I/F , 80 MHz (Maximum, depends on screen size) Rendering performance 400 Mpixels/sec. (peak) Video , Video Output Analog RGB output 8-bit (80 MHz) DAC × 3-ch Digital RGB output 8-bit × 3


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PDF MN67762 64Mbyte 16-bit 1/48kHz 417-pin MN67762 GRITT-2 Polygon sync video MN6776 graphics processor Am3 diagram
ZNA134J

Abstract: IN625 interlace ZNA134
Text: subtract clock oso El_IL_GL ' aooition circuits. TS -m—H Ej mode mixed mixeo sync video blanking


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PDF ZNA134J ZNA134J 5625MHz* IN625 interlace ZNA134
ZNA134J

Abstract: No abstract text available
Text: RESET FIELD BLANKING ADD SUBTRACT CLOCK OSC.1 OV MODE MIXED MIXED LINE HORIZONTAL Vcc CRYSTAL SYNC VIDEO DRIVE RESET OSC. 2 BLANKING 1 ' Sliz System Diagram 27


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PDF ZNA134J ZNA134J
Not Available

Abstract: No abstract text available
Text: shaping o f 3 V/l ADJ F/V VOLOUT FA/ DET FA/ M .M TIMING SYNC HOLD SYNC ON VIDEO IN SYNC DET. GND HD , ) ty p e s o f sync signal input: separate sync (p o sitive /n e g a tive p olarities 1 ~ 5 V p-p), co m p o site sync (p o sitive /n e g a tive po larities 1 ~ 5V P -p ia n d sync video ( sync negative). , -M .M -T IM IN G F /V M.M TIMINNG SYNC ON VIDEO IN HD/CO M P.D ET. V D -M .M -T IM IN G , MITSUBISHI ICs (TV) M52001SP SYNC SIGNAL PROCESSOR DESCRIPTION The M52001SP is a s e m ico n


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PDF M52001SP M52001SP
MM5322N

Abstract: MM5322 1k trimpot vertical 10k trimpot vertical color bar generator BCD8 trimpot horizontal
Text: Times FIGURE 4. Composite Video Pulse Timing, Horizontal Sync Mj lUULP^ 255.23784ms MAX I 111.74564m , . Composite Video Pulse Timing, Vertical Sync VIDEO OUT HORIZONTAL SYNC 0.2ms _ MIT) TRIGGER OUTPUT HORZT , (crystal controlled) frequency to provide the various timing, synchronization, and video information required in the alignment of color television receivers. A composite video output is provided for complete black and white dot-bar operation. It consists of all synchronization, blanking, and video information


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PDF MM5322 MM5322N 1k trimpot vertical 10k trimpot vertical color bar generator BCD8 trimpot horizontal
1995 - 4P2T switch

Abstract: MAX468 MAX467 MAX466 MAX465 MAX464 MAX463 MAX468CPE 4p2t MAX470CWE
Text: +5V 15 75 FROM OTHER MAX464s Figure 7. Higher-Order RGB + Sync Video Multiplexer , -of-4 RGB + Sync Video Multiplexer 14 75 +5V 75 1 75 17 IN3B 75 75 ­5V 22 , 1-of-4 RGB + Sync Signal Inputs Higher-Order RGB + Sync Video Multiplexing Figure 8 shows a 1-of-4 RGB + sync video mux/amp circuit. The 1k disabled output resistance limits the number of paralleled , . For multiplexing more than two devices, see the section Higher Order RGB + Sync Video Multiplexing


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PDF 100MHz 90MHz MAX463CNG MAX469EWE MAX470CPE MAX470CWE MAX470C/D MAX470EPE MAX470EWE MAX464CNI 4P2T switch MAX468 MAX467 MAX466 MAX465 MAX464 MAX463 MAX468CPE 4p2t MAX470CWE
2011 - FCBGA989

Abstract: FCBGA1023 BD82HM65 FCPGA988 CPU Intel Core i5-6500TE FCBGA-989
Text: performance for signal and image processing applications. Intel® Quick Sync Video : Improves media/ video , consumption. Intel® Quick Sync Video Technology Speeds up video conversion, editing and sharing for embedded applications such as video surveillance. Automated low-power states Adjusts system power consumption based on real-time processor loads. Intel® Clear Video HD Technology Visual quality and


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PDF 2710QE, 2715QE, 2655LE, 2610UE) 2510E, 2515E) 2310E) 0111/KSC/OCG/XX/PDF 324537-003US FCBGA989 FCBGA1023 BD82HM65 FCPGA988 CPU Intel Core i5-6500TE FCBGA-989
2006 - Video Sync Separator

Abstract: sync separator Hsync Vsync composite PAL/Secam DB1800 "frame grabber" csync hsync vsync
Text: Digital Blocks DB1800 NTSC/PAL/SECAM Video Sync Separator Semiconductor IP General Description The Digital Blocks DB1800 Video Sync Separator IP Core extracts timing information from a standard NTSC/PAL/SECAM composite sync video signal. The DB1800 extracts horizontal sync , vertical sync , , PAL, or SECAM video signal. Output of following signals: o horizontal sync o vertical sync o , DB1800-DS-V1.0 1 8/30/2008 Digital Blocks, Inc. DB1800 NTSC/PAL/SECAM Video Sync Separator Pin


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PDF DB1800 DB1800 p1800 DB1800-DS-V1 Video Sync Separator sync separator Hsync Vsync composite PAL/Secam "frame grabber" csync hsync vsync
Block diagram on monochrome tv receiver

Abstract: SL9100 Block diagram of monochrome tv receiver MR9735 MR9735-002 PIC1650-532 viewdata MR9735-005 TS10 block diagram of coloured t.v
Text: of video is approximately 1Qus after the negative edge of line sync . 37 Comp. Sync . Output This , composite sync . 38 Comp. Sync . Input The Composite sync , input monitors the composite sync / video being , Video Generator. Similarly if the normal transmission resumes, the fact that external sync pulses are , incoming transmission. Because the Video Generator is aware of the status of the mixed sync , at all times , criteria for detection is defined below. 1. Line Sync The Comp. Video Input must be negative for greater


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PDF MR9735 Block diagram on monochrome tv receiver SL9100 Block diagram of monochrome tv receiver MR9735 MR9735-002 PIC1650-532 viewdata MR9735-005 TS10 block diagram of coloured t.v
Not Available

Abstract: No abstract text available
Text: conversion rate • RS-343-A compatible • Complete video controls: Sync , Blank, Bright and Reference , accepting video data at 400 MWPS. Complete with video controls — Sync , Blank, Reference White (Force , temperature and /883 versions. BLOCK DIAGRAM Sync , Blank, Bright, Ref – White Video Controls In 4 , controls — Sync , Blank, Reference White (Force High) and Bright — are needed in video applications , €“ 4 FH Video Control Inputs 4 Register Sync Video Data Inputs Output Current


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PDF SPT5140 RS-343-A SPT5140SIN
LM1822

Abstract: TM01-1T 13-AGC LM1823N SAF45MC AV16 LM1823 N28B TM011
Text: compares the negative sync tips of noise-averaged pin 17 video with an internal 4V reference. Increases in , negative sync video . With no detector input signal the pin 16 voltage sits at the zero carrier level , sync pulses are normally the most negative portion of the recovered video . 12V 10k > ■wap-^ : 5k , -AGC Comparator Input: External negative sync video is fed to the AGC comparator and gate generator via pin 17. An , suppressed sync systems, the recovered video at pin 16 may require processing to restore normal sync


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PDF LM1823 28-Detector TL/H/5222-5 LM1822 TM01-1T 13-AGC LM1823N SAF45MC AV16 N28B TM011
Not Available

Abstract: No abstract text available
Text: , Intel® Turbo Boost , Dynamic Turbo, Intel® AVX 1.0, Intel® Quick Sync Video Bus Interfaces , bus, SMBus (system), I2C (user) Video Integrated in Processor HD Graphics 4000 at 350-1000 MHz Integrated Video DirectX 11.0, OpenGL 3.1, and OCL 1.1 Media Processing Decode (HW JPEG & MJPEG decode), encode (full HW MPEG2 encode), transcode Intel® Clear Video HD Technology + enhanced media processing


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PDF PCI/104-Express PCI/104, PC/104 PC/104-Plus 1600MHz 18/24-bit PCI/104
2009 - gf9450

Abstract: picture-in-picture motion interpolation "Frame rate conversion"
Text: Scaler Frame Sync Video Mixer OSD Mixer Region Based Picture Level Control ath 2 , Scaler Frame Sync Output Signal Timing Generator Digital Video Interlace Digital Video Output , players/recorders Two independent channels of VXP® processing ·Supports all DTV video and PC graphics formats ·Provides two flexible 30-bit digital video input ports ·Supports active raster size up to , ·Multi-tap scaling engine with panoramic scaling and aspect ratio conversion ·Multiple on-screen video


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PDF GF9450 10-bit 30-bit 2048x2048 gf9450 picture-in-picture motion interpolation "Frame rate conversion"
sweep generator

Abstract: C503 MC13011 MC1301
Text: and negative sync video outputs are produced, FIGURE 4 - PIN 2 VIDEO OUTPUT WITH WHITE-SPOT , White'Spot Clamp Level -t ,$,. ,L, FIGURE 5 - PIN 3 VIDEO OUTPUT FOR DRIVE TO A SYNC SEPARATOR &S , 1.3 1.1 - Tk:$#&&tive sync output is intended to be used as th~,a:~ti~l video and is acted , and defocused, The positive sync video output is not acted on by a white spot noise inverter and of , produce optimum sync performance. Note the sense of the video signals at' the outputs remain the same


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PDF MC1301 MC13011 MC13011 751E-07 sweep generator C503
Supplyframe Tracking Pixel