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SRIO-E3-UT1 Lattice Semiconductor Corporation SITE LICENSE SRIO 2.1 ECP3
SRIO-E3-U1 Lattice Semiconductor Corporation IP CORE SRIO 2.1 ENDPOINT ECP3

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srio datasheet (2)

Part Manufacturer Description Type PDF
SRIO-E3-U1 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE SRIO 2.1 ENDPOINT ECP3 Original PDF
SRIO-E3-UT1 Lattice Semiconductor Software, Programmers, Development Systems, SITE LICENSE SRIO 2.1 ECP3 Original PDF

srio Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2011 - Not Available

Abstract:
Text: : www.IDT.com/go/ SRIOGen2 DSP S-RIO 2 Military Open VPX System SOFTWARE AND HARDWARE ECOSYSTEM â , x4 S-RIO Backplane x4 S-RIO CPS-1616 RapidIO Switch x1 S-RIO FemtoClock® NG 156.25 MHz MAC Layer + Control Processor x1 S-RIO x4 S-RIO x1 S-RIO FPGA S-RIO CPS-1616 RapidIO Switch DSP S-RIO 2 DSP S-RIO 2 DSP S-RIO 2 PowerPC S-RIO CPS-1848 RapidIO Switch FemtoClock® NG 156.25 MHz FemtoClock® NG 156.25 MHz S-RIO 24 x 4 Switch Card S-RIO


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PDF CPS-1616 16-Port, 16-Lane REVC0211
2011 - Not Available

Abstract:
Text: S-RIO x4 S-RIO Discover what IDT know-how can do for you: www.IDT.com/go/ SRIOGen2 DSP S-RIO 2 , PHY Processing x4 S-RIO Backplane x4 S-RIO CPS-1848 RapidIO Switch SOFTWARE AND HARDWARE , IBIS models x4 S-RIO FemtoClock® NG 156.25 MHz MAC Layer + Control Processor x4 S-RIO x4 S-RIO DSP S-RIO 2 DSP S-RIO 2 x4 S-RIO FPGA S-RIO RapidIO Switch DSP S-RIO 2 PowerPC S-RIO S-RIO 24 x 4 Switch Card S-RIO Payload Card Imaging Application RapidIO Switch


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PDF CPS-1848 REVE0211
2010 - CPS-1848

Abstract:
Text: Switch x4 S-RIO x4 S-RIO Discover what IDT know-how can do for you: www.IDT.com/go/ SRIOGen2 , / CBSAI FPGA or ASIC OFDMA PHY Processing x4 S-RIO Backplane x4 S-RIO CPS-1848 RapidIO , ·HSPICE and IBIS models x4 S-RIO FemtoClock® NG 156.25 MHz MAC Layer + Control Processor x4 S-RIO x4 S-RIO DSP S-RIO 2 DSP S-RIO 2 x4 S-RIO FPGA S-RIO RapidIO Switch DSP S-RIO 2 PowerPC S-RIO S-RIO 24 x 4 Switch Card S-RIO Payload Card Imaging Application


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PDF CPS-1848 REVC0910 CPS 1848 srio 1848 4x4 calculator LTE ANTENNA GUIDE radar distance REVC0910
2010 - CPS-1848

Abstract:
Text: Discover what IDT know-how can do for you: www.IDT.com/go/ SRIOGen2 DSP S-RIO 2 Military Open VPX , Antenna Interface CPRI / CBSAI FPGA or ASIC OFDMA PHY Processing x4 S-RIO Backplane x4 S-RIO CPS-1616 RapidIO Switch x1 S-RIO FemtoClock® NG 156.25 MHz MAC Layer + Control Processor x1 S-RIO x4 S-RIO x1 S-RIO FPGA S-RIO CPS-1616 RapidIO Switch DSP S-RIO 2 DSP S-RIO 2 DSP S-RIO 2 PowerPC S-RIO CPS-1848 RapidIO Switch FemtoClock® NG 156.25 MHz


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PDF CPS-1616 16-Port, 16-Lane REVB0610 CPS-1848 srio Application of dsp in military sonar CPS1616 4x4 calculator CPS 1848
2011 - Not Available

Abstract:
Text: errors x86 Processor + PCIe2 to S-RIO2 Bridge S-RIO CPU x4 PCIe PCIe Switch x4 P PCIe , /monitors Dedicated maintenance path for “5th priority” Error Management features exceeding S-RIO , S-RIO links, 1 with three 4x S-RIO links, AMC.0 and AMC.4 Specification (NO support on IPMC and JTAG) • 2 SFP+ Connectors: 1 ports with 1x S-RIO link, INF-8341 Specification • 1 QSFP Connectors: 1 port with 4x S-RIO link, SFF-8438i Specification • 2 InfiniBand/CX4 Connectors: 1 port


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PDF REVB0311
2007 - srio

Abstract:
Text: . Unicast: All other operations are performed as specified in sRIO. c. Maintenance packets: As specified in sRIO. The core of the Pre-Processing Switch are the Packet Processing Scenarios. The PPScs perform a , generation per sRIO packet Packet Trace ­ Each Port provides the ability to match the first 160 bits of , Scenarios (PPSc) u Interfaces - sRIO ­ 12 Serial RapidIO ( sRIO ) v 1.3 full duplex lanes ­ Lane Rates , software) ­ sRIO Multicast support (10 simultaneous masks) ­ Support for 4 sRIO priorities ­ Port


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PDF 80KSW0001 80KSW0001 80KSW001 srio IDT70K2000
2010 - Not Available

Abstract:
Text: to S-RIO2 CPS-1432 x86 CPU Tsi721 PCIe2 to S-RIO2 S-RIO Switch 18x1,18x2, 12x4 Rapid , Application x4 S-RIO Backplane p Antenna Interface CPRI/OBSAI x4 S-RIO Tsi721 PCIe2 to S-RIO2 x4 , Integrated DeviceTechnology Integrated DeviceTechnology Tsi721 PCIe2 to S-RIO2 Protocol , LOGIC | TOUCH & USER INTERFACE | VIDEO & DISPLAY | AUDIO FEATURES • x4 PCIe V2.1 to x4 S-RIO V2 , • Reach Support: 60 cm over 2 connectors • 100, 125, 156.25 MHz S-RIO and PCIe Endpoint


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PDF Tsi721 REVD0711
2011 - Not Available

Abstract:
Text: x4 S-RIO Discover what IDT know-how can do for you: www.IDT.com/go/ SRIOGen2 DSP S-RIO 2 , ) Wireless Application Antenna Interface CPRI / CBSAI FPGA or ASIC OFDMA PHY Processing x4 S-RIO Backplane x4 S-RIO SOFTWARE AND HARDWARE ECOSYSTEM • Serial RapidIO Development Platform Gen2 , support • Power Calculator tool • HSPICE and IBIS models x4 S-RIO CPS-1432 RapidIO Switch FemtoClock® NG 156.25 MHz MAC Layer + Control Processor x4 S-RIO x4 S-RIO x4 S-RIO DSP


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PDF CPS-1432 REVA0311
2010 - e500v2

Abstract:
Text: Mezzanine DDR II DDR SRIO /PCIe 4x SRIO /PCIe MUX LB DDR III Mini-USB SRIO 4x 4x SRIO SRIO I2C USB IPMB-L UART I2C Mezzanine DDR III Port 8:11 Port 17:20 4x eSDHC SRIO /PCIe Port 12:15 SRIO GigE Memory Card FPGA MSC8156 DDR DDR GigE GigE sRIO sRIO UART I2C Ethernet Port 4:7 MUX SRIO Switch SRIO Ethernet 1000 Base-X 4x SOCDIMM Flash Port 0 Port 1 P2020 GigE GigE PCIe/ sRIO


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PDF P2020-MSC8156 P2020-MSC8156 P2020, MSC8156 P2020MSC8156RDFS e500v2 P2020 RGMII switch p2020 processor registers MSC8156 datasheet fpga rgmii DDR2-1600 P2020MSC8156RDFS RGMII
2009 - 80KSW0004

Abstract:
Text: DSPs, processors, FPGAs, other switches, or any other sRIO-based devices. It may also be used in , performed as specified in sRIO. c. Maintenance packets: As specified by sRIO. If there is no match, the , . Features Interfaces - sRIO ­ 12 bidirectional serial RapidIO ( sRIO ) lanes v 1.3 ­ Port Speeds , Forward data flow ­ Device configurable through any of sRIO ports, I2C, or JTAG ­ Packet Trace/Mirror , configurable as line card, or backplane ports. It is an end-point free (switch) device in an sRIO network


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PDF 12-Port CPS-12, IDT80KSW0004, CPS-12 125Gbps, 25Gbps 80KSW0004 IDT80KSW0004
2009 - backplane cps-16

Abstract:
Text: , processors, FPGAs, other switches, or any other sRIO-based devices. It may also be used in serial RapidIO , Interfaces - sRIO ­ 16 bidirectional serial RapidIO ( sRIO ) lanes v 1.3 ­ Port Speeds selectable: 3.125Gbps , Performance ­ 40 Gbps of peak switching bandwidth ­ Non-blocking data flow architecture within each sRIO , of sRIO ports, I2C, or JTAG ­ Packet Trace/Mirror/Filter. Per-port line rate copy or filter of all , ) device in an sRIO network. The CPS-16 receives packets from up to 16 ports. The CPS-16 offers full


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PDF 16-Port CPS-16, 80KSW0002, CPS-16 125Gbps, 25Gbps backplane cps-16 80KSW0002 LN12 srio CPRI
2006 - pcb thermal Design guide pcb trace

Abstract:
Text: Serial Rapid I/O ( SRIO ) interface on the TMS320TCI6482 DSP device. The approach to specifying interface timing and physical requirements for the SRIO interface is quite different than previous approaches for , analog nature of SRIO , it is not possible to specify the interface in a traditional DSP digital , requirements laid out by the SRIO specification. Understanding the SRIO specification and producing a , , and expensive tools. For the TMS320TCI6482 SRIO interface, the approach is to reduce the


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PDF TMS320TCI6482 pcb thermal Design guide pcb trace pcb layout guide differential ohms stackup TMS320TCI100 SPRU811A Serial RapidIO Infiniband RG316 RG178 RG142 A 434 RF Receiver TRANSMITTER PAIR
2009 - 80KSW0003

Abstract:
Text: , processors, FPGAs, other switches, or any other sRIO-based devices. It may also be used in serial RapidIO , : All other operations are performed as specified in sRIO. c. Maintenance packets: As specified by sRIO. , optional broadcast) from any of its 8 input ports to any of its 8 output ports. Interfaces - sRIO ­ 8 bidirectional serial RapidIO ( sRIO ) lanes v 1.3 ­ Port Speeds selectable: 3.125Gbps, 2.5Gbps, or 1.25Gbps ­ , Gbps of peak switching bandwidth ­ Non-blocking data flow architecture within each sRIO priority ­


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PDF 80KSW0003, 125Gbps, 25Gbps 80KSW0003 324-ball
2007 - IDT80KSW0004

Abstract:
Text: DSPs, processors, FPGAs, other switches, or any other sRIO-based devices. It may also be used in , operations are performed as specified in sRIO. c. Maintenance packets: As specified by sRIO. If there is , . Features Interfaces - sRIO ­ 12 bidirectional serial RapidIO ( sRIO ) lanes v 1.3 ­ Port Speeds , architecture within each sRIO priority ­ Very low latency for all packet length and load condition ­ Internal , Device configurable through any of sRIO ports, I2C, or JTAG ­ Packet Trace: Each port provides the


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PDF 12-Port CPS-12, IDT80KSW0004, CPS-12 125Gbps, 25Gbps IDT80KSW0004 80KSW0004 PCIE SWITCH IDT SRIO
2009 - 80HFC1000

Abstract:
Text: any other sRIO-based devices. It may also be used in serial RapidIO backplane switching. The CPS , specified in sRIO. c. Maintenance packets: As specified in sRIO. 2) Enhanced Functions Enhanced features , 60 Gbps of peak switching bandwidth Non-blocking data flow architecture within each sRIO priority , any of sRIO ports, I2C, or JTAG ­ Packet Trace/Mirror/Filter. Per-port line rate copy or filter of , 16 input ports to any of its 16 output ports. 2 Features Interfaces - sRIO 24 bidirectional


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PDF 80KSW0006 80HFC1000 tdm RECEIVER CPS-6Q CPRI 80HFC1001 CPS-10Q 80KSBR201 80KSW0006 srio
2006 - MSC8144EPB

Abstract:
Text: serial RapidIO interface or Ethernet. sRIO MSC8144E sRIO MSC8144E TDM 1xsRIO 4x/1x sRIO ETH ETH ETH I 2C UTOPIA 4x/1x sRIO PCI MSC8144E TDM ETH ETH I 2C UTOPIA PCI DDR sRIO TDM ETH PCI DDR I2C UTOPIA DDR 1xsRIO DDR SDRAM ETH sRIO DDR SDRAM MSC8144E sRIO MSC8144E TDM 1000Base-T ETH ETH ETH I 2C PCI DDR DDR SDRAM sRIO UTOPIA TDM ETH ETH I 2C UTOPIA PCI TDM


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PDF MSC8144EPB MSC8144E MSC8144EPB MPC8347E MSC8144 SC140 SC1400 SC3400 the RMII Consortium Specification VOCODERS voip
2007 - 8-port GbE PHY

Abstract:
Text: , processors, FPGAs, other switches, or any other sRIO-based devices. It may also be used in serial RapidIO , performed as specified in sRIO. c. Maintenance packets: As specified by sRIO. serial RapidIO ports. The , optional broadcast) from any of its 8 input ports to any of its 8 output ports. Interfaces - sRIO ­ 8 bidirectional serial RapidIO ( sRIO ) lanes v 1.3 ­ Port Speeds selectable: 3.125Gbps, 2.5Gbps, or 1.25Gbps ­ , Gbps of peak switching bandwidth ­ Non-blocking data flow architecture within each sRIO priority ­


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PDF 80KSW0003, 125Gbps, 25Gbps 8-port GbE PHY 80KSW0003
2008 - pcb thermal Design guide pcb trace

Abstract:
Text: Disabled. Loss-of-signal detection not used in SRIO. 13:12 ALIGN 01 Comma Alignment. SRIO uses , instructions for the Serial RapidIO® ( SRIO ) interface on the TMS320TCI6486/TMS320C6472 DSP device. The approach to specifying interface timing and physical requirements for the SRIO interface is quite , digital bus design. Due to this analog nature of the SRIO , it is not possible to specify the interface in , in terms of the raw physical requirements laid out by the SRIO specification. Understanding the SRIO


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PDF TMS320C6472/TMS320TCI6486 TMS320TCI6486/TMS320C6472 pcb thermal Design guide pcb trace RAPIDIO RG142 RG178 RG316 SPRU811 stackup TMS320TCI6486
2012 - 8535-01

Abstract:
Text: LP-HCSL1 PCIe G1/G2, SGMII, sRIO 1x / 2x SATA / SATA3G Input Qty Input Type Output Qty , /G2/G3, 1.25 / 2.5 / 3.125 / 5 / 10; 1.5 / 3” SGMII 1x/2.5x, sRIO 1x/1.25x/2x SATA/SATA3G , DIF HCSL 5 - 166 PCIe G1/G2/G3, sRIO 1x/2x SATA/SATA3G 2.5 / 5/8; 1.5 / 3” 1 DIF/ 1 , , sRIO 1x/1.25x/2x SATA/SATA3G, XAUI, XAUI 10G 1.25 / 2.5 / 3.125 / 5 / 8 / 10; 1.5 / 3.0 (SATA) 1x 25 REF / 1x 50 REF LVCMOS / LVTTL * PCIe G1/G2, SGMII 1x / 2.5x, sRIO 1x / 1.25x / 2x


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PDF REVA0112 8535-01
2009 - CPS-10Q

Abstract:
Text: for distribution among DSPs, processors, FPGAs, other switches, or any other sRIO-based devices. It , for broadcast. b. Unicast: All other operations are performed as specified in sRIO. c. Maintenance packets: As specified in sRIO. 2) Enhanced Functions Enhanced features are provided for support of , output ports. 2 Features Interfaces - sRIO 40 bidirectional serial RapidIO ( sRIO ) lanes v 1.3 , Performance 100 Gbps of peak switching bandwidth Non-blocking data flow architecture within each sRIO


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PDF 80KSW0005 CPS-10Q, 80KSW0005, CPS-10Q 125Gbps, 25Gbps SRIO40 CPS10Q 80KSW0005 cpri SRIO
2013 - Not Available

Abstract:
Text: DSC571-04 Crystal-less™ XAUI/SGMI/ SRIO /PCIe Clock Generator General Description Features The DSC571-04 is a Crystal-less™ XAUI clock generator with support for SGMI, SRIO and PCI express , : 156.25MHz (LVPECL) o SGMI/ SRIO : 125MHz (LVPECL) o PCIe: 100MHz (HCSL)  XAUI, SGMI, SRIO & , SGMI/ SRIO requirements. Clk2 +/- is 156.25MHz per XAUI standards. For other frequencies, please , _ DSC571-04 Page 1 Crystal-less™ XAUI/SGMI/ SRIO /PCIe Clock Generator


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PDF DSC571-04 DSC571-04 25MHz
1999 - Not Available

Abstract:
Text: , processors, FPGAs, other switches, or any other sRIO-based devices. The CPS-10Q supports serial RapidIO , multicast as defined in the sRIO multicast registers. b. Unicast: specified by sRIO. c. Maintenance packets: As specified by sRIO. The CPS-10Q supports a peak throughput of 100 Gbps which is the line rate for 10 ports in 4x configuration, each at 10 Gbps (3.125 Gbps minus the sRIO-defined 8b/10b , transmitted code-group as well as synchronization sequences required by sRIO. For two way traffic, packet


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PDF 80KSW0005 10-Quad CPS-10Q 80KSW0005) CPS-10Q 125Gbps, 25Gbps 676-Pin
Not Available

Abstract:
Text: sRIO SERIAL BUFFER FLOW-CONTROL DEVICE Device Overview Product Brief 80KSBR201 Provides , Rapid IO ( sRIO ) – One four-bit (x4) link, configurable to one-bit (x1) link – Port Speeds , €“ Error management supports standard and enhanced port operations – sRIO version 1.3 – Class 1+ End , connect up to two high-speed Serial RapidIO interfaces. This device is built to work with any sRIO device , flexibility make it the perfect buffering solution for sRIO systems. Features Two Independent Serial


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PDF 80KSBR201
1999 - IDT70K2000

Abstract:
Text: specified in sRIO. c. Maintenance packets: As specified in sRIO. The PPS can be programmed through a CPU , applications. Features Interfaces - sRIO 40 bidirectional serial RapidIO ( sRIO ) lanes v 1.3 Port , -bit memory address (in sRIO header) ­ Multiple packets from a group of input sample packets can be , sRIO network. If packets are addressed to a certain port or a range of addresses, the unprocessed data , switched as defined by the transport layer sRIO specification. The packet manipulation in the PPS is


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PDF 70K2000 IDT70K2000 70K2000 cpri ppsc
2007 - C6454

Abstract:
Text: equation: srio_total_power = srio_core_activity (Cvdd-1.25/1.2) + srio_io_baseline ( srio-1.25 /1.2) + srio_io_activity ( srio-1.25 /1.2) 3.2.3 Totals SoCSection of the Spreadsheet The totals section provides the , ) column sums up the rows for leakage and clocking power. The baseline portion of the srio-1.25 /1.2 , receiving data. To calculate the total SRIO power, the baseline portions of the srio-1.25 /1.2 supplies , voltage Dvdd-1.8 DVDD18 srio-1.2 /1.25 (1) DVDDR Dvdd-1.5 1.8-V I/O supply voltage (DDR2


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PDF TMS320C6455/C6454 TMS320C6455 TMS320C6454 C645x C6454 C6455 viterbi
Supplyframe Tracking Pixel