The Datasheet Archive

Top Results (5)

Part Manufacturer Description Datasheet Download Buy Part
TNETA1500APCM Texas Instruments 155.52-Mbit/S SONET/SDH Atm Receiver/Transmitter 144-QFP
SLK2501CD1VFP Texas Instruments OC-48 Muti-Rate SONET Transceiver 32-HLQFP 0 to 70
SLK2701IPZP Texas Instruments 2.7 Gbps OC-48 SONET Transceiver 100-HTQFP -40 to 85
TNETA1500APGE Texas Instruments 155.52-Mbit/S SONET/SDH Atm Receiver/Transmitter 144-LQFP
SLK2721PZP Texas Instruments IC TRANSCEIVER, PQFP100, POWER, THERMALLY ENHANCED, PLASTIC, VQFP-100, ATM/SONET/SDH IC

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1997 - fpga vhdl code for crc-32

Abstract: crc verilog code 16 bit XC2VP20 sonet testbench verilog code for 10 gb ethernet verilog code for frame synchronization vhdl code scrambler STM 64 FRAMER WITH OTN vhdl code CRC32 CRC-32
Text: ) Read Controller Framer Scrambler SONET /SDH Tx (Line) Header Inserter GCI Interface , ) De-Framer De-Scrambler Sync State Machine SONET /SDH Rx (Line) Header Processor Figure 1 , hybrid SONET /SDH-Ethernet equipment The GFP processor can be deployed in transport network elements (e.g. SONET /SDH, OTN) to encapsulate and de-capsulate data packets. Data frames from multiple , SONET /SDH or OTN backplanes. Ethernet STM-64 OC-192 Ethernet Ethernet Switch GFP Frame r


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PDF CC327 OC-192 fpga vhdl code for crc-32 crc verilog code 16 bit XC2VP20 sonet testbench verilog code for 10 gb ethernet verilog code for frame synchronization vhdl code scrambler STM 64 FRAMER WITH OTN vhdl code CRC32 CRC-32
1997 - OTU1

Abstract: XIP2174 Paxonet Communications OC48 ISE4 OTN testbench
Text: Constraints File cc381.ucf Testbench , test scripts Verification Tool Instantiation Templates VHDL , Multi frame Aligned OTU OH Processor ODU OH Processor System Interface ( SONET ) Client , System Interface ( SONET ) Client Adapter Source External Overhead Interface External OH , ITU recommendations G.709 and G.798. It supports OC48 SONET data on the client interface. The source , external overhead interface. The Client Adapter extracts the client data ( SONET ) and gives it out on a 64


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PDF STS48 CC381) cc381 OTU1 XIP2174 Paxonet Communications OC48 ISE4 OTN testbench
1997 - OTN testbench

Abstract: CC481 XIP2196 OTU2 framer verilog code for TCM decoder Generic AIS vhdl code for bram XILINX vhdl code REED SOLOMON encoder decoder STS192 OC48
Text: Constraints File cc481.ucf Testbench , test scripts Verification Tool Instantiation Templates VHDL , ( SONET ) Client Adapter OTU2 Source Line Interface Scrambler FEC Encoder OTU Framer ODU OH Processor System Interface ( SONET ) Client Adapter Source External Overhead , .798. It supports OC48 SONET data on the client interface. The source takes in client data, maps it into , external overhead interface. The Client Adapter extracts the client data ( SONET ) and gives it out on a 64


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PDF STS192 CC481) cc481 OTN testbench XIP2196 OTU2 framer verilog code for TCM decoder Generic AIS vhdl code for bram XILINX vhdl code REED SOLOMON encoder decoder OC48
1997 - GR-253

Abstract: XIP211 XIP2198 STS-192 vhdl code for frame synchronization Paxonet Communications
Text: File Formats .ucf Constraints File Verification Tool Script-based Behavioral VHDL Testbench , having value 620A\h in SONET mode and 6A0A\h in SDH mode Optionally inserts AIS-P on microprocessor , locates the SPE in the SONET frame. It further extracts and processes the path overhead bytes. It then , /extraction for SONET /SDH framing. The drop interface takes in/gives out telecom data with C1, J1 indication , payload envelope (SPE). Pointer bytes are added to form a partial SONET frame. This is then transmitted


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PDF STS192c/STM64 CC324) GR-253, CC324 GR-253 XIP211 XIP2198 STS-192 vhdl code for frame synchronization Paxonet Communications
2009 - vhdl code for 8 bit barrel shifter

Abstract: verilog code for barrel shifter vhdl code for 16 prbs generator vhdl code for 4 bit barrel shifter vhdl code for loop filter of digital PLL ML523 8 bit barrel shifter vhdl code vhdl code for phase frequency detector verilog code of parallel prbs pattern generator prbs pattern generator using vhdl
Text: specifically designed for 8-bit protocols, such as SONET /SDH. Other barrel shifters can be designed by the , . Simulating the DRU, page 8 describes the testbench developed to simulate the DRU, while Testing the DRU on the ML523 Characterization Platform, page 9 describes the testbench that shows the DRU at work on the , TB_SIM_DRU_JITTER testbench is to simulate the ability of the NI-DRU to operate at many different data rates (shown in Table 4) with synchronous and plesiochronous inputs. This testbench works with a single reference


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PDF XAPP875 vhdl code for 8 bit barrel shifter verilog code for barrel shifter vhdl code for 16 prbs generator vhdl code for 4 bit barrel shifter vhdl code for loop filter of digital PLL ML523 8 bit barrel shifter vhdl code vhdl code for phase frequency detector verilog code of parallel prbs pattern generator prbs pattern generator using vhdl
2009 - verilog code for barrel shifter

Abstract: vhdl code for 8 bit barrel shifter vhdl code for 4 bit barrel shifter vhdl code Pseudorandom Streams Generator XAPP875 vhdl code for 16 prbs generator vhdl code for loop filter of digital PLL vhdl code for clock and data recovery prbs pattern generator using vhdl prbs generator using vhdl
Text: specifically designed for 8-bit protocols, such as SONET /SDH. Other barrel shifters can be designed by the , . "Simulating the DRU," page 8 describes the testbench developed to simulate the DRU, while "Testing the DRU on the ML523 Characterization Platform," page 9 describes the testbench that shows the DRU at work on , the DRU The purpose of the TB_SIM_DRU_JITTER testbench is to simulate the ability of the NI-DRU to , testbench works with a single reference clock frequency of 155.52 MHz. The user can also apply any ppm


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PDF XAPP875 verilog code for barrel shifter vhdl code for 8 bit barrel shifter vhdl code for 4 bit barrel shifter vhdl code Pseudorandom Streams Generator XAPP875 vhdl code for 16 prbs generator vhdl code for loop filter of digital PLL vhdl code for clock and data recovery prbs pattern generator using vhdl prbs generator using vhdl
1997 - rx data path interface in vhdl

Abstract: vhdl code for 8-bit calculator vhdl code for scrambler descrambler CRC-16 and verilog fpga vhdl code for crc-32 x431 CRC-16 CC226 STS-48 CRC-32
Text: Tx FIFO (System) Read Controller Framer SONET /SDH Tx (Line) Scrambler Header , Controller Rx FIFO (System) Sync State Machine Descrambler Deframer SONET /SDH Rx (Line , aggregation function embedded in hybrid SONET / SDH-Ethernet equipment The GFP processor can be deployed in transport network elements (e.g. SONET /SDH, OTN) to encapsulate and decapsulate data packets. Data frames , networks to SONET /SDH or OTN backplanes. Ethernet Ethernet OC-12 Ethernet Switch GFP


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PDF CC224) CC224 apCC224 rx data path interface in vhdl vhdl code for 8-bit calculator vhdl code for scrambler descrambler CRC-16 and verilog fpga vhdl code for crc-32 x431 CRC-16 CC226 STS-48 CRC-32
1998 - RFC-1619

Abstract: foundation field bus protocol PLX9080 RFC1619 counter schematic diagram vhdl code CRC 32 vhdl code for scrambler descrambler VHDL CODE FOR HDLC controller
Text: RFC1619 PPP Over SONET specification Supports programmable Address, Control and Protocol fields , (PPP Over SONET ) specification. Figure 1 shows an example application using the transmit and receive , Local Bus 32 32 PPP8 CoreCell Tx Tx FIFO Tx PP FPGA SONET TxFPGA Tx Line Drv. PPP8 CoreCell Rx Rx PP FPGA SONET RxFPGA Rx Line Drv. 32 Config EPLD Memory Interface Cntler 32 Rx FIFO 32 FPGA Config Signals X8816 Packets Over SONET Figure 1


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PDF CC318f) RFC1619 16/32-bit RFC-1619 foundation field bus protocol PLX9080 counter schematic diagram vhdl code CRC 32 vhdl code for scrambler descrambler VHDL CODE FOR HDLC controller
1997 - cc143

Abstract: simple powerful charge controller block diagram scrambler
Text: Specification Design File Formats EDIF Netlist cc200.ucf Constraints File Behavioral VHDL Testbench , stream of the Transmission Convergence sublayer of an ATM Physical Layer processor for SONET /SDH. The , Transmission Convergence sublayer of an ATM Physical Layer processor for any SONET or SDH transmission , Verification The CC200 testbench was written in VHDL with very powerful scripting capabilities and several , testbench by writing new scripts. The FPGA verification was done by back annotating the implementation and


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PDF CC200 disc2277 cc143 simple powerful charge controller block diagram scrambler
1997 - OTU2 framer

Abstract: verilog code for TCM decoder 8 BIT PROCESSOR USING VHDL
Text: Interface ( SONET ) System Interface ( SONET ) Source External Overhead Interface External OH , Transport Network (OTN) device complying to ITU recommendations G.709 and G.798. It supports OC-48 SONET , . The Client Adapter extracts the client data ( SONET ) and gives it out on a 64-bit, 167.33 MHz system interface The OTU2 Source takes in the client data ( SONET ) on a 64-bit, 167.33 MHz system interface , VHDL testbench with very powerful scripting capabilities. More than 40 scripts have been written to


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PDF CC481 cc481chp OTU2 framer verilog code for TCM decoder 8 BIT PROCESSOR USING VHDL
2001 - GR-253-CORE

Abstract: No abstract text available
Text: /asynchronous T3 signal over Synchronous Optical Network ( SONET ) Synchronous Transport Signal level 1 (STS , , Synchronous Optical Network ( SONET ) Transport Systems: Common Generic Criteria, GR-253-CORE, Issue 2 , Serializer Deserializer SONET STS-1 Framer (STS1FRM) T3 Mapper (T3MAP) T3 Framer (T3 FRM) T3 , bytes deep. Accepts data bytes from a SONET framer Performs destuffing Extracts a raw T3 bit stream , a 32-byte FIFO buffer Performs payload bit stuffing Provides payload bytes to a SONET framer


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2001 - 512Kx32x4

Abstract: vhdl GPCM TADM042G5 block diagram 8085 microprocessor based traffic control system
Text: Preliminary Data Sheet November 2001 Quad-Port Gigabit Ethernet Over SONET /SDH Smart Silicon Solution Overview The quad-port gigabit Ethernet (GbE) over SONET / SDH design is a system solution for transporting GbE frames over existing SONET /SDH rings or point-topoint connections. It is provided using a combination of SONET /SDH and GbE standard products together with FPGAs and stand-alone SDRAM devices. One of , having the reliability built into SONET /SDH systems. The solution provided by Agere Systems Inc. is an


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PDF DS02-055NCIP DS01-230NCIP) 512Kx32x4 vhdl GPCM TADM042G5 block diagram 8085 microprocessor based traffic control system
2000 - BM1S

Abstract: sonet testbench CP155
Text: SONET /SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) December 19, 2000; ver. 1.00 , simulation with user design in third-party simulators Performs Synchronous Optical Network ( SONET , with all applicable standards, including: ­ Bellcore, Synchronous Optical Network ( SONET ) Transport , Bellcore, Synchronous Optical Network ( SONET ) Transport Systems: Common Generic Criteria, Issues List , achieve ATM transport over SONET . Figure 1. Typical Application Midbus Atlantic Interface Fiber


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2001 - sonet testbench

Abstract: CP155 GR-253-CORE
Text: SONET STS-1 Framer MegaCore Function (STS1FRM) June 2001; ver. 1.01 Data Sheet I Features I I I I I I Typical Applications Performs synchronous optical network ( SONET , transport over SONET . Figure 1. Typical Application Line Interface Circuit Clock Data Recovery Serializer Deserializer SONET STS-1 Framer (STS1FRM) Atlantic ATM Cell Processor 155 Mbps , Multiplexers 1 SONET STS-1 Framer MegaCore Function (STS1FRM) Data Sheet The STS1FRM complies with


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2001 - CP155

Abstract: GR-253-CORE
Text: SONET /SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) June 2001, ver. 1.01 Data Sheet , ( SONET )/synchronous digital hierarchy (SDH) framing and transport convergence (TC) Processes transport , SONET . Figure 1. Typical Application Fiber Optic Module Clock Data Recovery Serializer Deserializer SONET /SDH STS-3c/ STM-1 Framer (STS3CFRM) Atlantic ATM Cell Processor 155 Mbps , -1.01 ATM switches Digital cross-connection (DCC) systems Routers Multiplexers 1 SONET /SDH STS


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2001 - CP622

Abstract: GR-253-CORE STS12CFRM
Text: SONET /SDH STS-12c/STM-4 Framer MegaCore Function (STS12CFRM) July 2001; ver. 1.01 Data Sheet , ( SONET )/synchronous digital hierarchy (SDH) framing and transport convergence (TC) Processes transport , interfacing with two other Altera MegaCore variants to achieve ATM transport over SONET . Figure 1. Typical Application Fiber Optic Module Clock Data Recovery Serializer Deserializer SONET /SDH STS , Multiplexers 1 SONET /SDH STS-12c/STM-4 Framer MegaCore Function (STS12CFRM) Data Sheet The STS12CFRM


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PDF STS-12c/STM-4 STS12CFRM) CP622 GR-253-CORE STS12CFRM
2000 - CP155

Abstract: No abstract text available
Text: SONET STS-1 Framer MegaCore Function (STS1FRM) December 19, 2000; ver. 1.00 Features s s , user design in third-party simulators Performs Synchronous Optical Network ( SONET ) framing and , Bellcore, Synchronous Optical Network ( SONET ) Transport Systems: Common Generic Criteria, Generic Requirements GR-253CORE, Issue 2, Revision 2, January 1999 ­ Bellcore, Synchronous Optical Network ( SONET , SONET . Figure 1. Typical Application Midbus Atlantic Line Interface Circuit Clock Data


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2001 - vhdl code for stm-1 sequence

Abstract: vhdl code for BIP-8 generator STM-1 verilog code BIP-8 rw0s ATM machine working circuit diagram using sonet vhdl alarm clock design of digital VHDL vhdl code for 9 bit parity generator GR-253 vhdl code stm-64 verilog implementation of sts1 pointer processing
Text: SONET /SDH STS-3c/STM-1 Framer MegaCore Function STS3CFRM June 2001 User Guide Version 1.01 , -1.01 SONET /SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide Altera, APEX, APEX 20K , user guide provides comprehensive information about the Altera® SONET /SDH STS-3c/STM-1 Framer MegaCore , you to jump to related information. iii About this User Guide SONET /SDH STS-3c/STM-1 Framer , SONET /SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide About this User Guide


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2001 - verilog code BIP-8

Abstract: alarm clock verilog code rw0s digital alarm clock vhdl code in modelsim ATM machine working circuit diagram using sonet vhdl GR-253 GR-253-CORE vhdl code for 9 bit parity generator vhdl code for 1 bit error generator verilog implementation of sts1 pointer processing
Text: SONET STS-3 Framer MegaCore Function STS1X3FRM June 2001 User Guide Version 1.01 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com A-UG-IPSTS1X3FRM-1.01 SONET , Guide User Guide This user guide provides comprehensive information about the Altera® SONET STS , SONET STS-3 Framer MegaCore Function (STS1X3FRM) User Guide How to Contact Altera For the most , . Altera Corporation SONET STS-3 Framer MegaCore Function (STS1X3FRM) User Guide Typographic


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2001 - 16 byte register VERILOG

Abstract: verilog code BIP-8 GR-253 GR-253-CORE STS12CFRM digital alarm clock vhdl code in modelsim alarm clock design of digital VHDL
Text: SONET /SDH STS-12c/STM-4 Framer MegaCore Function STS12CFRM July 2001 User Guide Version 1.01 , -1.01 SONET /SDH STS-12c/STM-4 Framer MegaCore Function (STS12CFRM) User Guide Altera, APEX, APEX 20K , about the Altera® SONET /SDH STS-12c/STM-4 Framer MegaCore® Function (STS12CFRM). Table 1 shows the , SONET /SDH STS-12c/STM-4 Framer MegaCore Function (STS12CFRM) User Guide Typographic Conventions About this User The SONET /SDH STS-12c/STM-4 Framer MegaCore Function (STS12CFRM) User Guide uses the


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PDF STS-12c/STM-4 STS12CFRM -UG-IPSTS12CFRM-1 STS-12c/STM-4 STS12CFRM) STS12c/STM-1 16 byte register VERILOG verilog code BIP-8 GR-253 GR-253-CORE STS12CFRM digital alarm clock vhdl code in modelsim alarm clock design of digital VHDL
2001 - verilog implementation of sts1 pointer processing

Abstract: verilog code BIP-8 GR-253 J0 byte length 14 GR-253 GR-253-CORE
Text: SONET STS-1 Framer MegaCore Function STS1FRM June 2001 User Guide Version 1.01 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com A-UG-IPSTS1FRM-1.01 SONET , Guide User Guide This user guide provides comprehensive information about the Altera® SONET STS , green text, allow you to jump to related information. iii About this User Guide SONET STS , . Altera Corporation SONET STS-1 Framer MegaCore Function (STS1FRM) User Guide Typographic


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vhdl code for 1 bit error generator

Abstract: PQ2084 CRC10 vhdl code CRC 32 I363 XC4000XL XC4013XL CRC-32 crc 10 in atm fpga vhdl code for crc-32
Text: telecommunications and networking equipment including ATM, SONET and Ethernet systems. General Description The , implementation. Additional tests can be added to the testbench by writing new scripts. Recommended Design , design methodology including FPGA targeting. Using the testbench requires familiarity with V-System of


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PDF CRC10 CC-130) CRC10 telecommunication0-1313 vhdl code for 1 bit error generator PQ2084 vhdl code CRC 32 I363 XC4000XL XC4013XL CRC-32 crc 10 in atm fpga vhdl code for crc-32
1998 - vhdl code for 1 bit error generator

Abstract: CRC10 crc 10 in atm vhdl code CRC 32 I363 CRC-32 PQ2084 XC4013XL XCS30 xcs30-pq208
Text: Verifier cores can be used in telecommunications and networking equipment including ATM, SONET and , verifying the implementation. Additional tests can be added to the testbench by writing new scripts , familiar with HDL design methodology including FPGA targeting. Using the testbench requires familiarity


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PDF CRC10 CC-130) CRC10 vhdl code for 1 bit error generator crc 10 in atm vhdl code CRC 32 I363 CRC-32 PQ2084 XC4013XL XCS30 xcs30-pq208
2001 - GR-253-CORE

Abstract: No abstract text available
Text: SONET STS-3 Framer MegaCore Function (STS1X3FRM) June 2001; ver. 1.01 Features Data Sheet , user design in third-party simulators Performs synchronous optical network ( SONET )/synchronous , SONET STS-3 Framer MegaCore Function (STS1X3FRM) Data Sheet Figure 1. Typical Applications STS1X3FRM , Serializer Deserializer SONET STS-3 Framer (STS1X3FRM) txclk External CPU CPU Bus Processor , Data Recovery Serializer Deserializer SONET STS-3 Framer (STS1X3FRM) txclk External CPU


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2001 - cyclic redundancy check verilog source

Abstract: CRC-16 CRC-32 PP155 PP622 RFC1662 CRC-CCITT 0xFFFF
Text: HDLC I/O IP LE LSB LSByte Mbps MSB MSByte PC POS-PHY PPP RX RXHLDC SDH SONET SPE STS , Most Significant Byte Personal computer Packet Over SONET Physical layer Point-to-Point Protocol , .30 Using the Verilog Demo Testbench , preserved (as in SONET ), this function should be disabled. Assume the following packet: Clock Cycle , external bit-serial mediums such as SONET and SDH (optical fibre), in keeping with telephony convention


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PDF PP622 -UG-IPPP622-1 PP622) cyclic redundancy check verilog source CRC-16 CRC-32 PP155 PP622 RFC1662 CRC-CCITT 0xFFFF
Supplyframe Tracking Pixel