SFE-6.0 MB
Abstract: sfe 5,5 mb tda8190 SFE 5.5 Mb sfe 55 mb dc volume tone control circuit murata tv flyback
Text: MHz 10 O o II 120 9 68 Murata SFÉ 4.5 MA 22 1000 1000 68 8.2 47 Murata SFE 5.5 MB 18 560 560 68 6.8 47 Murata SFE 6.0 MB 18 470 470 Figure 16 : Application Circuit R1 o ¿ = 7
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TDA8190
TDA8190
SFE-6.0 MB
sfe 5,5 mb
SFE 5.5 Mb
sfe 55 mb
dc volume tone control circuit
murata tv flyback
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Not Available
Abstract: No abstract text available
Text: II o a rh o L1 Murata SFE 5.5 MB Murata SFE 6.0 MB PF f i f i 22 18
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TDA8190
TDA8190
18ki2
7T2T237
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1994 - TDA8190
Abstract: sfe 5,5mb murata tda 5W amplifier tone volume control tda AMP 12V MV2201 sfe 5.5 murata SFE-5.5 DIP20 POWER AMPLI 400HZ sfe 4.5
Text: . TDA8190 C5 C4 C8 C. F C1 R2 R3 Units µH Appl. 4.5 MHz 10 Qo = 60 120 9 68 Murata SFE 4.5 MA 22 1000 1000 pF pF nF pF Appl. 5.5 MHz 12 Qo = 80 68 8.2 47 Murata SFE 5.5 MB 18 560 560 Appl. 6 MHz 10 Qo = 70 68 6.8 47 Murata SFE 6.0 MB 18 470 470
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TDA8190
TDA8190
sfe 5,5mb murata
tda 5W amplifier tone volume control
tda AMP 12V
MV2201
sfe 5.5 murata
SFE-5.5
DIP20
POWER AMPLI 400HZ
sfe 4.5
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TDA4190
Abstract: SFE-5.5 12KW DIP-20 TDA4190A sfe 5,5 mb s069
Text: HH Qo =60 Qo =80 Qo =70 C5 pF 120 68 68 C4 PF 9 8.2 6.8 C8 nF 68 47 47 C.F. - Murata SFE 4.5 MA Murata SFE 5.5 MB Murata SFE 6.0 MB C1 pF 22 18 18 R2 n 1000 560 470 R3 « 1000 560 470 Figure 17
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TDA4190
TDA4190
SFE-5.5
12KW
DIP-20
TDA4190A
sfe 5,5 mb
s069
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Not Available
Abstract: No abstract text available
Text: nF Qo - 10 = 70 68 6.8 68 47 47 Murata SFE 4.5 MA C F Murata SFE 5.5 MB Murata SFE 6.0 MB C1 pF 22 18 18 R2 n 1000 560 470 R3 n
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TDA8190
TDA8190
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sfe 5,5 mb
Abstract: TDA8190 SFE-6.0 MB MV2201 sfe 5,5mb murata SFE-5.5 DIP20 tda819 murata filter SFE 6 TDA i2c tone volume dip
Text: . TDA8190 C5 C4 C8 C. F C1 R2 R3 Units µH Appl. 4.5 MHz 10 Qo = 60 120 9 68 Murata SFE 4.5 MA 22 1000 1000 pF pF nF pF Appl. 5.5 MHz 12 Qo = 80 68 8.2 47 Murata SFE 5.5 MB 18 560 560 Appl. 6 MHz 10 Qo = 70 68 6.8 47 Murata SFE 6.0 MB 18 470 470
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TDA8190
TDA8190
sfe 5,5 mb
SFE-6.0 MB
MV2201
sfe 5,5mb murata
SFE-5.5
DIP20
tda819
murata filter SFE 6
TDA i2c tone volume dip
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sfe 5,5 mb
Abstract: G5063 SFE-6.0 MB A819
Text: produced by the dissipate power. Appl. 5.5 MHz 12 D 68 8.2 47 Murata SFE 5.5 MB 18 560 560 O Appl. 6 MHz O pF PF nF 68 6.8 47 Murata SFE 6.0 MB 18 470 470 10/11 1056 SGS-THOMSON -si , output Components L1 C5 C4 C8 C. F C1 R2 R3 PF Q Q Units UH Appi. 4.5 MHz 10 Qo = 60 120 9 68 Murata SFE
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A8190
TDA8190
TDA8190
sfe 5,5 mb
G5063
SFE-6.0 MB
A819
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506j
Abstract: tda4190
Text: SFE 4.5 MA 22 1000 1000 12 Qo =80 68 8.2 47 Murata SFE 5.5 MB 18 560 560 10 Qo =70 68 6.8 47 Murata SFE 6.0 MB 18 470 470 pF PF nF PF Q n Figure 17 : PC Board and Com ponents Layout of
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TDA4190
A4190
506j
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TDA8305
Abstract: TDA8305A TDA4505 TBA120 colour tv power supply circuit diagram sfe 5,5 mb SAW-Filter colour tv vertical ic circuit diagram colour tv sound section ic SFE 5.5 Mb
Text: SFE 5.5 MB Fig.11 Application diagram. June 1990 2699
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TDA8305A
TheTDA8305A
100nF
/f10kÂ
TDA8305
TDA8305A
TDA4505
TBA120
colour tv power supply circuit diagram
sfe 5,5 mb
SAW-Filter
colour tv vertical ic circuit diagram
colour tv sound section ic
SFE 5.5 Mb
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TDA6303
Abstract: tda830 1074a TDA8303A 7 segment display 5612 Block diagram on monochrome tv receiver circuit sfe 5,5 mb TDA8303 horizontal deflction output 86-60-3
Text: pF 22 nF HI-K AFC 6.8 |JH 2.2 kn 120 pF T 22 nF Hl- Ls-^ SFE 5.5 MB video out Fig. 12
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TDA8303/A
TDA6303
tda830
1074a
TDA8303A
7 segment display 5612
Block diagram on monochrome tv receiver circuit
sfe 5,5 mb
TDA8303
horizontal deflction output
86-60-3
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2004 - AN-263
Abstract: sfe 4.5 MB
Text: Frame Evaluation ( SFE ) bit low for at least one frame starts a measurement cycle. When the SFE bit in , signal that a valid offset measurement is ready to be read from bits 0 to 11 of the FAR. The SFE bit , of measuring an offset up to 2047.5 clock cycles (1 frame at 8 Mb /s = 128 channels * 8 bits/channel , alignment offset. This bit is reset to zero, when SFE bit in the CR register is changed from 1 to 0. 11 , refers to the measured input offset value. These bits are rest to zero when the SFE bit of the CR
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AN-263
drw05
AN-263
sfe 4.5 MB
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2001 - sfe 6,5 mb
Abstract: OF81 1A1-1A10 TX11-RX11 sfe 55 mb
Text: capacity of 1,024 x 1,024 channels at 2.048 Mb /s, 2,048 x 2,048 channels at 4.096 Mb /s, and 4,096 x 4,096 channels at 8.192 Mb /s and 8,192 x8,192 channels at 16.384 Mb /s. With 32 inputs and 32 outputs , Mb /s 32 serial input and output streams Accepts data streams at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s Per-channel Variable Delay Mode for low-latency applications Per-channel Constant Delay Mode , stream. These streams have selectable data rates of 2.048, 4.096, 8.192 or 16.384 Mb /s. Provides the
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IDT72V71650
IDT72V71650
DA144-1)
BB144-1)
72V71650
drw17
sfe 6,5 mb
OF81
1A1-1A10
TX11-RX11
sfe 55 mb
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2000 - AN-263
Abstract: fd100
Text: Frame Evaluation ( SFE ) bit low for at least one frame starts a measurement cycle. When the SFE bit in , signal that a valid offset measurement is ready to be read from bits 0 to 11 of the FAR. The SFE bit , of measuring an offset up to 2047.5 clock cycles (1 frame at 8 Mb /s = 128 channels * 8 bits/channel , alignment offset. This bit is reset to zero, when SFE bit in the CR register is changed from 1 to 0. 11 , refers to the measured input offset value. These bits are rest to zero when the SFE bit of the CR
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AN-263
drw05
AN-263
fd100
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2001 - sfe 6,5 mb
Abstract: No abstract text available
Text: switch capacity of 1,024 x 1,024 channels at 2.048 Mb /s, 2,048 x 2,048 channels at 4.096 Mb /s, and 4,096 x 4,096 channels at 8.192 Mb /s and 8,192 x8,192 channels at 16.384 Mb /s. With 32 inputs and 32 , 8K non-blocking switching at 16.384 Mb /s 32 serial input and output streams Accepts data streams at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s Per-channel Variable Delay Mode for low-latency , have selectable data rates of 2.048, 4.096, 8.192 or 16.384 Mb /s. Provides the clock to the JTAG test
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IDT72V71650
DA144-1)
BB144-1)
72V71650
drw17
com/docs/PSC4062
com/docs/PSC4094
sfe 6,5 mb
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2001 - Not Available
Abstract: No abstract text available
Text: 1,024 x 1,024 channels at 2.048 Mb /s, 2,048 x 2,048 channels at 4.096 Mb /s, and 4,096 x 4,096 channels at 8.192 Mb /s and 8,192 x8,192 channels at 16.384 Mb /s. With 32 inputs and 32 outputs , 16.384 Mb /s 32 serial input and output streams Accepts data streams at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s Per-channel Variable Delay Mode for low-latency applications Per-channel , . Serial data input stream. These streams have selectable data rates of 2.048, 4.096, 8.192 or 16.384 Mb /s
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IDT72V71650
IDT72V71650
DA144-1)
BB144-1)
72V71650
drw17
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2001 - Not Available
Abstract: No abstract text available
Text: x 2,048 channel non-blocking switching Accepts data streams at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s Rate matching capability: Mux/Demux mode Output Enable Indication pins provided by dedicated , maximum non-blocking switch capacity of 2,048 x 2,048 channels with data rates at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s. With 16 inputs and 16 outputs, a variety of rate combinations is supported , stream. These streams may have a data rate of 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s, or 16.384 Mb /s. These
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IDT72V71623
drw19
com/docs/PSC4085
com/docs/PSC4062
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2000 - MT90820AL
Abstract: MT90820AP1 OF100 MT90820 MT90820AL1 MT90820AP MT90820APR MT90820APR1 STO10
Text: ,048 × 2,048 channel non-blocking switching at 8.192 Mb /s · Per-channel variable or constant , 2.048 Mb /s, 4.096 Mb /s or 8.192 Mb /s · Automatic frame offset delay measurement · , rate of 8.192 Mb /s, 1,024 x 1,024 channels at 4.096 Mb /s and 512 x 512 channels at 2.048 Mb /s. The , 2.048, 4.096 or 8.192 Mb /s, depending upon the value programmed at bits DR0 - 1 in the IMS register , streams may have data rates of 2.048, 4.096 or 8.192 Mb /s, depending upon the value programmed at bits
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MT90820
MT90820AL
MT90820AP1
OF100
MT90820
MT90820AL1
MT90820AP
MT90820APR
MT90820APR1
STO10
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2000 - Not Available
Abstract: No abstract text available
Text: x 2,048 channel non-blocking switching Accepts data streams at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s Rate matching capability: Mux/Demux mode Output Enable Indication pins provided by dedicated , maximum non-blocking switch capacity of 2,048 x 2,048 channels with data rates at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s. With 16 inputs and 16 outputs, a variety of rate combinations is supported , stream. These streams may have a data rate of 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s, or 16.384 Mb /s. These
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IDT72V71623
DA144-1)
72V71623
drw19
com/docs/PSC4085
com/docs/PSC4062
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2002 - IDT72V71623
Abstract: RX15
Text: ,048 channel non-blocking switching Accepts data streams at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s Rate matching capability: Mux/Demux mode Output Enable Indication pins provided by , IDT72V71623 has a maximum non-blocking switch capacity of 2,048 x 2,048 channels with data rates at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s. With 16 inputs and 16 outputs, a variety of rate , streams may have a data rate of 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s, or 16.384 Mb /s. These pins reflect
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BC144-1)
DA144-1)
72V71623
drw19
IDT72V71623
RX15
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2001 - IDT72V71623
Abstract: RX15
Text: ,048 channel non-blocking switching Accepts data streams at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s Rate matching capability: Mux/Demux mode Output Enable Indication pins provided by , IDT72V71623 has a maximum non-blocking switch capacity of 2,048 x 2,048 channels with data rates at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s. With 16 inputs and 16 outputs, a variety of rate , streams may have a data rate of 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s, or 16.384 Mb /s. These pins reflect
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BC144-1)
DA144-1)
72V71623
drw19
IDT72V71623
RX15
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Not Available
Abstract: No abstract text available
Text: b u s control signals. The M B92411 s u p p o rts 8-, 16-, a n d 3 2 -b it tra n sfe rs a n d is d , speed ratin g s: 20 MHz, 25 MHz, an d 33 MHz w ith block tra n sfe r ra te s of 4 0 M B /s, 50 M B /s, a n d 66 M B /s, respectively. T his ran g e of tra n sfe r ra te s allow s y ou to choose th e , DMA o p eratio n s su c h a s cycle stea l a n d b u r s t transfer. T ra n sfe r can be in itiated , w ith dual bus control signals Transfer Speeds ( MB /s) 20 MHz: M B92411-20C R 25 MHz: M B
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MB92411,
32-bit
B92411
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2000 - 16 input 16 output
Abstract: FD11
Text: × 2,048 channel non-blocking switching at 8.192 Mb /s Per-channel variable or constant throughput delay Automatic identification of ST-BUS/GCI interfaces Accept ST-BUS streams of 2.048 Mb /s, 4.096 Mb /s or 8.192 Mb /s Automatic frame offset delay measurement Per-stream frame delay offset programming , Switch has a non-blocking switch capacity of 2,048 x 2,048 channels at a serial bit rate of 8.192 Mb /s, 1,024 x 1,024 channels at 4.096 Mb /s and 512 x 512 channels at 2.048 Mb /s. The device has many features
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MT90820
IEEE-1149
MT90820AP
MT90820AL
MT90820APR
MT90820AL1
MT90820AP1
16 input 16 output
FD11
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2005 - Not Available
Abstract: No abstract text available
Text: non-blocking switching ⢠Internal Loopback for testing ⢠Accepts data streams at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or ⢠Available in 144-pin Thin Quad Flatpack (TQFP) 16.384 Mb /s 1 ⢠Rate matching , channels with data rates at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s. With 16 inputs and 16 , output stream. These streams may have a data rate of 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s, or 16.384 Mb /s , streams may have a data rate of 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s, or 16.384 Mb /s. This input accepts
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IDT72V71623
IEEE-1149
144-pin
dedica000
CQ-13-01
CQ-14-06
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2000 - IC TX-2
Abstract: IDT72V71623 RX15 OF81
Text: streams Maximum 2,048 x 2,048 channel non-blocking switching Accepts data streams at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s Rate matching capability: Mux/Demux mode Output Enable Indication , ,048 channels with data rates at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s. With 16 inputs and , Mb /s, 4.096 Mb /s, 8.192 Mb /s, or 16.384 Mb /s. These pins reflect the active or three-state status , Drive Enable I I I Serial data input stream. These streams may have a data rate of 2.048 Mb /s
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IDT72V71623
drw19
com/docs/PSC4085
com/docs/PSC4062
IC TX-2
IDT72V71623
RX15
OF81
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2005 - Not Available
Abstract: No abstract text available
Text: data streams at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s Rate matching capability: Mux/Demux , channels with data rates at 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s or 16.384 Mb /s. With 16 inputs and 16 , output stream. These streams may have a data rate of 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s, or 16.384 Mb /s , streams may have a data rate of 2.048 Mb /s, 4.096 Mb /s, 8.192 Mb /s, or 16.384 Mb /s. This input accepts , serial input streams (RX) and serial output streams (TX) of the IDT72V71623 can be run up to 16.384 Mb /s
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IEEE-1149
144-pin
drw19
CQ-13-01
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