The Datasheet Archive

Top Results (5)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
444-5025-064 444-5025-064 ECAD Model Amphenol Communications Solutions VHDM-HSD™, Backplane connectors, Vertical Orientation, Press Fit Termination, 5 Row eHSD+, 25 positions, open, 5.15mm (0.202in), Header.
444-5010-064 444-5010-064 ECAD Model Amphenol Communications Solutions VHDM-HSD™, Backplane connectors, Vertical Orientation, Press Fit Termination, 5 Row eHSD+, 10 positions, open, 5.15mm (0.202in), Header.
444-5010-062 444-5010-062 ECAD Model Amphenol Communications Solutions VHDM-HSD™, Backplane connectors, Vertical Orientation, Press Fit Termination, 5 Row eHSD+, 10 positions, open, 6.25mm (0.246in), Header.
444-5025-062 444-5025-062 ECAD Model Amphenol Communications Solutions VHDM-HSD™, Backplane connectors, Vertical Orientation, Press Fit Termination, 5 Row eHSD+, 25 positions, open, 6.25mm (0.246in), Header.
0934445233 0934445233 ECAD Model Molex Combination Line Connector

scl 4445 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2012 - Not Available

Abstract: No abstract text available
Text: -436.691 77 SEG19 833.15 17 SCL -1294.81 -436.691 78 SEG20 773.15 444.5 , Diagram Power_on reset VSS COM0 SDA SCL Internal RC Oscillator Timing generator I2C , SCL VSS COM0 COM1 COM2 COM3 COM4/SEG0 COM5/SEG1 COM6/SEG2 COM7/SEG3 COM8/SEG4 COM9/SEG5 , SEG29 SEG30 SEG31 VDD SDA SCL VSS COM0 COM1 COM2 COM3 COM4/SEG0 COM5/SEG1 COM6/SEG2 COM7 , SDA 3 64 SEG53 SCL 4 63 SEG52 VSS 5 62 SEG51 COM0 6 61


Original
PDF HT16C24/HT16C24G 32kHz 160Hz
2011 - Not Available

Abstract: No abstract text available
Text: -436.691 77 SEG19 833.15 444.5 17 SCL -1294.81 -436.691 78 SEG20 773.15 , September 23, 2011 HT16C24/HT16C24G Block Diagram Power_on reset VSS COM0 SDA SCL Internal , SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 VDD SDA SCL VSS COM0 COM1 COM2 COM3 , SCL VSS COM0 COM1 COM2 COM3 COM4/SEG0 COM5/SEG1 COM6/SEG2 COM7/SEG3 COM8/SEG4 COM9/SEG5 , SCL 4 63 SEG52 VSS 5 62 SEG51 COM0 6 61 SEG50 COM1 7 60


Original
PDF HT16C24/HT16C24G 32kHz 160Hz
2012 - Not Available

Abstract: No abstract text available
Text: 444.5 444.5 16 SDA -1381.81 -436.691 77 SEG19 833.15 17 SCL -1294.81 , Power_on reset COM0 SDA Internal RC Oscillator SCL Timing generator I2C Controller 8 , SEG27 VDD SDA SCL VSS COM0 COM1 COM2 COM3 COM4/SEG0 COM5/SEG1 COM6/SEG2 COM7/SEG3 COM8 , SEG27 SEG28 SEG29 SEG30 SEG31 VDD SDA SCL VSS COM0 COM1 COM2 COM3 COM4/SEG0 COM5/SEG1 , 2 SDA 3 64 SEG53 SCL 4 63 SEG52 VSS 5 62 SEG51 COM0 6


Original
PDF HT16C24/HT16C24G 32kHz 160Hz
2011 - Not Available

Abstract: No abstract text available
Text: -920.85 -436.872 66 SEG18 450 444.5 20 SCL -833.85 -436.872 67 SEG19 , Diagram Power_on reset VSS COM0 SDA SCL Internal RC Oscillator Timing generator I2C , SEG9 SEG9 SEG8 SEG8 SEG7 SEG7 SEG6 SEG6 SEG5 SEG5 SEG4 SEG4 VDD SDA VDD SCL SDA VSS SCL COM0 VSS COM1 COM0 COM2 COM1 COM3 COM2 COM4 COM3 COM5 COM4 COM6 COM5 COM7 COM6 , SCL SDA VSS SCL COM0 VSS COM1 COM0 COM2 COM1 COM3 COM2 COM4/SEG0 COM3 COM5/SEG1 COM4


Original
PDF HT16C23/HT16C23G
2011 - Not Available

Abstract: No abstract text available
Text: SEG15 630 444.5 17 SDA -920.85 -436.872 64 SEG16 570 444.5 18 SCL , SCL Timing generator I2C Controller Column /Segment driver output Display RAM 52 , SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 VLCD VDD SDA SCL VSS , VLCD SEG54 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDD SDA SCL VSS COM0 COM1 COM2 , SEG54 SEG55 VLCD VCCA2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD SDA SCL


Original
PDF HT16C23/HT16C23G 32kHz 160Hz HT16C23/HT16C23G
2011 - panel 8179

Abstract: VOH27
Text: SEG15 630 444.5 17 SDA -920.85 -436.872 64 SEG16 570 444.5 18 SCL , reset VSS COM0 SDA SCL Internal RC Oscillator Timing generator I2C Controller , SEG33 SEG48 VSS SEG49 SCL SEG34 SEG50 SDA SEG35 SEG51 SEG36 1 2 3 4 , SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG52 SCL SEG53 , 42 41 40 39 38 37 SEG27 1 36 42 7 VDD 35 SEG26 2 41 HT16C23 8 SDA SEG25 3 34 SCL 64


Original
PDF HT16C23/HT16C23G 32kHz 160Hz panel 8179 VOH27
2004 - A76 MARKING CODE

Abstract: a77 package marking a80 marking code marking A32 marking A45 marking code B38 MR18R162WEG0-CM8 MARKING B17 MARKING CODE B82 marking a86
Text: A90 A91 A92 Page 2 Pin Name NC NC NC Vdd Vref Gnd SCL Vdd SDA SVdd SWP Vdd RSCK , Serial Presence Detect Address 2. SCL A53 I SVDD Serial Presence Detect Clock. SDA , signals. SPD Voltage. Used for signals SCL , SDA, SWE, SA0, SA1 and SA2. I SVDD Page 4 Serial , . 2004 Page 5 0.1 µF U0 Gnd SA0 SA1 SA2 SDA SVDD Vcc SCL SDA WP A0 A1 A2 SCL SWP 47K Serial Presence Detect SVDD Note 1. Rambus Channel signals form a loop through


Original
PDF MR18R162WEG0 288Mbit 16Mx18) 32pcs 288Mb 16K/32ms A76 MARKING CODE a77 package marking a80 marking code marking A32 marking A45 marking code B38 MR18R162WEG0-CM8 MARKING B17 MARKING CODE B82 marking a86
2002 - transistor marking A21

Abstract: a74 marking code b82 400 B83 004 marking B44 MARKING CODE b48
Text: A52 Gnd B52 Gnd A7 A8 Gnd LDQA2 B7 B8 Gnd LDQA1 A53 A54 SCL Vdd , Serial Presence Detect Address 2. SCL A53 I SV DD Serial Presence Detect Clock. SDA , signals. SPD Voltage. Used for signals SCL , SDA, SWE, SA0, SA1 and SA2. I SV DD Page 4 , Version 1.1 July. 2002 Page 5 0.1 µF U0 Gnd SA0 SA1 SA2 SDA SCL SDA WP A0 A1 A2 SCL SWP 47K Serial Presence Detect SV D D Note 1. Rambus Channel signals form a loop


Original
PDF MR18R162WAG0 288Mbit 16Mx18) 32pcs 288Mb 16K/32ms transistor marking A21 a74 marking code b82 400 B83 004 marking B44 MARKING CODE b48
2002 - a80 marking code

Abstract: MR18R162WDG0-CM8 B83 004 marking code B38 MR18R162WDG0 MR18R162WDG0-CK8 marking A70 marking code b84
Text: Name NC NC NC Vdd Vref Gnd SCL Vdd SDA SVdd SWP Vdd RSCK Gnd RDQB7 Gnd RDQB5 Gnd , I SVDD Serial Presence Detect Address 2. SCL A53 I SVDD Serial Presence Detect , reference voltage for RSL signals. SPD Voltage. Used for signals SCL , SDA, SWE, SA0, SA1 and SA2. I , Version 1.0 July. 2002 Page 5 0.1 µF U0 Gnd SA0 SA1 SA2 SDA SVDD Vcc SCL SDA WP A0 A1 A2 SCL SWP 47K Serial Presence Detect SVDD Note 1. Rambus Channel signals


Original
PDF MR18R162WDG0 288Mbit 16Mx18) 32pcs 288Mb 16K/32ms a80 marking code MR18R162WDG0-CM8 B83 004 marking code B38 MR18R162WDG0 MR18R162WDG0-CK8 marking A70 marking code b84
2004 - b41 Marking

Abstract: No abstract text available
Text: A87 A88 A89 A90 A91 A92 Pin Name NC NC NC Vdd Vref Gnd SCL Vdd SDA SVdd SWP Vdd RSCK Gnd RDQB7 Gnd , . RROW0 RSCK SA0 SA1 SA2 SCL SDA SIN SOUT SVDD SWP VCMOS Vdd A79 A81 A91, B91, A89, B89, A87, B87, A85 , RDRAM device on the module. SPD Voltage. Used for signals SCL , SDA, SWE, SA0, SA1 and SA2. I SVDD Serial , Device (288Mb) RDRAM Device (288Mb) RDRAM Device (288Mb) RDRAM Device (288Mb) Vcc SCL SDA WP A0 A1 A2 U0 SCL SWP 47K SVDD SIO0 SIO1 SCK CMD Vref SIO0 SIO1 SCK CMD Vref SIO0


Original
PDF MR18R162WEG0 288Mbit 16Mx18) 32pcs 288Mb 16K/32ms b41 Marking
2002 - a74 marking code

Abstract: MARKING B82 MARKING B83 a80 marking code B11 marking code Device marking code B12 B13 B14 B15 B16 marking A45 a64 marking code A79 marking code a86 diode
Text: B7 LDQA3 Gnd A52 A53 Gnd SCL B52 B53 Gnd SA0 A8 LDQA2 B8 LDQA1 A54 , Serial Presence Detect Address 2. SCL A53 I SV DD Serial Presence Detect Clock. SDA , signals. SPD Voltage. Used for signals SCL , SDA, SWE, SA0, SA1 and SA2. I SV DD Page 4 , Version 1.0 July. 2002 Page 5 0.1 µF U0 Gnd SA0 SA1 SA2 SDA SCL SDA WP A0 A1 A2 SCL SWP 47K Serial Presence Detect SV D D Note 1. Rambus Channel signals form a loop


Original
PDF MR18R162WDG0 288Mbit 16Mx18) 32pcs 288Mb 16K/32ms a74 marking code MARKING B82 MARKING B83 a80 marking code B11 marking code Device marking code B12 B13 B14 B15 B16 marking A45 a64 marking code A79 marking code a86 diode
2002 - MARKING CODE B82

Abstract: a87 marking Marking b66 marking a86 MARKING B83 marking a75
Text: NC Vdd Vref Gnd SCL Vdd SDA SVdd SWP Vdd RSCK Gnd RDQB7 Gnd RDQB5 Gnd RDQB3 Gnd RDQB1 Gnd RCOL0 Gnd , MR18R162WAG0 Signal RCTM RCTMN RDQA8. RDQA0 RDQB8. RDQB0 RROW2. RROW0 RSCK SA0 SA1 SA2 SCL SDA SIN SOUT , for signals SCL , SDA, SWE, SA0, SA1 and SA2. I SVDD Serial Presence Detect Write Protect (active high , (288Mb) RDRAM Device (288Mb) RDRAM Device (288Mb) Vcc SCL SDA WP A0 A1 A2 U0 SCL SWP 47K , [5.250±0.005] 6.35[0.25] 3.00[0.118] 126.35[4.97] DIA 2.44 44.45 [1.75] 69.85[2.75] 66.35[2.61] 5.68


Original
PDF MR18R162WAG0 288Mbit 16Mx18) 32pcs 288Mb 16K/32ms MARKING CODE B82 a87 marking Marking b66 marking a86 MARKING B83 marking a75
2003 - TDA7467D

Abstract: DIP28 TDA7467 D99AU1031 scl 4445
Text: DIG_GND 4 25 LP1 SCL 5 24 HP6 ADDR 6 23 HP5 SDA 7 22 HP4 , DECODER + LATCHES + LP2 0.1µF R-OUT DIG_GND ADDR SDA SCL L-OUT TDA7467 , interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be , the SCL line is LOW. Start and Stop Conditions As shown in fig.2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line


Original
PDF TDA7467 DIP28 TDA7467D TDA7467 TDA7467D DIP28 D99AU1031 scl 4445
2003 - DU128

Abstract: DIP28 TDA7467 TDA7467D D96A scl 4445
Text: 26 LP2 DIG_GND 4 25 LP1 SCL 5 24 HP6 ADDR 6 23 HP5 SDA 7 , R-OUT DIG_GND ADDR SDA SCL L-OUT TDA7467 BLOCK DIAGRAM s) t( ro P , place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors , can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop


Original
PDF TDA7467 DIP28 TDA7467D TDA7467 DU128 DIP28 TDA7467D D96A scl 4445
2003 - Not Available

Abstract: No abstract text available
Text: . The SRS sound is guaranteed by external compoPIN CONNECTION (Top view) LOUT RIN LIN DIG_GND SCL , PHASE SHIFTER 2 5 7 I2C BUS DECODER + LATCHES MONO 6 4 + + 1 L-OUT MONO SCL SDA ADDR DIG_GND + MONO + 2 , vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL , data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop


Original
PDF TDA7467 DIP28 TDA7467 TDA7467D TDA7467D013TR$
Not Available

Abstract: No abstract text available
Text: SRS labs specificaPIN CONNECTION (Top view) LOUT C RIN C LIN C DIG J3N D C SCL C ADDR C SDA C AGND C , BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage , signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH tran sition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must con tain 8


OCR Scan
PDF TDA7467 DIP28 TDA7467 1997SGS-THOMSON
2011 - Not Available

Abstract: No abstract text available
Text: Measurement Range 0 to 2000 ppm* 0.38 in (9.65 mm) 1.75 in ( 44.45 mm) 2 Mounting Holes à , I2C SCL 6 No Connect 7 I2C SDA 8 No Connect 9 No Connect 10 TX (UART


Original
PDF T6613 T6613-F T6613-C T6613-R12 T6613-5K T6613-5KF T6613-5KC 920-448G
2011 - infrared gas sensors

Abstract: No abstract text available
Text: (9.65 mm) 1.75 in ( 44.45 mm) 2 Mounting Holes Ø.105 (2.667) 0.15 in (3.81 mm) Dimensions , SCL 6 No Connect 7 I2C SDA 8 No Connect 9 No Connect 10 TX (UART) 11


Original
PDF T6615 T6615-50K T6615-F T6615-50KF T6615-10KF T6615-5KF T6615-R12 920-474C infrared gas sensors
1994 - TDA7300 audio processor circuit

Abstract: TDA7300D bass treble simply diagram tda7300 DIP28 3 db attenuator
Text: SDA, SCL , SEN. If SDA and SEN inputs are short-circuited together, then the TDA7300 appears as a , supply voltage via pull-up resistors. LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. S-bus: the start/stop conditions (points 1 and 6) are detected exclusively by a transition of the SEN line (1 0 / 0 1) while the SCL line is at the HIGH level. The SDA line is only allowed to change during the time the SCL line is


Original
PDF TDA7300 TDA7300 DIP28 TDA7300D TDA7300 audio processor circuit TDA7300D bass treble simply diagram DIP28 3 db attenuator
1997 - 5.1 surround sound circuits

Abstract: 5.1 surround sound diagrams DIP28 TDA7467 TDA7467D
Text: SCL 5 24 HP6 ADDR 6 23 HP5 SDA 7 22 HP4 AGND 8 21 VS , 5 1 R-OUT DIG_GND ADDR SDA SCL L-OUT TDA7467 BLOCK DIAGRAM TDA7467 , the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data , . The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is , the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while


Original
PDF TDA7467 DIP28 TDA7467 5.1 surround sound circuits 5.1 surround sound diagrams DIP28 TDA7467D
1996 - Not Available

Abstract: No abstract text available
Text: amplifiers according to the SRS labs specificaPIN CONNECTION (Top view) LOUT RIN LIN DIG_GND SCL ADDR SDA , 4.7nF 0.47nF 1µ F 0.1 µF 0.1µ F 1µF 0.1µ F L-OUT MONO SCL SDA ADDR DIG_GND + SRS MONO + 2 SRS FIX VREF , through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to , change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH


Original
PDF TDA7467 TDA7467
TDA7300 audio processor circuit

Abstract: TDA7300D DIP28 package tda7300 DIP28
Text: SDA, SCL , SEN. If SDA and SEN inputs are short-circuited together, then the TDA7300 appears as a , supply voltage via pull-up resistors. LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. S-bus: the start/stop conditions (points 1 and 6) are detected exclusively by a transition of the SEN line (1 0 / 0 1) while the SCL line is at the HIGH level. The SDA line is only allowed to change during the time the SCL line is


Original
PDF TDA7300 TDA7300 DIP28 TDA7300D TDA7300 audio processor circuit TDA7300D DIP28 package DIP28
1997 - DIP28

Abstract: TDA7467 TDA7467D
Text: SCL 5 24 HP6 ADDR 6 23 HP5 SDA 7 22 HP4 AGND 8 21 VS , LP2 0.1µF R-OUT DIG_GND ADDR SDA SCL L-OUT TDA7467 BLOCK DIAGRAM , wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply , clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH


Original
PDF TDA7467 DIP28 TDA7467 DIP28 TDA7467D
1999 - DIP28

Abstract: TDA7319 TDA7339
Text: 11 TREBLE MIDDLE BASS 2nd VOL MUTE 3x 2.2µF VS 1st VOL 1 SCL SDA ADDR , CMUTE 11 18 ADDR OUT L 12 17 OUT R SDA 13 16 AGND SCL 14 15 , and SCL (pull-up resistors to positive supply voltage must be externally connected). Data Validity , HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW , line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is


Original
PDF TDA7339 DIP28 TDA7339 DIP28 TDA7319
philips tv tuner 3139 147

Abstract: colour tv sound section ic diagram tv Philips 14 FR1246 12 pin tv tuner module Philips 3139 147 colour tv power supply system ic tuner 3139 147 tuner philips 3139 147 EN55020
Text: Desktop video & radio module i . system CCIR I PINNING SYMBOL AGC ADC VT Vs(tuner) SCL SDA AS P3 FM-IF , © © © TH4 O O 12 13 14 15 0.64 * 0.64 OO 4.445 TH3 . " B- 0- « ik - 3 ti" ^ - b- a- g


OCR Scan
PDF FR1246 philips tv tuner 3139 147 colour tv sound section ic diagram tv Philips 14 FR1246 12 pin tv tuner module Philips 3139 147 colour tv power supply system ic tuner 3139 147 tuner philips 3139 147 EN55020
Supplyframe Tracking Pixel