The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LF198S Linear Technology IC SAMPLE AND HOLD AMPLIFIER, PDSO, Sample and Hold Circuit
LF198AS Linear Technology IC SAMPLE AND HOLD AMPLIFIER, PDSO, Sample and Hold Circuit
LF198AJ8 Linear Technology IC SAMPLE AND HOLD AMPLIFIER, CDIP8, Sample and Hold Circuit
LF198AN8 Linear Technology IC SAMPLE AND HOLD AMPLIFIER, PDIP8, Sample and Hold Circuit
LF198J8 Linear Technology IC SAMPLE AND HOLD AMPLIFIER, CDIP8, Sample and Hold Circuit
LT1490AIS8#TRA1PBF Linear Technology Dual and Quad Micropower Rail-to-Rail Input and Output Op Amps

schematic of TTL AND Gates Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
full adder using ic 74138

Abstract: full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 Application of Multiplexer IC 74151 IC 74138 74138 IC decoder Multiplexer IC 74151
Text: designs described in TTL schematic form. A complete set of design drawings and design compilation , capable of implementing up to 2100 equivalent gates of custom and conventional logic. · Pre-programmed to contain 14 MSI TTL functions for user evaluation. · May be erased for other uses upon completion of , . The device supports a range of complexities up to 2100 equivalent 2-input NAND or NOR gates . The speeds and density of the EP1800 series make it suitable for LSI replacement of Low power Schottky TTL in


OCR Scan
PDF EP1800JC-EV1 EPt800 68-pin EP1800JC-EV1 0UT20 0UT21 OUT22 0UT23 full adder using ic 74138 full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 Application of Multiplexer IC 74151 IC 74138 74138 IC decoder Multiplexer IC 74151
ns 4248

Abstract: Toggle flip flop THREE INPUT TTL OR GATE DUAL FLIP FLOP TRISTATE
Text: 560 640 864 1.232 1.664 2.016 t * Useable Gates - 27% times number of Logic Cells plus 9 times , Data Selector 2 Line to 1 Line Data Selector/Multiplexer Other Gates Internal TTL Schmitt Trigger , arrays are constructed using two types of elements: Logic Cells, consisting of two n-channel and two , . Each of these devices can be implemented in a wide variety of DIP, PLCC, PGA or FLAT packages ranging , Cells: - CMOS/ TTL Schmitt - Bi-directional - Open Drain - Push-pull - Tri-state - High Drive (24 mA) -


OCR Scan
PDF MSM10V0000 ns 4248 Toggle flip flop THREE INPUT TTL OR GATE DUAL FLIP FLOP TRISTATE
ttl74

Abstract: TTL138 TTL74 series 2-input OR gate 7400 family TTL244 TTL06 TTL373 QL16X24 ttl273 marking code JRW
Text: programming element insures a technology migration path to devices of 20,000 gates and above. Designs are , will allow the development of pASIC devices with tens of thousands of usable gates . QuiacLoGic 4 This , "gate array gates ." As a typical application will use 10 to 12 of these gates , the QL8xl2 is described , insuring maximum logic flexibility. The logic cell consists of two 6-input AND gates , four 2-input AND , determined by the logic levels applied to the inputs of the AND gates . ViaLink sites located on signal wires


OCR Scan
PDF 16-bit ttl74 TTL138 TTL74 series 2-input OR gate 7400 family TTL244 TTL06 TTL373 QL16X24 ttl273 marking code JRW
shiftregisters

Abstract: EP910 altera TTL library LSI Replacement altera logicaps TTL library PLE40 EP610 EP1810-45 EP1810 74LS
Text: • Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of , independent clocking of all registers. • Accepts popular TTL SSI and MSI based Macro-Function design inputs , of CMOS EPLDs from Altera offer LSI density, TTL equivalent speed performance and low power consumption. Each device is capable of implementing over 2100 equivalent gates of SSI, MSI and custom logic , blocks as well as simple, optimized gate and flip-flop elements. Schematic descriptions of these


OCR Scan
PDF
dc cdi schematic diagram

Abstract: cdi schematic DD139 Newmarket Microsystems Newmarket Transistors cdi schematic diagram DD193 DD240 level shifter from TTL to CMOS bidirectional Newmarket Transistors 275
Text: conventional standard cells. ■Typical delays of 1.1 ns for 2 input NAND gates with FO=2 plus interconnect , performance family of HCMOS devices ranging in complexity from 3,528 to 21,336 equivalent 2-input gates , location) Figure 1. CSB8000 Series Array Structure CORE LOGIC UTILIZATION The number of usable gates for , number of usable gates in the array. The most important factor determining the routability of a logic , appropriate array size. By running this program after completion of schematic capture the logic can be


OCR Scan
PDF CSB8000 11-87/Printed dc cdi schematic diagram cdi schematic DD139 Newmarket Microsystems Newmarket Transistors cdi schematic diagram DD193 DD240 level shifter from TTL to CMOS bidirectional Newmarket Transistors 275
dc cdi schematic diagram

Abstract: Ac cdi schematic diagram DM30ND California Devices cdi schematic level shifter . CMOS to TTL D334 transistor TTL TRANSISTOR MODEL PARAMETER transistor BC 945 cdi schematics
Text: gates with FQ = 2 plus interconnect capacitance. ■Flexible I/O programmability compatible with TTL , . DLM SERIES FAMILY ORGANIZATION Part Number Available Gates Number of Cells Maximum Pads Maximum , demands of the high drive output buffers, input TTL level shifters, and core logic. To improve noise , application-specific integrated circuits. The customer submits a schematic diagram describing the circuit in terms of , silicon gate HCMOS technology, ■From 210 to 10,152 equivalent 2-input gates . ■Double layer metal


OCR Scan
PDF T-42-11 D-6050 5M85/Prlnted dc cdi schematic diagram Ac cdi schematic diagram DM30ND California Devices cdi schematic level shifter . CMOS to TTL D334 transistor TTL TRANSISTOR MODEL PARAMETER transistor BC 945 cdi schematics
ac cdi schematic diagram

Abstract: dc cdi schematic diagram cdi schematic California Devices cdi circuit diagram off grid inverter schematics equivalent transistor bc 107 cdi wiring diagram "california devices" cdi schematics
Text: – Typical delays of 2 ns for 2 input NAND gates with FO = 2 plus interconnect capacitance. ■Flexible I/O , family of HCMOS devices ranging in complexity from 210 to 10,152 equivalent 2-input gates manufactured , assured because of the flexibility allowed in the basic cell for programming either logic gates , metal bus lines are provided for high current demands of the high drive output buffers, input TTL level , customer submits a schematic diagram describing the circuit in terms of standard MSI and SSI functions


OCR Scan
PDF pi880 D-6050 5M85/Printed ac cdi schematic diagram dc cdi schematic diagram cdi schematic California Devices cdi circuit diagram off grid inverter schematics equivalent transistor bc 107 cdi wiring diagram "california devices" cdi schematics
quicklogic pasic

Abstract: No abstract text available
Text: technology migration path to devices of 20,000 gates and above. Designs are entered into the pASIC Family , pASIC devices with tens of thousands of usable gates . Q u ic k Lo g ic 4 pASIC 1 FAMILY S , up to 30 "gate array gates ." As a typical application will use 10 to 12 of these gates , the QL8xl2 , consists of two 6-input AND gates , four 2-input AND gates , three 2-to-l multiplexers and a D flip-flop. As , gates . ViaLink sites located on signal wires tied to the gate inputs perform the dual role of


OCR Scan
PDF 16-bit quicklogic pasic
Not Available

Abstract: No abstract text available
Text: utilization ranging from 2,600 to 130,000 usable gates · I/O counts from 60 to 320 reduce the number of , circuitry, capable of sourcing and sinking currents up to 16mA, responding to either CMOS or TTL logic , usable gates . This efficient nnilini; scheme combined with close spacing for both metal layer«! allow s , Gates Usable Gates Total Pins I/O ATL4 4K 2.6K 86 60 ATL10 10K fi.5K 124 116 ATL20 22 K 12K 144 136 , Atmel's gate array cell library. Library Atmel provides the cell library, with schematic symbols, func


OCR Scan
PDF ATL10 ATL20 ATL60 ATL130 ATL260
Altera EP1800

Abstract: EP1800 JEDEC FORMAT EP1800 altera logicaps TTL library SCHEMA PA BUILT UP EP1800 LOGIC DIAGRAM ep18001
Text: Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of , is capable of implementing over 2100 equivalent gates of SSI, MSI and custom logic circuits. The , as simple, optimized gate and flip-flop elements. Schematic descriptions of these functions are , complete logic schematic and automatically re moves unused gates and flip-flops from any MacroFunction , PRIMITIVE LIBRARY The Primitive library consists of 80 low-level logic gates , flip-flop, and I/O symbols


OCR Scan
PDF EP1800 Altera EP1800 EP1800 JEDEC FORMAT EP1800 altera logicaps TTL library SCHEMA PA BUILT UP EP1800 LOGIC DIAGRAM ep18001
LC6000

Abstract: LSI CMOS GATE ARRAY IC 7400 NAND Signal Path Designer IC TTL 7400 quiescent power
Text: applications such as TTL replacement, boardspace reduction and logic optimization. Designs of 700-6700 gates , bASIC arrays. A range of seven array sizes from 1968 to 19000 gates is offered with each gate equivalent , periphery. Each gate consists of two n-channel and two p-channel transistors. These gates can be configured , library supports many of the familiar TTL equivalent functions. Table 2 lists some commonly used , structure the complete schematic as a set of functional subsystems such as a 16-bit ALU, a data receiver, a


OCR Scan
PDF LMb6000 LC6000 LSI CMOS GATE ARRAY IC 7400 NAND Signal Path Designer IC TTL 7400 quiescent power
dc cdi schematic diagram

Abstract: ac cdi schematic diagram level shifter from TTL to CMOS bidirectional cdi schematic d flip flop using gdi techniques a8508 cdi wiring diagram cdi schematics California Devices transistor BC 945
Text: – Typical delays of 1.1 ns for 2 input NAND gates with FO = 2 plus interconnect capacitance. ■Flexible I , Number Available Gates Number of Cells Maximum Pads Maximum Inputs* Maximum Outputs CHA 200 t 210 140 , of the flexibility allowed in the basic cell for programming either logic gates , interconnect, or , metal bus lines are provided for high current demands of the high drive output buffers, input TTL level , submits a schematic diagram describing the circuit in terms of standard MSI and SSI functions along with


OCR Scan
PDF FjorrL21Q 3M95/Printed dc cdi schematic diagram ac cdi schematic diagram level shifter from TTL to CMOS bidirectional cdi schematic d flip flop using gdi techniques a8508 cdi wiring diagram cdi schematics California Devices transistor BC 945
schematic diagram NAND gates

Abstract: logic gates circuit diagram schematic of TTL OR Gates sama logic schematic diagram AND gates pin configuration of logic gates signetics nand gates logic gates pin configuration Buffers NAND Gates
Text: programmable LSI • 2016 ISL (NAND) gates • 72 Schottky buffers • 76 I/O buffers • LS TTL compatible , package PRODUCT DESCRIPTION The 8A2176 Gate Array (Figure 1) is an uncommitted array of ISL gates (Figure 2), Schottky buffers (Figure 3) and LSTTL-compatible I/O cells. Thus, up (o 2016 gates can be custom interconnected to provide the advantages of both Large Scale Integration (LSI) and proprietary , interconnecting 2016 ISL NAND gates , using two layers of metal routing. Seventy-two Schottky buffers are provided


OCR Scan
PDF 8A2176 24-milliampere schematic diagram NAND gates logic gates circuit diagram schematic of TTL OR Gates sama logic schematic diagram AND gates pin configuration of logic gates signetics nand gates logic gates pin configuration Buffers NAND Gates
1996 - XC5200

Abstract: RAM32X8 RAM32X4 RAM16X4 Xilinx XC4006-6 XC4000 XC4000H ROM32X1 XC4000D XC4000A
Text: XC5200. Table 1: Comparison of Resources Between XC4010, XC5206, and XC5210 Resource Max Logic Gates , Cascadable versions of decoders, using CY_MUX. Use these to create AND gates wider than 16 inputs. In , frequency, of which only three can be used in a design. After converting a schematic , the OSC5 symbol will , will have to be removed in the XC5200 version of the schematic . Three-State Buffers Like the , , 1996 (Version 2.0) XC4000H I/O allow per-pin designation of CMOS or TTL input thresholds and


Original
PDF XC4000 XC5200 XC5200 RAM32X8 RAM32X4 RAM16X4 Xilinx XC4006-6 XC4000H ROM32X1 XC4000D XC4000A
1995 - 16-LINE TO 4-LINE PRIORITY ENCODERS

Abstract: RS flip flop cmos 16-to-4 line priority encoder 32-Bit Parallel-IN Serial-OUT Shift Register encoder 74174 DSTD190 CMOS Quad 2-Input NOR Gate RS flip flop T Flip-Flop jk flip flop to d flip flop conversion
Text: of JEDEC files to be read and modelled so that the schematic representations of the designs can be , listing of the topics covered in this application note: · The Atmel-ViewPLD Menu Commands " Schematic , unused pins of a DSTD symbol · Creating a Viewdraw schematic from an ABELTM or a JEDEC file · , the WORKVIEW\STANDARD or WORKVIEW\ATMEL directory. The process of compiling the schematic to the , schematic capture and ABEL HDL design entries in the same design. In addition, old designs which consist of


Original
PDF thD882 32-Bit DSTD90 DSTD91 DSTD92 Divide-by-12 DSTD93 DSTD94 ATV5000 ATV5100 16-LINE TO 4-LINE PRIORITY ENCODERS RS flip flop cmos 16-to-4 line priority encoder 32-Bit Parallel-IN Serial-OUT Shift Register encoder 74174 DSTD190 CMOS Quad 2-Input NOR Gate RS flip flop T Flip-Flop jk flip flop to d flip flop conversion
dc cdi schematic diagram

Abstract: ac cdi schematic diagram cdi schematic oz 8602 gm dm165 DM240 CMOS 4000 Series family databook DM195 cdi schematics DM273
Text: – Typical delays of 1.4 ns for 2 input NAND gates with FO=2 plus interconnect capacitance. 9957S> ■Flexible I/O programmability compatible with TTL or ffSlS-MOS logic families. 7S3 ■High ESD protection , assured because of the flexibility allowed in the basic cell for programming either logic gates , application-specific integrated circuits. The customer submits a schematic diagram describing the circuit in terms of , -input gates . ■Double layer metal used for global and intracell routing. ■Wide operating supply range


OCR Scan
PDF 9957S> 8602-R1 5M11-86/Printed dc cdi schematic diagram ac cdi schematic diagram cdi schematic oz 8602 gm dm165 DM240 CMOS 4000 Series family databook DM195 cdi schematics DM273
Not Available

Abstract: No abstract text available
Text: ) technology with standard ECL or TTL I/O compatibility to provide the optimum balance of radiation hardness , Optimizing System Performance vs. Power in Air Cooled Systems: - Logic to Power Densities of 750 Gates /Watt , and ECL are faster than TTL . Both CML and ECL use a differential pair of NPN transistors for switching current. Circuit diagrams of the basic OR/NOR gates for CML and ECL appear similar, but they differ in , 's emitter-follower driver is eliminated. The single differential pair of CML gates drive following gates directly


OCR Scan
PDF HM3500R, HVM10000R to172 148-Pin 244-Pin M2010, M2023 M1008,
1998 - schematic of TTL XOR Gates

Abstract: TTL XOR Gates ttl 2-bit half adder cmos XOR Gates schematic XOR Gates xnor ttl ALU of 4 bit adder and subtractor "XOR Gates" XNOR GATE cmos gate nand nor xor
Text: technology Operating voltage: 5V/3V Propagation delay of 2-input NAND with fanout=2 ­ 0.3ns for 5V high , cell usage ­ Up to 40K gates for high performance ­ Up to 60K gates for high density · · · · , Buffers ­ Inverting, noninverting, tri-state, clock buffer NAND/AND gates NOR/OR gates AOI/OAI gates XNOR/XOR gates D Flip-Flops T Flip-Flops Multiplexed Flip-Flops JK Flip-Flops Latches ­ with set , NAND/AND gates NOR/OR gates AOI/OAI gates XNOR/XOR gates D Flip-Flops T Flip-Flops Multiplexed


Original
PDF
8284 clock generator

Abstract: 8 bit barrel shifter barrel shifter with flip flop 8259 Programmable Interrupt Controller 8254 programmable interval timer 8254 aa 80286 schematic B180 schematic diagram ac-dc inverter MSM91U000
Text: Customers supply Oki with a TTL level schematic of their logic, test vectors, AC and DC specifications and , building block topology allow designs up to 40,000 gates to be obtained. The standard cell design process , designs to be easily converted from gate arrays to standard cells. Oki has a wide variety of DIP, PLCC, PGA or FLAT packages ranging from 14 to 299 pins. Oki supports a wide range of flexible interfaces on , , applications programs and documentation are available upon customer requests. Oki is also capable of


OCR Scan
PDF b724240 MSM91U000 MSM91U000 b7Z43M0 T-42-4] 8284 clock generator 8 bit barrel shifter barrel shifter with flip flop 8259 Programmable Interrupt Controller 8254 programmable interval timer 8254 aa 80286 schematic B180 schematic diagram ac-dc inverter
EP1810JC-35

Abstract: programming manual EP910 EP1810LC-35 OLC-45 EP1810JC35 programming manual EPLD EP1810LI-45 EP1810JC EP1810I 48-MACROCELL
Text: . Schematic descriptions of these functions are stored in a library. The desired TTL logic functions are , -REVISED AUGUST 1989 Erasable, User-Configurable LSI Circuit Capable of Implementing 2100 Equivalent Gates of , offer LSI density, TTL equivalent speed performance and iow power consumption. Each device is capable of implementing over 2100 equivaient gates of SSI, MSI and custom logic circuits. The EP1810 series is packaged as , EP1810 maerocell can accommodate the équivalent of 40 gates . to other macrocells equivalent gates - 40


OCR Scan
PDF EP1810 48-MACROCELL D3232. 1989-REVISED 33-MHz 68-pin 28Cll EP1810JC-35 programming manual EP910 EP1810LC-35 OLC-45 EP1810JC35 programming manual EPLD EP1810LI-45 EP1810JC EP1810I
full adder using Multiplexer IC 74151

Abstract: 74151 MUX 8-1 full subtractor using ic 74138 pin configuration IC 74151 Multiplexer IC 74151 modulo 16 johnson counter MUX 74157 MUX 74151 16 bit comparator using 74*85 IC binary to gray code conversion using ic 74157
Text: functions. To isolate adjacent macrocells. the gates of one or more p or n channel transistors are fused to , the gates of the p-channel transistors in the TPTs. These lines can also be used as global signals , optimize design trade-offs such as performance vs. size of the circuit. Schematic Symbols: Schematic , design methodologies. This enables design engineers to use familiar gate array tools for schematic entry , expectations." CDS is a trademark of Crosspoint Solutions, Inc. Macintosh is a registered trademark of Apple


OCR Scan
PDF
74LS82

Abstract: 74LS176 74LS94 74LS286 74ls150 74LS177 74LS116 74ls198 7400 TTL 74ls521
Text: fabricated in silicon. The main advantage of using 7400 TTL Cells is the reduced design time for most system , TTL Cells can also be combined into a schematic and simulated with other Gould library functions , process and implementation of choice. Designs with 7400 TTL Cells (alone or in combination with other , design making it use more silicon area than necessary. The combination of Gould's 7400 TTL Cells and Gate , implementation, e.g., in a gate array instead of a standard cell, the steps after schematic capture described


OCR Scan
PDF
T157WG

Abstract: S-MOS navnet A138G2 t177 4-bit full adder using nand gates and 3*8 decoder 6 input or gate SLA1024 T161RE
Text: consists of 11 arrays ranging from 9,000 to 101,800 usable gates and from 128 to 432 I/O. The SLA10000 series has been tailored for high performance designs with typical gate delays of .3 nanoseconds , , logic simulation and timing verification up to 6,000 gates using PCs with 640K of memory or up to 20,000 gates in PCs equipped with 4 megabytes of extended memory. * Standard Cell Migration The SLA10000 Series , selectable output drive capability of 2,6,12 or 24 mllllamps (two output buffers can be used in parallel to


OCR Scan
PDF GG01522 SLA10000 SSC5000 B8259 B8237 B82284 B8255 T157WG S-MOS navnet A138G2 t177 4-bit full adder using nand gates and 3*8 decoder 6 input or gate SLA1024 T161RE
1998 - Logic Buffered

Abstract: Delay Lines APP1_LOG A Simple Rise and Fall Time Waveform Control schematic of TTL OR Gates Delay Modules "Delay Modules" MIL-D-83532 for the construction of cmos logic gates
Text: to drive a higher number of gates of a more complicated topology with minimal effect on signal , adjustment is required. Also, by incorporating the functions of multiplexers or logic gates , active lines , Schematic D7 8 to 1 MUX Minimum Pulse Width and BW Limitations: Although the output rise time of , physical switching properties of integrated circuits. For example, the logic "1" threshold of TTL devices is 2.0 Vdc minimum, at approximately 50% of the margin between the typical TTL low and high levels


Original
PDF
m60013

Abstract: M60016 m60011 M60014 z46n M60030 M60024 Z24N M60012 m60043
Text: transistors) instead of two-input NAND gates increases gate utilization. This three-input NAND example , M60053 M60054 M60055 M60056 M60057 Number of Usable Gates 5,000 6,000 8.000 10.000 12,000 15,000 25 , ) architecture, providing variable-sized routing channel widths for efficient use of gates . Figure 3 shows an , M60032 M60034 M60035 M60037 Number of Usable Gates 224 507 800 1,104 1,773 2,400 3,200 4,100 6,300 , M60044 M60045 M60047 M60049 Number of Usable Gates 2,400 3,200 4,100 6.300 8,400 Maximum I/O Ports


OCR Scan
PDF MDS-GA-11-90-RK m60013 M60016 m60011 M60014 z46n M60030 M60024 Z24N M60012 m60043
Supplyframe Tracking Pixel