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LT1111CJ8 Linear Technology SWITCHING REG ADJ. OUT
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register file Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1997 - register file

Abstract: UM97Z8X0104 00H-03H
Text: for the Z8® MCU: s s The Z8 Standard Register File contains addresses for peripheral, control, all general-purpose, and all I/O port registers. This is the default register file specification , data only, whether internal or external. The Z8 Expanded Register File (ERF) contains addresses , FILE The Z8 Standard Register File totals up to 256 consecutive bytes (Registers). The register file , (F0H-FFH). Table 2-1 shows the layout of the register file , including register names, locations, and


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PDF UM97Z8X0104 register file UM97Z8X0104 00H-03H
2000 - register file

Abstract: 54SX-A bgn-tn
Text: double-word register file and two state machines. The register file can be clocked at either the PCI rate or , the data through the register file . One of the state machines runs at the PCI rate and the other runs at the back-end rate to load and unload the register file . The back-end state machine can be , transferred to and from the register file in either one or four, 32-bit wide word sub-bursts. Four-word , blocks shown in Figure 2 on page 3. These blocks are the register file , the PCI-loading state machine


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PDF A54SX A54SX72A A54SX16A, A54SX16P, A54SX32A, register file 54SX-A bgn-tn
2000 - Not Available

Abstract: No abstract text available
Text: double-word register file and two state machines. The register file can be clocked at either the PCI rate or , the data through the register file . One of the state machines runs at the PCI rate and the other runs at the back-end rate to load and unload the register file . The back-end state machine can be , to and from the register file in either one or four, 32-bit wide word sub-bursts. Four-word , blocks shown in Figure 2 on page 3. These blocks are the register file , the PCI-loading state machine


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PDF A54SX A54SX72A A54SX16A, A54SX16P, A54SX32A,
SM85CPU

Abstract: No abstract text available
Text: ] General register [word] Register file (0000 h-007F h) and (0080 h-00FF h) [byte] Register file (0000 h , Implied Register Register pair Register file Register file pair Register indirect Register indirect auto , immediate data in the instruction code [word] Register file (0000 h-007F h) and memory (0080hOOFFh, FFOOh-FFFFh) [bit] (1 bit of 1 byte pointed by R, n(r) and DAp) Register file (001 0 h-001 7 h) [byte] Bit , within OOOOh-OOFFh. Although the general purpose registers are members of the register file , which


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PDF SM8504/SM8506 SM85CPU SM85CPU 16-bit
1998 - F15-F8

Abstract: block alu R7F7 ODJ01 R11F1 AVS service manual circuits ADSP-21065L ADSP-2100 00FF R5F5
Text: 's Manual 2-1 PM Data Bus DM Data Bus Register File Shifter Multiplier ALU 16 × 40 , ten-port register file . The Register File is accessible to the processor's program memory data (PMD) bus , topics: · Data formats · Register File data storage and transfers · ALU architecture and operations , User's Manual &RPSXWDWLRQ8QLWV 5HJLVWHU)LOH The Register File provides the interface between , operands and results. The Register File has these structural and functional characteristics: · Consists


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PDF ADSP-21065L R10--F10 R11--F11 R12--F12 R13--F13 R14--F14 R15--F15 F15-F8 block alu R7F7 ODJ01 R11F1 AVS service manual circuits ADSP-2100 00FF R5F5
Register

Abstract: type register
Text: immediate data and condition codes, all operands are expressed as register file or Program Memory addresses , register in the current page of the register file . Register File Program Memory 8-Bit Register , Register in the Register File Figure 2-1. 8-Bit Register Addressing 7/<: Register File RP Program Memory Operand 4-Bit Working , Instruction (Example) OpCode Points to One Register in the Register File Figure 2-2. 4


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PDF 12-bit 000H-FFFH. 16-bit 0000H-FFFFH. Register type register
register file

Abstract: 2019H 0H17H memory interface 8255 8XC196KC chapter 4 memory partitions 8XC196KC instruction set 8XC196KC chapter 5 interrupts 8XC196kc 8216 INTEL 8XC196KC instructions
Text: External Memory + 4 1FFH OH 3FFH OH Register File * Always write Ports 3 and 4 as a single word , 200H-1FFDH 512-6189 400H-1 FFDH 1024-8189 Register File (includes SFRs) 0H-1FFH 0-511 0H-3FFH 0-1023 NOTES , Register File are always assigned to external memory or I/O (see Figure 4-1 or Table 4-1). The 8XC196KC/KD , Memory \ Lower Interrupt Vectors 1FFH 3FFH Register \ \ \ 2000H OH OH File A0090-D0 Figure , (see Appendix C, "8XC196KC/KD Registers"). 4-5 Intel. MEMORY PARTITIONS 4.4. REGISTER FILE The


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PDF 8XC196KC 8XC196KD. 8XC196KD 8XC196KC. 6000H 0A000H 2080H 2080H register file 2019H 0H17H memory interface 8255 8XC196KC chapter 4 memory partitions 8XC196KC instruction set 8XC196KC chapter 5 interrupts 8216 INTEL 8XC196KC instructions
register file

Abstract: d2936 Parity Checkers SN74AS883 036 84, 036 85, 036 86 rondorex w21 TRANSISTOR Y1D PS1J rab5 Y29NC F119
Text: PRODUCT PREVIEW SN54AS8B34, SN74AS8834 40-BIT REGISTER FILE d2936, november 1985 , File • Supports 'AS888 and AS8832 Register File Expansion • Four 10-Bit Input Ports with , files in a 1 56-pin ceramic pin grid array. The register files are designed to support register file , «HB-BS WiL-üüi «SjltliU^ 40-BIT REGISTER FILE ■A SB 8 34 IO9-D0I 1019-0101 1O29-D201 (D39-D301 , Respective Manufacturer SN54AS8834, SN74AS8834 40-BIT REGISTER FILE sn54as8834. sn74as8834 gb


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PDF SN54AS8B34, SN74AS8834 40-BIT d2936, 1985-revised 64-Word AS888 AS8832 10-Bit register file d2936 Parity Checkers SN74AS883 036 84, 036 85, 036 86 rondorex w21 TRANSISTOR Y1D PS1J rab5 Y29NC F119
1997 - 8 BIT ALU

Abstract: register file 16 bit alu alu datasheet 00FF ADSP-2100
Text: next cycle. The computation units input data from and output data to a 10-port register file that consists of sixteen primary registers and sixteen alternate registers. The register file is accessible to , and external memory or other parts of the processor. The individual registers of the register file , REGISTER FILE MULTIPLIER SHIFTER ALU 16 x 40-bit MR2 MR1 MR0 Figure 2.1 Computation , Multifunction Computations Register File and Data Transfers 2.2 IEEE FLOATING-POINT OPERATIONS The


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PDF ADSP-2106x R15-R8 F15-F8) 8 BIT ALU register file 16 bit alu alu datasheet 00FF ADSP-2100
1998 - register file

Abstract: ADSP-2100 ADSP-21000 ADSP-21160 RND32
Text: -bit data values. The register file source or destination of such an access is two adjacent data registers , significant 8 bits forced to zero on stores and truncated on loads. The register file source or destination , -bit accesses. The register file source or destination of such an access is a single 40-bit data register with , -bit width accesses occur as the result of an access to short word address space. The register file source , DATA BUS MUX 64 HOST PORT MULT DATA REGISTER FILE (PEx) 16 x 40-BIT BARREL SHIFTER


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PDF ADSP-21160s 64-bit ADSP-21160 32-bits, 40-bit register file ADSP-2100 ADSP-21000 RND32
1990 - 2901s

Abstract: 4 bit ALU USING VLSI 8 BIT ALU design by cmos 8 BIT ALU by 74181 alu 74181 functional diagram of ALU IDT49C402A register file 16 BIT ALU design with 74181
Text: counter-type operations where constants may be in the register file in order CORDIC-type algorithms. Put , high-speed, fully cascadable 16-bit CMOS ALU slice with 64-by-16-bit register file . It combines the , from the D inputs into the register file and Q register . Normally, the loading of the register file , direct data input path through the ALU and then store the results in the register file or Q register . With the new data path, the data can be put directly into the register file in parallel with other


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PDF IDT49C402A 16-bit 20MHz 2901s. 32-Bits IDT74FCT374A 2901s 4 bit ALU USING VLSI 8 BIT ALU design by cmos 8 BIT ALU by 74181 alu 74181 functional diagram of ALU register file 16 BIT ALU design with 74181
weitek 1066

Abstract: WEITEK register file Weitek 1233 WTL1232 wtl 1232 weitek 2264 sa wf 74AS74 tcl 1232
Text: WTL 1066 32 x 32 SIX PORT REGISTER FILE Features HIGH SPEED 32-BIT x 32-WORD REGISTER FILE , SUBSYSTEMS Description The WTL 1066 register file directly supports the WTL 1232/1233, WTL 2264/2265 and WTL 1264/1265 floating point subsystems. The register file has 32 words, each 32-bits wide, which are , major cycle. The WTL 1066 register file provides the necessary data bandwidth to fully utilize WEITEK , ported register file makes it possible to achieve high pipeline utilization in a wide variety of


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PDF 32-BIT 32-WORD 16-bit 64-bit CH-1227, weitek 1066 WEITEK register file Weitek 1233 WTL1232 wtl 1232 weitek 2264 sa wf 74AS74 tcl 1232
weitek

Abstract: 1066-10gcd weitek 1066 Weitek 1233 weitek 2264 WTL1066
Text: WTL 1066 32 x 32 SIX PORT REGISTER FILE July 1986 Features HIGH SPEED 32-BIT x 32-WORD REGISTER FILE WITH THREE READ PORTS AND THREE WRITE PORTS HIGH SPEED 200 million bytes-per-second total , operation EXPANDABLE Fully expandable for more bits per word and more words per register file Two six-port register files may be paralleled to create a true eight-port register file LOW POWER NMOS 3.2 watts maximum , Description The WTL 1066 register file directly supports the WTL 1232/1233, WTL 2264/2265 and WTL 1264/1265


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PDF 32-BIT 32-WORD 16-bit 64-bit weitek 1066-10gcd weitek 1066 Weitek 1233 weitek 2264 WTL1066
1998 - ADSP-21160

Abstract: I-PEX ADSP register file
Text: ) includes a data register file . The dual processing elements provide a SIMD (Single Instruction Multiple , * 0 0 0 0 * - - - - ! Rx, Ry = Any register file location; treated , . 'XSOLFDWH3URFHVVLQJ(OHPHQWV The ADSP-21160 contains an additional set of computation units and register file . This , storage for operands and results. There is one register file associated with each of the ADSP-21160s two processing elements. Each register file consists of 16 primary registers and 16 alternate (secondary


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PDF ADSP-21160 I-PEX ADSP register file
1999 - register file

Abstract: INTEL DX2 R223 R240 R244 R245 R255
Text: & Register file 3. Addressing Modes 4. Interrupt Controller 5. DMA Description 6. RCCU 7 , STACK POINTER FILE MICRO REGISTER SEQUENCER MMU Memory Management Unit FILE , FOR MEMORY (16 bits) AND REGISTER FILE (8 bits) - 6-bit BUS FOR INTERRUPT AND DMA (output on emulator , Processing Unit with a 8/16 bit Arithmetic Unit The Register File consisting of 256 Registers (directly , , byte, word data 14 addressing modes ® ST9+ TRAINING / CORE / 6 2. REGISTER FILE ST9


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PDF 16-bit register file INTEL DX2 R223 R240 R244 R245 R255
72720

Abstract: 1S34 TP register file
Text: Control Register in the Peripheral File (see figure 4). Writing a `V to an Interrupt Enable bit enables , (via a PRG instruction) to bit 0 and bit 7 o f the Security Lock Register in the Peripheral File (all , space divided into three basic areas: a Register File , a Peripheral File , and Memory. REGISTER FILE - The Register File resides In the lower 256 bytes o f system memory. The Register File contains the A Register , . The Stack resides in the Register File and Is accessed via a separate 8 bit Stack Pointer Register


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PDF 0D015H7 -W-19-05 Cycleas400ns 10MHz 250ns 16MHz MD400Q05/- 72720 1S34 TP register file
register file

Abstract: sn74as8832 AS8832 AS888 3 bit magnitude comparator
Text: -bit register file • Bit, byte, 16-bit and 32-bit operations • Configurable as quad 8-bit or dual 16 , 64-word register file is 36 bits wide to permit storage of the parity bits. Master/slave comparator , -word by 36-bit register file . Data and parity from the register file can be output on the DA and DB ports , an input mode to furnish external data to the register file or during master/slave operation as an , operand write to be performed at the register file simultaneously. An MQ shifter and MQ register can also


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PDF SN74AS8832 AS888 64-word 36-bit 16-bit 32-bit SIM74AS8832 DA/B31-DA/BO, Y31-Y0 register file AS8832 3 bit magnitude comparator
fpga 1553B

Abstract: MIL-STD-1553B FPGA 1F16
Text: FPGA. The FPGA architecture allocates a 34 x 16-bit register file for message processing: 32 registers , architecture, the S MMIT maps all 1553 message into the same 34 word register file . To support message , and subaddress/mode code data buffer. The S MMIT accesses the 36 x 16 register file with A(5:0), D , "XXXX16" for these read cycles. Register file location 116 must contain a value of 416. Register file locations 216 and 316 correspond to Data Pointer B and the Broadcast Data Pointer. Reserve register file


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PDF 16-bit MIL-STD-1553B fpga 1553B MIL-STD-1553B FPGA 1F16
AS888

Abstract: No abstract text available
Text: -port I/O architecture · Sim ultaneous A L U and register operations · 64-word by 36-bit register file · , out put port. T he 64-word register file is 36 bits wide to permit storage o f the parity bits. M , input data to the A L U or the 64-word by 36-bit register file . D ata and parity from the register file , ports allow a two-operand fetch and an operand write to be performed at the register file simultaneously , outputs See Table 2 Selects shifted ALU output See Table 8 Inhibits register file write See Table 5


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PDF SN74AS8832 32-Bit AS888 64-word 36-bit 16-bit DA/B31-D IESI03-IESIOO
1999 - VLIW architecture

Abstract: address generation unit vliw vector register file VLIW ieee 32 bit floating point multiplier
Text: Word Flow Control Register File Address Multiple Address Generation Unit Field Arithmetic , Register Program Counter Read Data 16-port Data Register File Multiple Address Generation Unit 8-port Address Register File Left Read Addr Left Write Addr Left Dual-port Data , computation Large multi-port data register file directly connected to parallel customizable operator block , unit incorporating an 8-port address register file which connects directly to two 2K word dual-port


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1994 - AN421

Abstract: "Overflow detection"
Text: limited. On ST9 devices, the system stack may be located in the Register File or in data memory space , . Figure 1. Example of Stack overflow detection in Register File Register File system registers System , initializes the system stack in groups D and C of the Register File . In the stack management of the ST9, the , the Register File , while the instruction: ld SSPLR,#SSTACK + 1 initializes the system stack pointer , Declaration and end of stack initialisation ; in RAM space or Register File


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1994 - register file

Abstract: st9 technical manual st9 technical AN421 r235
Text: limited. On ST9 devices, the system stack may be located in the Register File or in data memory space , . Figure 1. Example of Stack overflow detection in Register File Register File system registers System , initializes the system stack in groups D and C of the Register File . In the stack management of the ST9, the , the Register File , while the instruction: ld SSPLR,#SSTACK + 1 initializes the system stack pointer , Declaration and end of stack initialisation ; in RAM space or Register File


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register file

Abstract: B20B Parity Checkers d2936
Text: PRODUCT PREVIEW SNS4AS8834, SN74AS8834 40 BIT REGISTER FILE D 2936, N O V EM B ER I9 8 5 - R E , -Bit Register File Supports 'A S 8 8 8 and 'A S8 8 3 2 Register File Expansion logic sym b ol t 109-001 , . SN54AS8834, SN74AS8834 40-BIT REGISTER FILE SN 54A S8834. SN 74A S8834 G B PIN -G R ID -A R R A Y P A C K , , T E X A S 75265 SN54AS8834, SN74AS8834 40 BIT REGISTER FILE PIN N AM E NO. I/O D ESC R IP , ; low selects D A 20-D A 39. Clocks data into register file on rising edge. C LK DO D1 D2 D3 D4 D5 D6


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PDF SNS4AS8834, SN74AS8834 64-Word 40-Bit IO29D20) 10-Bit 156-Pin IDA39-OA20] IDB190B0I register file B20B Parity Checkers d2936
1996 - Z86CXX

Abstract: Z86C72 Z86C92 Z86L72 Z86L92 ram 512x8
Text: /Trackball Interface on P00 Through P03 is available on the L72 version. Expanded Register File Control , on Zilog's 8-bit microcontroller core with an Expanded Register File to allow access to register , spaces available to support a wide range of configurations: Program Memory, Register File , Expanded Register File . Extended Data RAM and Ex- ternal Memory. The register file is composed of 256/128 bytes , . The Expanded Register FIle consists of two additional register groups (F and D). External Memory is


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PDF Z86C72/C92/L72/L92 Z86C72 Z86C92 Z86L72 Z86L92 16-Bit 512x8 16-Bit Z86CXX Z86C72 Z86C92 Z86L72 Z86L92 ram 512x8
1996 - L16 "8 pin"

Abstract: Z86L06
Text: Expanded Register File Control Registers s One/Two Programmable 8-Bit Counter/Timers, Each with a 6 , -bit microcontroller core with the addition of an Expanded Register File to allow easy access to register mapped peripheral and I/O circuits. The Z86L03/L06/L16 offers a flexible I/O scheme, an efficient register and , , Register File , and Expanded Register File . The register file is composed of 60/124 bytes of , Analog Comparators Register File 142 x 8-Bit Port 2 I/O (Bit Programmable) Figure 1


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PDF Z86L03/L06/L16 Z86L03 Z86L06 Z86L16 512/K L16 "8 pin" Z86L06
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