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Part Manufacturer Description Datasheet Download Buy Part
LT1319CS Linear Technology IC INFRARED, RECEIVER IC, PDSO16, 0.150 INCH, PLASTIC, SO-16, Remote Control IC
LT1319CS#PBF Linear Technology IC INFRARED, RECEIVER IC, PDSO16, 0.150 INCH, PLASTIC, SO-16, Remote Control IC
LT1015MJ8/883B Linear Technology IC DUAL LINE RECEIVER, CDIP8, CERDIP-8, Line Driver or Receiver
LT1015CN8#PBF Linear Technology IC LINE RECEIVER, PDIP8, PLASTIC, DIP-8, Line Driver or Receiver
LT1103CY Linear Technology IC SWITCHING CONTROLLER, Switching Regulator or Controller
LT1015CJ8 Linear Technology IC LINE RECEIVER, CDIP8, 0.300 INCH, CERAMIC, DIP-8, Line Driver or Receiver

receiver CONTROLLER rx-2 Datasheets Context Search

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2005 - RX2 RC Car

Abstract: Remote Control Toy Car Receiver rx-2 IC REMOTE CONTROLLER toy car Z "RF Receiver" RX-2 Remote Control Toy Car Receiver IC car toys remote control electronic design rx2 REMOTE CONTROLLER toy car RC TOY CAR CIRCUIT DIAGRAM remote control toy car circuit diagram RX-2 -G receiver CONTROLLER rx-2
Text: 3 OSCI 2 10 FAN8100N/FAN8100MTC OSCO 1 VO2 Receiver Controller RX-2 11 , Q2 RF Signal R1 Q3 FORWARD Receiver Controller RX-2 10 FIN D1A 11 PVCCA , for an RC car application - for a Turbo function for Ch.A (five-function RF receiver chip RX- 2 , www.fairchildsemi.com FAN8100N/FAN8100MTC Low Voltage/Low Saturation 2 -CH DC Motor Driver , OUT2A GND 9 8 7 14 13 12 11 10 9 8 PVCCB VCC GND 2 3


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PDF FAN8100N/FAN8100MTC RX2 RC Car Remote Control Toy Car Receiver rx-2 IC REMOTE CONTROLLER toy car Z "RF Receiver" RX-2 Remote Control Toy Car Receiver IC car toys remote control electronic design rx2 REMOTE CONTROLLER toy car RC TOY CAR CIRCUIT DIAGRAM remote control toy car circuit diagram RX-2 -G receiver CONTROLLER rx-2
Not Available

Abstract: No abstract text available
Text: www.pericom.com 05/23/14 PI7C9X760B 2 I C-bus/SPI to UART Bridge Controller w/ 64 bytes of TX/RX FIFOs , XTAL2 VSS www.pericom.com 05/23/14 PI7C9X760B 2 I C-bus/SPI to UART Bridge Controller w , /14 PI7C9X760B 2 I C-bus/SPI to UART Bridge Controller w/ 64 bytes of TX/RX FIFOs 24 23 22 , to UART Bridge Controller w/ 64 bytes of TX/RX FIFOs 2.1 Auto-RTS Figure 2 shows RTS functional , N N+1 002aab040 (1) N = receiver FIFO trigger level. ( 2 ) The two blocks in dashed lines


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PDF PI7C9X760B 16C450 16Mbit/s PI7C9X760B PD-2100 PI7C9X760BBLE 16-Contact, PI7C9X760ABLE 24-Contact,
2014 - Not Available

Abstract: No abstract text available
Text: 14-0028 3 www.pericom.com 05/23/14 PI7C9X1170B 2 I C-bus/SPI to UART Bridge Controller w , www.pericom.com 05/23/14 PI7C9X1170B 2 I C-bus/SPI to UART Bridge Controller w/ 64 bytes of TX/RX FIFOs , to UART Bridge Controller w/ 64 bytes of TX/RX FIFOs 2.1 Auto-RTS Figure 2 shows RTS functional , N N+1 002aab040 (1) N = receiver FIFO trigger level. ( 2 ) The two blocks in dashed lines , PI7C9X1170B 2 I C-bus/SPI to UART Bridge Controller w/ 64 bytes of TX/RX FIFOs 3 Software flow control


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PDF PI7C9X1170B PI7C9X1170B 16C450 16Mbit/s PD-2100 PI7C9X1170BBLE 16-Contact, PI7C9X1170ABLE
1995 - Not Available

Abstract: No abstract text available
Text: or tape controller applications or for the optional byte timing lead in X.21. Channel A (B) Receiver , output indicates to the DMA controller that one or more characters are available in the receiver FIFO , controller (CDUSCC) SC68C562 DESCRIPTION The Philips Semiconductors SC68C562 Dual Universal Serial Communications Controller (CDUSCC) is a single-chip CMOS-LSI communications device that provides two independent, multi-protocol, full-duplex receiver /transmitter channels in a single package. It supports bit-oriented and


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PDF SC68C562 SC68C562 150pF 150pF 100pF SD00270 SD00219
2013 - Not Available

Abstract: No abstract text available
Text: data rate in the multiple of 2 on the receiver channel during auto-rate negotiation (1) Channel , divider if you plan to reconfigure the receiver channels to support data rate (in a multiple of 2 ). This , reconfiguration controller performs write transactions, read transactions, offset cancellation of the receiver , controller to dynamically reconfigure your receiver channel. Implementing Dynamic Reconfiguration in , receiver channel. 1 The RX local divider (/ 2 ) is a hardware feature on Cyclone IV GX device. It is


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PDF AN-609-2013
MC68HC05

Abstract: MC68HC11 MPC823 MC68302 MC68328 MC68360
Text: debug/monitor port in an application, which allows a serial communication controller (SCCx) to be free for other purposes. The serial management controller clock can be derived from one of the four , COMMUNICATION PROCESSOR MODULE In totally Transparent mode, a serial management controller can use the TDM , generators, or from an external 1× clock. The Transparent protocol allows the transmitter and receiver to , Communication Processor Module SMC Each serial management controller supports the circuit interface and


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PDF 0x3800. 0x0003. 0x3c80. 0x3c00. 0x0005. 0xabcd122b, 0x42xxxxxx. MPC823 MC68HC05 MC68HC11 MC68302 MC68328 MC68360
1998 - 4ppm protocol

Abstract: CRC-16 CRC32 MC68160 MPC823 CRC-CCITT 0xFFFF 0XFFF0000 IrDA Protocol
Text: in detail in Section 16.9.19.5 Receiver Transparency Decoding. When the frame ends, the controller , , and detect errors on the line and in the controller . When the core enables the receiver , the receiver , controller and it is cleared by the controller when the buffer is full. OFFSET + 0 1 2 3 4 , SCC2 ASYNC HDLC controller . 16.9.19.1 FEATURES.The following list summarizes the main features of the , SCC2 ASYNC HDLC CHANNEL FRAME TRANSMISSION PROCESS. The SCC2 ASYNC HDLC controller , is designed to


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PDF MPC823 MPC823 10BASE-T) MPC823, 10BASE-T MC68160 4ppm protocol CRC-16 CRC32 CRC-CCITT 0xFFFF 0XFFF0000 IrDA Protocol
1998 - MC68HC11

Abstract: MPC823 MC68302 MC68328 MC68360 MC68HC05 16-1-151
Text: receiver and puts it in a reset state. 2 . Make modifications to the SMC receive parameters, including the , communication controller to be free for other purposes. The serial management controller clock can be derived , and detection. In totally Transparent mode, the serial management controller can use the TDM channel , from an external 1× clock. The Transparent protocol allows the transmitter and receiver to use the external synchronization pin. Each serial management controller supports the circuit interface and monitor


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PDF MPC823 MC68HC11 MC68302 MC68328 MC68360 MC68HC05 16-1-151
1996 - MPC860

Abstract: No abstract text available
Text: the frame, and detect errors on the line and in the controller . When the core enables the receiver , 16.14.19.5 Receiver Transparency Decoding. When the frame ends, the controller checks the incoming CRC field , as follows: 1. Set the NOF bits as preferred. 2 . Set the CRC to 16-bit CRC CCITT. 3. Set the RTE , zero or to their default condition. 16.14.18.3.3 HDLC Bus Controller Example. Except for the , Controller Asynchronous HDLC is a frame-based protocol that uses HDLC framing techniques in conjunction


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PDF 16-bit MPC860
2000 - VFIR

Abstract: LED IR for Tx, RX VFIR controller sharp infrared protocol ir led rx tx VFIR Transceiver IRM1600 IRC1802 IRMS1600 SIR MB
Text: , receiver sensitivity and power management. IRC 1802 IrDA Communications Controller for SIR, MIR, FIR , Pin Functions PIN # FUNCTION PIN # FUNCTION 1 LED Anode 5 SD/SCLK 2 LED Cathode , SIR Detection Irradiance MIR Detection Irradiance FIR Detection Irradiance VFIR Receiver Rise/Fall Time Receiver Rise/Fall Time 3 7 MIN TYPICAL 3 3 4 5 - V °C MAX UNIT , Supply Current, Shutdown LED Current RECEIVER PARAMETER SYMBOL PARAMETER CONDITIONS 3.6 75


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PDF IRMS1600 16Mb/s IRMS1600 VFIR LED IR for Tx, RX VFIR controller sharp infrared protocol ir led rx tx VFIR Transceiver IRM1600 IRC1802 SIR MB
1996 - MPC821

Abstract: No abstract text available
Text: the controller . When the core enables the receiver , the receiver waits for data to be present on the , . 16.14.19.5 RECEIVER TRANSPARENCY DECODING. The ASYNC HDLC controller maps characters according to RFC 1549 , ASYNC HDLC controller is designed to work with a minimum amount of intervention from the CPU core. It operates in a similar fashion to the HDLC controller on the MPC821. When the core enables the transmitter and sets the ready (R) bit in the first buffer descriptor, the ASYNC HDLC controller fetches the data


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PDF MPC821. MPC821
2004 - Not Available

Abstract: No abstract text available
Text: controller wakes the device. The receiver can be used in a low power Sniff Mode where the AMIS-52100 is , · Wake up on RSSI · Antenna diversity dual receiver · Internal VCO/PLL tuning varactor · Application wakeup interrupt to external controller 3.0 Technical Features · Operating Frequency: · Quick Start , Function: · TX Power (-3 to +12 dBm) · Antenna Impedance Match ( 2 independent channels) · Xtal for , Diagram The AMIS-52100 is a dual channel receiver and a transmitter in a single small outline package


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PDF AMIS-52100 AMIS52000 405MHz
scn68562 Users guide

Abstract: SC68C562 SC68C562A8A SC68C562C1A SC68C562C1N SCN68562 DUSCC Users guide scb68430
Text: indicates to the DMA controller that one or more characters are available in the receiver FIFO (when the , full-duplex DMA operation, this output indicates to the DMA controller that data is available in the receiver , specification CMOS Dual universal serial communications controller crcoo,c(1 (CDUSCC) SC68C562 DESCRIPTION The Philips Semiconductors SC68C562 Dual Universal Serial Communications Controller (CDUSCC) Is a single-chip CMOS-LSI communications device that provides two independent, multi-protocol, full-duplex receiver


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PDF SC68C562 SC68C562 150pF 150pF 100pF bbS3R24 scn68562 Users guide SC68C562A8A SC68C562C1A SC68C562C1N SCN68562 DUSCC Users guide scb68430
1998 - CRC-16

Abstract: DSP56000 MC68681 MC68HC11 MPC823
Text: in synchronous mode. · Idle Sequence Receive Error-When the SCC2 UART controller receiver , PSMR­SCC2 UART register when the SCC2 UART controller is in synchronous mode, the receiver reports all , Error-The SCC2 UART controller provides flexible break support to the receiver . When the first break , receiver is always enabled for one stop bit unless the SCC2 UART controller is in synchronous mode and the , While the SCC2 UART controller is transmitting data, the receiver is disabled. This is useful if the


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PDF 16-bit MPC823 CRC-16 DSP56000 MC68681 MC68HC11
2010 - altgx

Abstract: 485G EP4CGX15 EP4CGX150 EP4CGX22 EP4CGX30 EP4CGX75 F169 F324
Text: Increase or decrease the data rate (/ 2 ) for the receiver channel auto-rate negotiation Channel , the ALTPLL_RECONFIG controller to dynamically reconfigure your receiver channel. Altera , local / 2 divider is bypassed and the receiver data path takes in the data rate as it is. 10. Create , adjusting the transmitter or receiver buffer settings while bringing up a link. Controls and , non-bonded configuration mode to a bonded configuration mode © July 2010 Switch between a Receiver


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PDF AN-609-1 altgx 485G EP4CGX15 EP4CGX150 EP4CGX22 EP4CGX30 EP4CGX75 F169 F324
1999 - Zilog Z16C30

Abstract: 16c3010 Z16C3010VSC transistor mark d13
Text: Selection for Receiver and Transmitter Async Mode with 1 to 8 Bits/Character, 1/16 to 2 Stop Bits/Character , DS007900-SCC0499 ZiLOG Z16C30 CMOS USCTM Universal Serial Controller AS 2 6 1 7 SITACK 16 17 DS , Controller AS 2 98 99 2 98 1 1 99 PITACK ( 2 -Pulse) 96 97 96 97 AD15­AD0 18 19 18 19 WAIT/RDY , Receiver Output 2 INT 3 RxC, TxC Transmit TxREQ 4 TxC as Transmitter Output 5 INT 6 , Controller ZiLOG AC CHARACTERISTICS Z16C30 General Timing No 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18


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PDF Z16C30 0-to-10-mbps 32-Byte 110-ns 16-Bit 1/16-Bit 1553B DS007900-SCC0499 Zilog Z16C30 16c3010 Z16C3010VSC transistor mark d13
1996 - hdlc

Abstract: 806C MC68360
Text: 1 ASYNC HDLC Controller Overview 4 2 ASYNC HDLC Controller Key Features 2.1 ASYNC HDLC , Transmitter Transparency Encoding 2.4 Receiver Transparency Decoding 2.4.1 Receive Flowchart 2.4.2 Cases , Descriptor 18 2 Asynchronous HDLC 9 Differences Between HDLC and ASYNC-HDLC 9.1 Max Received , .1 Initialization Procedure for QUICC Version $0001 A. 2 Initialization Procedure for QUICC Revision $0002 A , Appendix C - References 24 3 Asynchronous HDLC 1 ASYNC HDLC Controller Overview Asynchronous


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PDF MC68360 hdlc 806C
2005 - Not Available

Abstract: No abstract text available
Text: overruns because the DMA controller did not service a request, an interrupt is queued. When a receiver is , the receiver , it is maintained through the DMA controller into memory. Interrupts There are two , ML145488 Dual Data Link Controller Legacy Device: Motorola MC145488 This technical summary gives a brief overview of the ML145488 Dual Data Link Controller . The ML145488 is a two­channel ISDN LAPD controller with an on­chip direct memory access (DMA) controller . It is intended for ISDN terminal


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PDF ML145488 MC145488 ML145488 MC145474
2006 - SC26C562C1A

Abstract: PLCC52 SC26C562 SC68C562 SCN26562
Text: for the receiver without receipt of a SYN character. This mode can be used in disc or tape controller , controller that data is available in the receiver FIFO. In non-DMA mode, this pin is a general purpose , CDUSCC that the DMA controller has acquired the bus and that the requested bus cycle (read receiver FIFO , controller has acquired the bus and that the requested read receiver FIFO bus cycle is beginning. Because , INTEGRATED CIRCUITS SC26C562 CMOS dual universal serial communications controller (CDUSCC


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PDF SC26C562 SC26C562 SC26C562C1A PLCC52 SC68C562 SCN26562
B300

Abstract: B500 MC145474 MC145488 ML145488-4P
Text: DMA controller into memory. Interrupts There are two interrupts generated by the receiver . The , , one for each transmitter and receiver . DMA Operation When the DMA controller detects a service , Interrupt is queued, but the receiver continues to receive and the DMA controller places the data in the , B500 BUFFER 2 BUFFER 4 RECEIVER BUFFER A START ADDR­AB00 HEX BUFFER A LENGTH­200 HEX , ML145488 Dual Data Link Controller Legacy Device: Motorola MC145488 This technical summary


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PDF ML145488 MC145488 ML145488 MC145474 B300 B500 MC145474 MC145488 ML145488-4P
2010 - V-by-One

Abstract: remote control transmitter and receiver circuit EP4CGX75 cyclone iv gxb tx_coreclk block diagram PCIe basic television block diagram EP4CGX150 EP4CGX30 EP4CGX50 Altera Cyclone IV
Text: , Volume 2 1­14 Chapter 1: Cyclone IV Transceivers Architecture Receiver Channel Datapath , Architecture Receiver Channel Datapath 1 You can implement a bit-slip controller in the user logic that , data is deserialized at the receiver . Cyclone IV Device Handbook, Volume 2 © July 2010 Altera , combination of MPLL_1 driving receiver channels 0, 1, and 3, while MPLL_ 2 driving receiver channel 2 is not , with channel 0 and channel 1 in a transceiver block Transmitter and Receiver Bonded (× 2


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PDF
1995 - MC145488FN

Abstract: MC145488 B300 B500 MC145474
Text: in the section describing the DMA controller . Packet Operation The receiver is reset and idle , controller are reset and the aborted frame is ignored. The FIFO is cleared and the receiver begins searching , alignment is obtained in the receiver , it is maintained through the DMA controller into memory , it changes state. DMA CONTROLLER Address Recognition (Filtering) The receiver can filter , transmitter and receiver . DMA Operation When the DMA controller detects a service request from one of the


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PDF MC145488 MC145488 MC145474 MC145488FN B300 B500
SC26C562

Abstract: SC68C562 SCN26562 0416C GP-12B
Text: ), The receiver BRG clock (16X), or the internal system clock (X1 * 2 ). SC26C562 April 7, 1993 5 NAPC , controller that data is available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output , controller has acquired the bus and that the requested bus cycle (read receiver FIFO when the receiver is , . Receiver FIFO empty. N-®— Figure 2 . Read Cycto12 SYMBOL PARAMETER LIMITS UNIT AUTOMOTIVE , Communications Products Product specification CMOS dual universal serial communications controller (CDUSCC


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PDF SC26C562 SC26C562 SC68C562 SCN26562 0416C GP-12B
2004 - automatic change over switch circuit diagram

Abstract: am transmitter and receiver circuit diagram power line carrier communication diagram remote control receiver and transmitter remote control transmitter and receiver circuit 8086 timing diagram block diagram for automatic room power control interfacing of memory devices with 8086 8086 interrupt vector table FM TRANSMITTER CIRCUIT DIAGRAM
Text: 2 Philips Semiconductors Product data CMOS dual universal serial communications controller , for the receiver without receipt of a SYN character. This mode can be used in disc or tape controller , controller that data is available in the receiver FIFO. In non-DMA mode, this pin is a general purpose , CDUSCC that the DMA controller has acquired the bus and that the requested bus cycle (read receiver FIFO , controller has acquired the bus and that the requested read receiver FIFO bus cycle is beginning. Because


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PDF SC26C562 SC26C562 automatic change over switch circuit diagram am transmitter and receiver circuit diagram power line carrier communication diagram remote control receiver and transmitter remote control transmitter and receiver circuit 8086 timing diagram block diagram for automatic room power control interfacing of memory devices with 8086 8086 interrupt vector table FM TRANSMITTER CIRCUIT DIAGRAM
1995 - MC145488

Abstract: No abstract text available
Text: discussed in the section describing the DMA controller . Packet Operation The receiver is reset and idle , controller are reset and the aborted frame is ignored. The FIFO is cleared and the receiver begins searching , alignment is obtained in the receiver , it is maintained through the DMA controller into memory , it changes state. DMA CONTROLLER Address Recognition (Filtering) The receiver can filter , transmitter and receiver . DMA Operation When the DMA controller detects a service request from one of the


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PDF MC145488 MC145488 MC145474
Supplyframe Tracking Pixel