The Datasheet Archive

Top Results (3)

Part Manufacturer Description Datasheet Download Buy Part
61646TU Integrated Device Technology Inc WAFER-0, Wafer
SN761647DBTR Texas Instruments Digital TV Tuner IC SN761647 38-TSSOP -40 to 85
SN761643DGKR Texas Instruments AGC Amplifier 8-VSSOP -20 to 85

ram 6164 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
6164 ram memory

Abstract: intel 6164 ram internal diagram of 7473 pin configuration of intel 80386 Unicorn Microelectronics UM82C384 T-50 PA13 6164 memory PA11
Text: base memory is 128KB video RAM , 64KB LIM pages and 128KB system BIOS. The extended memory can be 1M, 2M , Bank 1 OFFFFF 0E0000 09FFFF 000000 RAM Diagnostic & Relocation Register Not Used Relocated BIOS Not Used 2M-3M 1M-2M System BIOS 128KB Video RAM & 64KB LiM Pages DOS Base Memory 384K 1M 1M , regions marked "not used" and video ram and lim pages. 6-158 | 5 This Material Copyrighted By Its , 100000 OFFFFF 0E0000 09FFFF 000000 RAM Diagnostic & Relocation Register Not Used Relocated BIOS Not


OCR Scan
PDF TE707Ã UM82C384 16MHz, 20MHz 25MHz 120ns T-5S-33 6164 ram memory intel 6164 ram internal diagram of 7473 pin configuration of intel 80386 Unicorn Microelectronics T-50 PA13 6164 memory PA11
1995 - 74LS471

Abstract: ram 6164 6164 ram 6164 ram memory sram 6164 datasheet sram 6164 6164 memory cd 74373 6164 sram PAL16L8B
Text: PAL16L8B 74373 74521 74533 74373 74651 1 3 2 1 3 1 4 Memory Static Buffer Ram 256 x 8 ROM 6164 74LS471 2 1 2 Other Qty 3 MacIntosh II Ethernet Adapter Card TL F


Original
PDF
2007 - epd driver ic

Abstract: epd driver capacitor 30 pf ram 6164 Epson EPD controller S1C63808 k1158 OSC4 S1C63000 Piezo Ceramic generator pieZo 31
Text: 8K-word ROM, 2K-word RAM EPD Driver IC Power Supply Circuit Multiply-Divide Circuit Low Current , high-performance 4-bit CPU S1C63000 as the core CPU, ROM (8,192 words × 13 bits), RAM (2,048 words × 4 bits , 122 sec 1.0 sec 183 sec 1.5 sec RAM capacity , OSC2 OSC3 OSC4 Interrupt Generator OSC Clock Timer RAM 2,048 words × 4 bits VDD VD1 , (selected by software) Output port pins R10­R13 57­60 O P00­P03 61­64 I/O I/O port


Original
PDF S1C63808 S1C63000 S1C63808 S1C63000 epd driver ic epd driver capacitor 30 pf ram 6164 Epson EPD controller k1158 OSC4 Piezo Ceramic generator pieZo 31
Not Available

Abstract: No abstract text available
Text: -64A) Features • 8192 word x 10 bit ROM Pin Arrangement • 512 digit x 4 bit RAM • 48 I/O pins and 4 , pull-down MOS. ROO-R73 1-20, 47-54, 61-64 I/O Input/output ports accessed with 4


OCR Scan
PDF HD404678 HMCS400-series HD404678 FP-64A) FP-64A
2000 - ram 6164

Abstract: 6164 ram NJU3430 NJU3430FG1 QFP64 cg00
Text: NJU3430 NJU3430 16 1 ROM/RAMRAM RAM ROM/ RAM RAM RAM CPU 1MHz CPU RAM RAM NJU3430FG1 +1 +1 ROM 8,400 5 × 7 240 8,4005 7 , RAM 35 × 8 , RAM 8 16 16 35 NJU3430 NJU3430 16 1 3 2 1LED 1 LED 16 1 RAM RAM 16 × 8 16 1 ROM 8,400 5 × 7240 5 RAM 35 × 8 5 × 78 5 RAM 16 × 2 32 =45V) ( V DD -V FDP =45V) ( 16


Original
PDF NJU3430 NJU3430FG1 QFP64 NJU343 100pF ram 6164 6164 ram NJU3430 NJU3430FG1 QFP64 cg00
2000 - ram 6164

Abstract: 6164 ram NJU3430 NJU3430FG1 QFP64 D5101LC-1 RAM
Text: NJU3430 NJU3430 16 1 ROM/RAMRAM ROM/ RAM RAM RAM RAM CPU 1MHz CPU RAM RAM NJU3430FG1 +1 +1 ROM 8,400 5 × 7 240 8,4005 7 , RAM 35 × 8 , RAM 8 16 16 35 NJU3430 NJU3430 16 1 3 2 1LED 1 LED 16 1 RAM RAM 16 × 8 16 1 ROM 8,400 5 × 7240 5 RAM 35 × 8 5 × 78 5 RAM 16 × 2 32 ( V DD -V FDP =45V) ( =45V) 16


Original
PDF NJU3430 NJU3430FG1 QFP64 100pF ram 6164 6164 ram NJU3430 NJU3430FG1 QFP64 D5101LC-1 RAM
GPLB32A

Abstract: R32768 GPLB32A3 sram 6164 SEG73-0 GPLB32 C000-C7FF 6164 ram 6164 sram GPLB
Text: . 9 6.16.4 . Low voltage reset , :0], PD[5:0]) bytes working RAM , 512K bytes ROM, 8 I/Os, interrupt/wakeup . Dedicated I/Os: PA , 8 64 segments, 32 commons, maximum 2048 dots 6 8-bit 1216 bytes RAM 1/5, 1/6 bias; 1 , dedicated LCD RAM Built-in voltage regulator to generate VLCD for LCD driver (I/O) PA[7:0] PB[5:0] PC[7:0] PD[5:0] LCD RAM 296 bytes 32 Com m ons X 74 Segm ents LCD Driver 32-level contrast


Original
PDF GPLB32A3 512KB GPLB32A R32768 GPLB32A3 sram 6164 SEG73-0 GPLB32 C000-C7FF 6164 ram 6164 sram GPLB
2003 - AN55

Abstract: AN58 Si322x fsync in PCM si-3200 an5504 Si3220/Si3225 Si3225
Text: performance. Pins 1, 3, 4, 8, 9, 13, 14, 16­20, and 61­64 are sensitive current input pins that are , Registers and RAM Si3220/Si3225 Clock Requirements The Si3220/Si3225 programmable function is powered by , -bit RAM locations of the Si3220/Si3225 will initialize to 0x0000 following a reset. The RAM must be initialized with functional values to prepare the Si3220/Si3225 for operation. Refer to the RAM listing in AN58 for example RAM location values. Refer to the data sheet or ProSLIC LINC software for calculation


Original
PDF Si3220/Si3225 Si3220 Si3225 Si3200 AN55 AN58 Si322x fsync in PCM si-3200 an5504 Si3225
404678H

Abstract: No abstract text available
Text: -digit x 4-bit RAM · 48 I/O pins and four dedicated input pins - 16 large-current output pins: Ten 15 , , 61-64 I/O R8 0 - R 8 3 42-45 I Interrupt INT0, INT t in t2 > in t3 SCKA, SC KB SIA , 512 · 4-bit RAM Stack pointer Instruction decoder -N ÏL ZZ <> zz X (4) W (2


OCR Scan
PDF HD404678 CS400 mass/R83 N/R82 OD2/R73 OB/R70 03Ul4 03l\3- 404678H
2008 - p4 power supply

Abstract: BU9794KV BU9799KV bu9794
Text: which is suitable for multi function display and is integrated display RAM and power supply circuit for , ) Driver Feature (BU9794KV) 1) 3wire serial interface (CSB, SD, SCL) 2) Integrated RAM for display , 2 1 11-60 61-64 I I I SD SCL CSB VSS VDD VLCD SEG0-49 COM0-3 O O Function , transfer method. C 0 Next byte is RAM write data. 1 Next byte is command. Mode Set (MODE SET) MSB D7 , Transfer format Write display data and transfer method This device has Display Data RAM (DDRAM) of


Original
PDF BU9794KV, BU9799KV BU9794KV BU9799KV. 200Segment 50SEG BU9794KV p4 power supply BU9799KV bu9794
2009 - Not Available

Abstract: No abstract text available
Text: which is suitable for multi function display and is integrated display RAM and power supply circuit for , Feature (BU9794KV) 1) 3wire serial interface (CSB, SD, SCL) 2) Integrated RAM for display data (DDRAM) 50 , 6 5 3 2 1 11-60 61-64 I I I I I I I Function Input terminal for turn off display H: turn on , data judgment. Refer to Command and data transfer method. C 0 Next byte is RAM write data. 1 Next byte , method This device has Display Data RAM (DDRAM) of 50×4=200bit. The relationship between data input


Original
PDF BU9794KV, BU9799KV BU9794KV BU9799KV. 200Segment 50SEG BU9794KV
GPLB32A

Abstract: GPLB31A GPLB301 6164 ram memory 2368D C000-C7FF generalplus GPLB33B GPLB301A GPLB30A
Text: ] . 15 6.16.4 . PC[4:7]/SEG[73:70]/COM[25:22 , bytes working RAM , 512K bytes OTP memory, 30 I/Os, GPLB37. interrupt/wakeup controller, UART for , series via options. Body selected ALL GPLB30A RAM Size 4288 Bytes OTP Size 512K Bytes , ,1/16 1/16, 1/32 1/16 LCD RAM 296 Bytes 148 Bytes 296 Bytes 104 Bytes 96*8 , /F 8-bit 8 BEX/PB7-0 MC10/PC1-0 2 micro-processor 4288 bytes RAM 8 Max.30 I


Original
PDF GPLB301A 512KB LB31A GPLB32A GPLB31A GPLB301 6164 ram memory 2368D C000-C7FF generalplus GPLB33B GPLB301A GPLB30A
1996 - E2PROM

Abstract: ASM51
Text: addressable RAM byte 2. FUNCTION DESCRIPTIONS The functions that use write and/or erase actions are , (TI) and rcv-interrupt flag (RI). January 1992 6-164 Philips Semiconductors Application , write a block of data from internal RAM to E2PROM. Byte transfer is done on interrupt basis. The status , ; source byte in RAM is not 0x00 Tprog = A.tW+B.(tE+tW) B: Byte in E2PROM is not 0x00; source byte in RAM <> E2PROM byte If a ROW-erase is done, programming the ROW will take: C: Source byte in RAM <> `0' Tprog


Original
PDF 8xC851 EIE/AN91009 PL/M-51 ASM51 OM4142) PL/M51: PL/M51 OM4144) OM4136) E2PROM
2001 - VDR 20-100

Abstract: MWS5114E3 MWS5114E2X MWS5114E2 MWS5114E1 MWS5114D3X MWS5114D3 MWS5114D2 MWS5114D1 MWS5114
Text: MWS5114 TM 1024-Word x 4-Bit LSI Static RAM March 1997 Features as 2V Min · Fully Static Operation · All Inputs and Outputs Directly TTL Compatible · Industry Standard 1024 x 4 Pinout (Same as Pinouts for 6514, 2114, 9114, and 4045 Types) · Three-State Outputs · Low Standby and Operating Power · Common Data Input and Output Description · Memory Retention for , . Typical values are for TA = 25oC and nominal V DD. 6-164 MWS5114 tRC tAA ADDRESS CS tCO


Original
PDF MWS5114 1024-Word 200ns 250ns 300ns MWS5114E3 MWS5114E2 MWS5114E2X MWS5114E1 MWS5114D3 VDR 20-100 MWS5114E3 MWS5114E2X MWS5114E2 MWS5114E1 MWS5114D3X MWS5114D3 MWS5114D2 MWS5114D1 MWS5114
1999 - 2114 Ram pinout 18

Abstract: 9114 RAM 2114 static ram 2114 static ram ic ic 2114 MWS5114E3 9114 static ram MWS5114-3 STATIC RAM 2114 memory ic 2114
Text: MWS5114 1024-Word x 4-Bit LSI Static RAM March 1997 Features Description · Fully Static Operation The MWS5114 is a 1024 word by 4-bit static random access memory that uses the ion-implanted silicon gate complementary MOS (CMOS) technology. It is designed for use in memory systems where low power and simplicity in use are desirable. This type has common data input and data output and , 25oC and nominal VDD. 6-164 MWS5114 tRC tAA ADDRESS CS tCO tOTD tCX DOUT


Original
PDF MWS5114 1024-Word MWS5114 2114 Ram pinout 18 9114 RAM 2114 static ram 2114 static ram ic ic 2114 MWS5114E3 9114 static ram MWS5114-3 STATIC RAM 2114 memory ic 2114
2N6161

Abstract: 2N6165 2N6157 2N6162 2n6160 2N6163 2N6164
Text: 6157, 2N 6160, 2N 6163 2N 6158, 2N 6161, 2N 6164 2N 6159, 2N 6162, 2N 6165 · P e a k G a te V o lta g e , inal 1. F IG U R E 1 - RM S C U R R E N T D E R A T IN G Symbol ·DRM. ' RAM Min - Typ 1.5


OCR Scan
PDF 2N6145-47 2N5S71) 2N6157 2N6165 2N6161 2N6165 2N6162 2n6160 2N6163 2N6164
6164 ram memory

Abstract: 6164 ram mcm6164cc70 mcm6164
Text: °C, Unless Otherwise Noted) R E C O M M E N D E D OPER A TIN G C O N D IT IO N S P a ram eter Supply , DATA MCM6164C W R IT E CYCLE 1 (W C O N TR O LLED) I See Note 1) P a ram eter W rite Cycle Time , ORDERING INFORMATION (Order by Full Part Number) MCM 6164 C C 55 I - Speed Indicator - Package -


OCR Scan
PDF MCM6164C MCM6164C Number--MCM6164CC55 MCM6164CC70 6164 ram memory 6164 ram mcm6164cc70 mcm6164
2001 - 4 mhz crystal oscillator

Abstract: F8235 S3F8235
Text: RAM A/D Converter · · Eight analog input channels 20us conversion speed at 10MHz fADC clock , .0-P4.3 VLC1-VLC4 COM0-COM7 SEG0-SEG11 SEG12-SEG23 KIN0-KIN3 CA CB VLC1-VLC4 LCD Driver 16-Kbyte ROM 512-Byte RAM , -14 ­ ­ ­ Circuit Type H-14 Pin No. 61-64 Shared Functions SEG20-SEG23 KSTR9-KSTR 12 AD0-AD7 AVREF , 33-36 41-52 53-60 61-64 1-4 15 7 9 8 7-10 23 24 25 26 33-36 61-64 20 16 17 P1.0-P1.7 ­ P1.4-P1.7 ­


Original
PDF S3C8238/C8235/F8235 S3C8216/fx S3F8235 4 mhz crystal oscillator F8235
2006 - Not Available

Abstract: No abstract text available
Text: . 7 6.1 6.2 RAM , . 19 Publication Release Date: May 3, 2006 Revision A6 -1- W78E858 6.16.1 6.16.2 6.16.3 6.16.4 , the loader program located at the 4KB auxiliary Flash EPROM ROM; 768 bytes of on-chip RAM ; 128 bytes , of on-chip RAM 128 bytes on-chip EEPROM memory 64K bytes program memory address space and 64K bytes , 3, 2006 Revision A6 W78E858 5. BLOCK DIAGRAM RAM 256 Bytes SFR Auxiliary RAM 512 RAM Bytes


Original
PDF W78E858
2005 - 80C51

Abstract: 80C52 F04KBOOT W78E858 ra80xx P17937
Text: . 6 6.1 RAM , ).19 6.16.4 IRQ1 (C0H , the loader program located at the 4KB auxiliary Flash EPROM ROM; 768 bytes of on-chip RAM ; 128 bytes , Program (LDROM) · Low standby current at full supply voltage · 256 + 512 bytes of on-chip RAM , Revision A5 W78E858 5. BLOCK DIAGRAM RAM 256 Bytes PORT0 SFR Auxiliary RAM 512 RAM Bytes


Original
PDF W78E858 80C51 80C52 F04KBOOT ra80xx P17937
2004 - 80C51

Abstract: 80C52 F04KBOOT W78E858
Text: . 6 6.1 RAM , ).19 6.16.4 IRQ1 (C0H , the loader program located at the 4KB auxiliary Flash EPROM ROM; 768 bytes of on-chip RAM ; 128 bytes , Program (LDROM) · Low standby current at full supply voltage · 256 + 512 bytes of on-chip RAM , Revision A4 W78E858 5. BLOCK DIAGRAM RAM 256 Bytes PORT0 SFR Auxiliary RAM 512 RAM Bytes


Original
PDF W78E858 80C51 80C52 F04KBOOT
Not Available

Abstract: No abstract text available
Text: Paradigm PDM44538 32K x 18 Fast CMOS Synchronous Static RAM with Linear Burst Counter , counter to drive the two least-significant bits of the internal RAM address. The burst counter is loaded , next available RAM address. The next word in the burst is written by taking ADV low and presenting the , write data, which is sampled by the same clock, is written into the internal RAM during the time , S ta n d a rd P o w e r | P D M 4 4 5 3 8 - ( 3 2 K x 1 8 ) S y n c . S ta tic R A M 6-164


OCR Scan
PDF PDM44538 680x0 PDM44538
2010 - bu9796

Abstract: bu9795afv BU9796FS BU9799 BU9794 BU9794KV BU9799KV BU9795A circuit BU9795AKV BU9795A
Text: ) 3wire serial interface (BU9794KV, BU9795AKV/FV/GUW) 3) Integrated RAM for display data (DDRAM) 4 , to VSS "L" active SEG0-49 11-60 O SEGMENT output for LCD driving COM0-3 61-64 , ) Must be connect to VSS SEG0-49 11-60 O SEGMENT output for LCD driving COM0-3 61-64


Original
PDF BU9796FS BU9795AKV BU9795AFV BU9795AGUW BU9794KV BU9799KV 10044EAT05 BU9796FS, BU9799KV) BU9794KV, bu9796 BU9799 BU9794 BU9799KV BU9795A circuit BU9795A
SPLB30A

Abstract: SPR3206A SPBA01 SPR1024
Text: working RAM , 96K bytes ROM, 7 I/Os, interrupt/wakeup 2752 bytes SRAM controller, UART for serial , Detect dots AUDB 148 bytes dedicated LCD RAM Tx/PC2 Built-in voltage regulator to , 5.75V, in 1/5 bias) ! Power saving SLEEP mode BUS Mem I/F 8-bit micro-processor 2752 bytes RAM 8 AD[7:0]/PB[7:0] MC[1:0]/PC[1:0] 2 Voltage Regulator 8 Max.29 I/O Ports LCD RAM , , SPRS512C or memory, either RAM or ROM, can be extended up to 4MB. Serial SPRS1024C. 6.2. Map of


Original
PDF SPLB30A SPLB30A SPRS512A" SRS512C" SPRS1024A" SPRS1024C" SPR3206A SPBA01 SPR1024
Not Available

Abstract: No abstract text available
Text: H A R R M3DS271 GÜBTIS? 2 4bE ì> HARRIS SEMICOND SECTOR I S HAS H M - 6 5 1 6 2 / 8 8 3 SEMICONDUCTOR 2K x 8 Asynchronous CMOS Static RAM January 1992 Features , , the output will remain in .a high impedance state. G is held continuously low. 6-164 M302271 , deselected state to keep the RAM outputs high impedance, minimizing power dissipation. 3. Inputs which , down transitions. 4. The RAM can begin operation > 55ns after VCC reaches the min­ imum operating


OCR Scan
PDF M3DS271 Mil-Std-883 HM-65162/883 43D2271 HM-65162/883 T-46-23-12 MIL-STD-1835, GDIP1-T24 MIL-M38510
Supplyframe Tracking Pixel