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Part Manufacturer Description Datasheet Download Buy Part
CD4059AMG4 Texas Instruments CMOS Programmable Divide-by-N Counter 24-SOIC -55 to 125
CD4059AD3 Texas Instruments CMOS Programmable Divide-by-N Counter 24-CDIP SB -55 to 125
CD4059AM Texas Instruments CMOS Programmable Divide-by-N Counter 24-SOIC -55 to 125
CD40161BNSR Texas Instruments CMOS Synchronous Programmable 4-Bit Binary Counter with Asynchronous Clear 16-SO -55 to 125
CD4059AE Texas Instruments CMOS Programmable Divide-by-N Counter 24-PDIP -55 to 125
CD4059AEE4 Texas Instruments CMOS Programmable Divide-by-N Counter 24-PDIP -55 to 125

programmable counter Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1999 - 20PIN

Abstract: CXA1787N HIGH FREQUENCY COUNTER
Text: Counter 7bits NC FIN FC LAT DATA PS 11 CK Programmable Counter 11bits 9 , Reference Programmable Counter 14bits P 16 4 NC 17 3 Vp 19 Phase Comparator , -bit Latch 18-bit Shift Resister 1-bit Shift Resister 18-bit Latch Pulse swallow programmable counter , comparator output and the output signals of counter (reference, programmable ) output to the TEST pin , reference counter latch and the 18 bis of data to the pulse swallow programmable counter latch to set the


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PDF CXA1787N CXA1787N 20-pin 20PIN SSOP-20P-L01 SSOP020-P-0044 42/COPPER HIGH FREQUENCY COUNTER
TC9198F

Abstract: TC9198P 21D17 D1116
Text: PROGRAMMABLE COUNTER TC9198P, TC9198F are high speed programmable counters developed for dividing PLL circuits , counter 7bit (A) 11 bit (N) SWALLOW COUNTER PROGRAMMABLE COUNTER I I (swallow counter /simple counter , Supply Terminal 2 p|N Programmable Counter Input Programmable counter input terminal. Prescaler output , division of programmable counter . (1) MODE (22PIN) = at "L" level • Dg-Dg-^Swallow counter : A • D7~Di7-> Programmable counter : N (2) MODE = at "H" and D17 = at "L" level • Simple counter operation in setting


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PDF TC9198P/F TC9198P, TC9198F TC9198F 15MHz N-10Vp DIP24-P-300-2 93TVP TC9198P 21D17 D1116
Programmable Divider

Abstract: TC9223F TC9223P Q9-Q10
Text: . Pull-down resistor built in 6 P|N Programmable counter input Programmable counter input terminal. Input an , Programmable counter frequency division ratio • Group 3 —I— PSC control '— Phase comparator S, R , frequency division ratio intended. N^ 16,383 3. Programmable counter Programmable counter circuit adopts swallow system to generate high frequency and is composed of 7 bits swallow counter , 11 bits programmable , programmable counter is composed of 20bits but changes according to "P" of external prescaler. (1) When used


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PDF TC9223P/F TC9223P, TC9223F TC9223F 14bit 10MHz DIP16-P-300-2 735TYP Programmable Divider TC9223P Q9-Q10
Not Available

Abstract: No abstract text available
Text: Programmable counter input Prescaler control FUNCTION AND OPERATION Logic ground terminal. Reference frequency , . Used normally at "L " level or Open state. Test mode operation at "H " level. Programmable counter , frequency division ratio Programmable counter frequency division ratio PSC control Phase comparator S, R , binary code N of frequency division ratio intended. 5< N £ 16,383 3. Programmable counter Programmable counter circuit adopts swallow system to generate high frequency and is composed of 7 bits swallow


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PDF TC9223P, TC9223F TC9223F 14bit TC9223P- DIP16-P-300A
2007 - Not Available

Abstract: No abstract text available
Text: programmable counter , dual parallel output phase comparator, crystal oscillator and reference counter , and AM band local oscillator Programmable counter signals by capacitor coupling. FMIN and AMIN , Programmable counter data FM MODE OSC1 OSC2 Crystal oscillator selection bits Programmable counter , programmable 1” counter stops, and FM, AM and IFIN(when selected IFIN) are set to “ amp off”state , : www.silan.com.cn REV:1.1 2002.08.14 Page 8 of 22 SC9256 Programmable counter The programmable counter


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PDF SC9256 SC9256 DIP-16-300-2 OP-16-300-1 40MHz
mb15b13

Abstract: CNT12
Text: = 8 to 16383 Serial input 18-bit programmable divider consisting of: - Binary 7-bit swallow counter 0 to 127 - Binary 11-bit programmable counter 16 to 2047 Tx and Rx programmable counters can be , -bit programmable counter (16 to 2047) Preset divide ratio of binary 7-bit swallow counter (Os A < 127) fosc: Reference oscillation frequency R: Preset divide ratio ol binary 14-bit programmable reference counter (8 to , data CNT1 L L H CNT2 L H H Reference counter Programmable counter of PLLt Programmable counter of PLL2


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PDF MB15B13 MB15B13 1000pF 1000pF FPT-20P-M03 20-LEAD CNT12
TC9418FN

Abstract: No abstract text available
Text: a 17bit programmable counter , two parallel output phase comparators, a 75kHz crystal oscillator, a , START (JO (J1 WO Wl -1 -2 -3 -4 Set divide number. programmable counter -»Refer to 2.(1). Unlock , > Höh Cx X'tal = 75kHz C|_ = 15pF Typ., Cx = 0.47//F Typ. 2. Programmable counter The programmable counter block consists of a 1/2 prescaler, 2-modulus prescaler, and 4bit+13bit programmable binary counters. (1) Setting up the programmable counter block Use 17bits for the divide number and two bits for


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PDF TC9418FN TC9418FN 230MHz 130MHz 20MHz 10MHz 17bit
1999 - 20PIN

Abstract: CXA1787N
Text: FIN FC LAT DATA PS 11 CK Programmable Counter 11bits 9 10 15 12 7 Charge Pump 2 Charge Pump 1 DO2 13 6 TEST 14 5 Reference Programmable Counter , Resister 1-bit Shift Resister 18-bit Latch Pulse swallow programmable counter Sony reserves the , counter (reference, programmable ) output to the TEST pin. The signal output which is , reference counter latch and the 18 bis of data to the pulse swallow programmable counter latch to set the


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PDF CXA1787N CXA1787N 20-pin 20PIN SSOP-20P-L01 SSOP020-P-0044 42/COPPER
free circuit diagram for voltage controlled oscillator

Abstract: 4 digit counter circuit diagram max plus ECL Decade Counter 8X08-F decade radio frequency divider phase detector 10khz transistor 112 ac phase ac 400 v detector ecl prescaler phase detector and up down counter
Text: divide the local oscillator frequency down to a frequency compatible with the programmable counter , oscillator frequency (Fout) is changed by programming a different number into the programmable counter . The , blocks. Programmable Counter The programmable counter consists of 3 stages of decade counter plus a , signals; one strobe for each digit. A 4- 5 80MHz ECL prescaler precedes the programmable counter for FM , ) function to scale the programmable counter input frequency down to 16MHz maximum. A logic control Circuit


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PDF 8X08-F 80MHz 600mW free circuit diagram for voltage controlled oscillator 4 digit counter circuit diagram max plus ECL Decade Counter decade radio frequency divider phase detector 10khz transistor 112 ac phase ac 400 v detector ecl prescaler phase detector and up down counter
a35c

Abstract: programmable counter ic
Text: should be Input to the reference counter latch and the 18 bis of data to the pulse swallow programmable , . The input data Is retrieved Into the reference counter latch or the pulse swallow programmable counter , time, set the final bit C High. Next, Input the 19 bits of pulse swallow programmable counter data In , . Hereafter, when only the programmable counter data Is to be changed, only the latter 19 bits of programmable , control data consists of 16 bits for the reference counter and 19 bits for the pulse swallow programmable


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PDF CXA1786N CXA1786N 20-pln 20PIN SSOP-20P-L01 P020-P-0044 a35c programmable counter ic
Not Available

Abstract: No abstract text available
Text: comparator output and the output signals of counter (reference, programmable ) output to the TEST pin , be input to the reference counter latch and the 18 bis of data to the pulse swallow programmable , . The input data is retrieved into the reference counter latch or the pulse swallow programmable , been set. Hereafter, when only the programmable counter data is to be changed, only the latter 19 bits of programmable counter data should be changed. (In this case, set the bit C Low.) (2) Control data


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PDF CXA1786N CXA1786N 20-pin 20PIN P-20P-L01 020-P
HIGH FREQUENCY COUNTER

Abstract: No abstract text available
Text: comparator output and the output signals of counter (reference, programmable ) output to the TEST pin , should be input to the reference counter latch and the 18 bis of data to the pulse swallow programmable , . The input data is retrieved into the reference counter latch or the pulse swallow programmable , been set. Hereafter, when only the programmable counter data is to be changed, only the latter 19 bits of programmable counter data should be changed. (In this case, set the bit C Low.) (2) Control data


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PDF CXA1786N CXA1786N 20-pin 20PIN SSOP-20P-L01 SSOP020-P-0044 HIGH FREQUENCY COUNTER
Not Available

Abstract: No abstract text available
Text: -bit swallow counter and binary 11-bit programmable counter ), analog switches, and intermittent operation , : Binary 7-bit swallow counter : 0 to 127 Binary 11-bit programmable counter : 16 to 2,047 • Serial input, 15-bit programmable reference divider consisting of binary 14-bit programmable reference counter , ­ acteristics changing cir­ cuit Programmable reference divider Binary 14-bit reference counter Vcc , pin (test pin) of f R or fP 16 BiSW o 17 fP 0 Programmable counter output monitor


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PDF MB1513 MB1513 16-bit 15-bit 14-bit 19-bit 18-bit 20-LEAD
2000 - Not Available

Abstract: No abstract text available
Text: bit programmable divider consisting of Binary 7 bit swallow counter : 0 to 127 Binary 11 bit programmable counter : 3 to 2,047 -On-chip high performance charge pump circuit and phase comparator achieved , -bit latch Binary 11-bit Binary 7-bit swallow counter Programmable counter (RF2-PLL) (RF2-PLL) SWRF2 , Programmable ref. RF2 counter (RF2-PLL) LDRF2 OSCout 9 OSCin 8 Selector FC CMC RF1 OR , -bit Programmable ref. counter (RF1-PLL) frRF1 7-bit latch Binary 11-bit fpRF1 Programmable counter


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PDF MB15U36 MB15U36 20pins, FPT-20P-M03) MB15U36PFV 20pin
Not Available

Abstract: No abstract text available
Text: frequency synthesizer. TJTTTTtn 1 Included high speed programmable counter , 2 2.8 MAX operated , PROGRAMMABLE COUNTER Max. Operating Frequency Min. Operating Input Voltage ^IN(MIN) MHz REFERENCE , VCO oscillation frequency due to high speed programmable counter , not necessary mixing down. The , SINGLE X-TAL METHOD - Fig. 2 TC9106BP DIRECT Programmable counter has frequency devide shift , . PROGRAMMABLE COUNTER “ ^ ^ (13 BIT PROGRAMMABLE COUNTER ) • Programmable counter Is a 13 bit


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PDF TC9106BP TC9106BP
programmable counter ic

Abstract: tc9198
Text: , TC9198F SILICON MONOLITHIC TECHNICAL PROGRAMMABLE COUNTER TC9198P, TC9198F are high speed , BLOCK DIAGRAM Y :Q> PSC CONTROL CIRCUIT 5bit (N'J PROGRAMMABLE COUNTER "^POUT 7bit (A) SWALLOW COUNTER 1 1 bit (N) PROGRAMMABLE COUNTER -@ M O D E (SWALLOW COUNTER /SIMPLE COUNTER , FUNCTION PIN SYM BOL No. 1 PIN NAME Ground Terminal Power Supply Terminal Programmable Counter Input , in PSC 24 2 3 Programmable counter input terminal. Amp. Circuit Prescaler output is input


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PDF TC9198P, TC9198F TC9198F TC9198P- DIP24-P-300 93TYP programmable counter ic tc9198
7-segment 4 digit 5461

Abstract: TLR-321 TLR321 cd 5411 ic tc9109 TC9109BP
Text: frequency synthesizer. - · Included high speed programmable counter , operated direct division of VCO can , VCO oscillation frequency due to high speed programmable counter , not necessary mixing down. The , Operating Supply Current PROGRAMMABLE COUNTER Max. Operation Frequency Min. Operation Input Voltage , B A ELECTR ON IC 02 ^ 0^72 47 0017030 : f l T -5 0 -1 7 2, PROGRAMMABLE COUNTER (13 BIT PROGRAMMABLE COUNTER ) Divided byindicated divide · Programmable counter Is a 13bit variable divider


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PDF TC9109BP TC9109BP 3D18A-P 24MHz) 405MHz) 71MHz) 7-segment 4 digit 5461 TLR-321 TLR321 cd 5411 ic tc9109
diode m7 toshiba

Abstract: DIP20-P-300-2 TC9256F TC9256P TC9257F TC9257P TC9256 "Overflow detection"
Text: programmable counter , dual parallel output phase comparator, crystal oscillator and reference counter . â , clock output pin. VDD C )—1—■-H 11 (-) 1/0-6 13 (10) AM|N Programmable counter input , MODE OSC1 OSC2 Address = D2 H - Programmable counter data- (*3) (*5) |— TV -Reference-frequency code data TV TV T ■re- programmable Crystal counter oscillator mode selection bits -(*3)-1 GO , occurs when bits RO, R1, R2 and R3 are all set to "1". In standby mode, the programmable counter stops


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PDF TC9256 57P/F TC9256P, TC9256F, TC9257P, TC9257F TC9257P TC9257F diode m7 toshiba DIP20-P-300-2 TC9256F TC9256P "Overflow detection"
tc91068p

Abstract: TC9106 tc9106bp ic 3389 LED programmable counter ic TLR321 IC counter 3 digit LED 2 digit 7 segment led frequency divider rotary counter ISA13
Text: -16MK2 - 18 25 oA PROGRAMMABLE COUNTER Max. Operating Frequency fMAX VDD-7.5V 20 - KH2 , Programmable counter has frequency devlde shift, function to that VCO oscillation frequency tiay shift 4S5klU , COUNTER (13 BIT PROGRAMMABLE COUNTER ) • Programmable counter is a 13 bit variable divider. Divided by , special high speed programmable counter , maximum operation frequency is higher than 20 MHz at VpD=8V. Therefore can be divided directly by programmable counter without VCO oscillation frequency mixingdown in


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PDF TC91068P TC9106BP 3D18A-P -55channel T-50-17 TC9106 tc9106bp ic 3389 LED programmable counter ic TLR321 IC counter 3 digit LED 2 digit 7 segment led frequency divider rotary counter ISA13
presettable digital clock

Abstract: IC1 723
Text: adjustable by the 8-bit programmable counter and the system clock. The system clock can be divided internally , .b it predivider W L L H H X L H L H clock fo r programmable counter CP/X X = 1 X = 16 X = 256 X = 4096 , Programmable 8-bit counter * inputs active LOW A B C D E F G H value 1 2 4 E 16 32 64 128 * A ll inputs A to , input CP is, at its original frequency, the system clock, but it also drives the programmable counter , . Parts o f the flip -flop s are used together w ith the programmable 8-bit counter as a retriggerable m


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PDF HEF4753B HEF4753B presettable digital clock IC1 723
SC9257S

Abstract: SC9257 DIP20 FMH 110
Text: : 0.5 to 40 MHz .( with 2 modulus prescaler or direct dividing ) * 16-bit programmable counter , select R2 R3 Reference frequency code data Programmable counter data Address=D2H R1 FM MODE OSC1 OSC2 Crystal oscillator selection bits Programmable counter mode (*2) SC , bits R0,R1,R2,and R3 are all set to " .In standby mode, the programmable 1" counter stops, and FM, AM , the I/O ports are set to input mode. Programmable counter The programmable counter section consists


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PDF SC9257 SC9257 DIP-20-300-2 DIP20, OP-20-300-1 16-bit SC9257S DIP20 FMH 110
2007 - SC9257S

Abstract: No abstract text available
Text: select R2 R3 Reference frequency code data Programmable counter data Address=D2H R1 FM MODE OSC1 OSC2 Crystal oscillator selection bits Programmable counter mode (*2) SC , to “ .In standby mode, the programmable 1” counter stops, and FM, AM and IFIN are set to â , to input mode. Programmable counter The programmable counter section consists of a 1/2 prescaler, a 2 modulus prescalers and a 4bit +12bit programmable binary counter . 1. Setting programmable


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PDF SC9257 SC9257 DIP-20-300-2 DIP20, OP-20-300-1 16-bit SC9257S
TC9181P

Abstract: TC9181F cb radio
Text: on, because of it's various purposive system design. Built in 12 bits programmable counter as a reference frequency divider, so frequency division range of programmable counter is 5~4095 divisions according to serial data. Built in swallow type programmable counter to generate very high frequency , purposive output ports externally controllable by serial data. — 6 P|N Programmable counter input Programmable counter input terminal. Input an external prescaler output through a coupling capacitor. — 7


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PDF TC9181P/F TC9181P, TC9181F TC9181P TC9181F tc9181p cb radio
1997 - HIGH SPEED FREQUENCY DIVIDER

Abstract: MN6155
Text: Swallow counter 3-bit counter Swallow counter Control 13-bit programmable counter 14-bit programmable counter 18-bit latch 18-bit shift register 17-bit latch Switching circuit 3 14 , divider stage output frequency N : Setting for 14-bit programmable counter on comparator side A : Setting for 4-bit swallow counter on comparator side R : Setting for 17-bit programmable counter on low-speed reference side NR : Setting for 13-bit programmable counter on high-speed reference side AR


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PDF MN6155 MN6155 SSOP016-P-0225 HIGH SPEED FREQUENCY DIVIDER
1994 - MB15B01

Abstract: No abstract text available
Text: -bit swallow counter : 0 to 127 ­ Binary 11-bit programmable counter : 16 to 2,047 Each programmable counter , programmable counter (PLL1) Charge pump (PLL-1) 8 fr fr 15 fp 14 LD2 12 DO2 , Schmitt circuit Binary 11-bit programmable counter (PLL2) Phase comparator (PLL2) fP2 , transferred to one of PLL1 programmable counter , PLL2 programmable counter and programmable reference counter , : Preset divide ratio of binary 11-bit programmable counter (16 to 2,047) A: Preset divide ratio of


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PDF MB15B01 I9412
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