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Part Manufacturer Description Datasheet Download Buy Part
DC1613A Linear Technology INTERFACE MOD FOR LTPOWERPLAY
LT4430HS6 Linear Technology IC SPECIALTY INTERFACE CIRCUIT, PDSO6, PLASTIC, MO-193, TSOT-23, 6 PIN, Interface IC:Other
LT4430HS6#TR Linear Technology IC SPECIALTY INTERFACE CIRCUIT, PDSO6, PLASTIC, MO-193, TSOT-23, 6 PIN, Interface IC:Other
LT4430HS6#TRM Linear Technology IC SPECIALTY INTERFACE CIRCUIT, PDSO6, PLASTIC, MO-193, TSOT-23, 6 PIN, Interface IC:Other
LT4430MPS6#TRM Linear Technology IC SPECIALTY INTERFACE CIRCUIT, PDSO6, PLASTIC, MO-193, TSOT-23, 6 PIN, Interface IC:Other
LT4430IS6#TR Linear Technology IC SPECIALTY INTERFACE CIRCUIT, PDSO6, PLASTIC, MO-193, TSOT-23, 6 PIN, Interface IC:Other

powerwise interface Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2007 - mipi controller

Abstract: ARM926 powerwise interface national pwi bus
Text: Unit (EMU) PowerWise ® Interface (PWI) Off-Chip AMBA APB 1. SoC PowerWise . . National PowerWise . , SoC 1 AMBA , APC(Advanced , PWI( PowerWise Interface ) . APC2 CMU . Fixed-Vdd 140 130 120 , PowerWise ® ® PowerWise . , ) , . . ." PowerWise National PowerWise SoC


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2006 - voltage scaling

Abstract: TSMC embedded Flash tsmc cmos TSMC Flash IP APC2 emu ARM926 LP5550 National Discrete Products pm2006 powerwise interface
Text: · Generic interface © 2006 National Semiconductor Corporation 5 PowerWise ® Technology , Unit (EMU) ­ PowerWise compatible regulators ­ PWI slave ­ National Semiconductor or licensee products · PowerWise Interface (PWI) ­ Connects APC and EMU ­ Open standard interface © 2006 , Timer I2S Versatile Timer GPIO MIWU USB APC PowerWise Interface Remap RTC , USART (2x) I2S ARM Timer GPIO APC USB Flash ROM, SRAM, SDRAM PowerWise Interface


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2004 - verilog code for apb

Abstract: 9297-APC1-D101 SY751-DC-06002 APC1 Release Notes SY751-DA-03001 verilog code voltage regulator timing diagram of AMBA apb protocol SY751-DC-06002 SY751-DC-08001 SY751-MN-22001 LN+9297
Text: ) System clock Performance indexes PowerWise Interface (PWI) Clock Management Unit (CMU , PWI master interface Control logic Host Interface PowerWise Interface (PWI) PWI slave , interface EMU PowerWise Interface (PWI) PWI Slave Interface Open-loop voltage table , external power supplies conforming to the PowerWise Interface (PWI). AMBA See Advanced Microcontroller , Energy Management Unit. Energy Management Unit (EMU) A PowerWise Interface (PWI) compliant power


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PDF 9297-APC1-D101 verilog code for apb 9297-APC1-D101 SY751-DC-06002 APC1 Release Notes SY751-DA-03001 verilog code voltage regulator timing diagram of AMBA apb protocol SY751-DC-06002 SY751-DC-08001 SY751-MN-22001 LN+9297
TSMC 180nm dual port sram

Abstract: TSMC 90nm sram tsmc 180nm sram voltage regulator I2C 10GBASE-T TSMC 90nm flash ARM926EJ-S 120C and/TSMC 90nm sram powerwise interface
Text: Real-time continuous closed-up PWI = PowerWise Interface 11 DVS vs. AVS Pre-defined frequency-voltage , Clock Generation Reset & Sys Mgmt PowerWise Interface I2S ARM Timer GPIO APC USB Flash ROM, SRAM, SDRAM 19 RTC PowerWise Interface Example 2 Measured Results Fixed-Vdd , PowerWise ® Adaptive Voltage Scaling (AVS) Technology Webinar Rick Zarr, PowerWise ® Technologist , digital subsystems in various applications · Discuss PowerWise ® Adaptive Voltage Scaling (AVS


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powerwise interface

Abstract: solar voltage regulator digital clock using logic gates PMIC "power gating" switching management Solar panel regulator
Text: Table V.vs PowerWise Interface (PWI) Vqatt n AVS Voilage Regulator 2 AVS Regulator 1 Power , single scaled voltage island. APC1 supports the PowerWise Interface 1.0 compliant point-to-point , : APC1 and APC2 key feature comparison Feature APC1 APC2 PMIC interface PowerWise Interface 1.0 PowerWise Interface 2.0 Multiple peripherals No Yes Number of scaled voltage islands 1 1-4 Number of , Hardware Accelerator Hi DVFS Domain 1 ->\ > I HPM1 Clock Clock Management Unit Host Interface Target


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Level Shifters

Abstract: Gate level simulation without timing "Level Shifter" powerwise interface voltage scaling APC powerwise POWERWISE APC
Text: Timer GPIO MIWU USB APC PowerWise Interface Clock Generation Reset & Sys Mgmt Flash ROM, SRAM, SDRAM Versatile Timer ARM Timer APC PowerWise Interface Image Sensor I , APC PowerWise Interface Level Shifters Clock Generation Reset & Sys Mgmt Flash ROM, SRAM, SDRAM Versatile Timer ARM Timer APC PowerWise Interface Image Sensor I/F RTC , tricky timing problems to worry about if the boundary is an asynchronous interface Synchronous


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2006 - verilog code for interrupt controller amba based

Abstract: verilog code for ALU implementation APC2 emu AN 10349 verilog code voltage regulator verilog code for apb
Text: ) APC2 PowerWise ® Interface (PWI) Off-chip Clocks to processor and others AMBA APB Figure , master PowerWise Interface (PWI) PWI slave DVS voltage table Figure 1-3 Closed-loop AVS , PWI master PowerWise Interface (PWI) PWI slave DVS voltage table Figure 1-4 , external power supplies conforming to the PowerWise Interface (PWI). AMBA See Advanced Microcontroller , Energy Management Unit. Energy Management Unit (EMU) A PowerWise Interface (PWI) compliant power


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PDF 10349-APC2-D101 verilog code for interrupt controller amba based verilog code for ALU implementation APC2 emu AN 10349 verilog code voltage regulator verilog code for apb
2005 - LM3370

Abstract: LM5026 LP5550 BAT54 LM1770 SIGNAL PATH designer c25 mosfet
Text: · V02 PWI · · V03 SCLK SPWI PowerWise ® Interface · (APC) RTC etc. PWI · GND LP5550 · (AVS) PowerWise ® (EMU) · 1 3 · , PowerWise ® Interface (PWI) IC FPGA Figure 4 FPGA I/O FGPA , . 1-7 I2C 2 DC/DC . 2 70 PowerWise ® . 4 SOT , power.national.com/jpn 3 70 PowerWise ® (AVS) LP5550 LP5550 VBAT LP5550 EMU VOSW ·


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PDF OT-23 LM3370 550263-009-JP LM3370 LM5026 LP5550 BAT54 LM1770 SIGNAL PATH designer c25 mosfet
2006 - AN-1460

Abstract: LP5550 national pwi bus
Text: .0, but a similar scheme could be used for PWI2.0 functionality. PowerWise Interface (PWI) compatible , Emulating the PowerWise Interface Using GPIOs and Software Emulating the PowerWise Interface Using GPIOs , said circuitry and specifications. Emulating the PowerWise Interface Using GPIOs and Software , presented has been verified using National's COP8 microcontroller and the LP5550 PowerWise EMU, but should , communication over the PWI is managed with a 2-wire serial interface . The PWI data line, SPWI, is bidirectional


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PDF LP5550 CSP-9-111S2) CSP-9-111S2. AN-1460 AN-1460 national pwi bus
2008 - LMK212BJ106KD

Abstract: AN1653 DIP26 vishay resistor 0603 1 0.1W LPS3010-102ML NC7SZ126M5 vishay 0402 SMD capacitors AN1610 SOT23-5 REGULATORS mainboard layout
Text: open-standard interface . The LP5552 operates cooperatively with PowerWise ® technology-compatible processors to , from a mainboard such as the PowerWise Evaluation Kit (PEK) or USB2PWI interface board. The , GUI. The PEK is designed to quickly and easily control the LP5552 for PowerWise Interface (PWI , be done in the following order to ensure best performance: 1. Switchers 2. PowerWise Interface 3 , practice to minimize high-current and switchingcurrent paths. POWERWISE INTERFACE ROUTING The PowerWise


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PDF LP5552 AN-1610 LMK212BJ106KD AN1653 DIP26 vishay resistor 0603 1 0.1W LPS3010-102ML NC7SZ126M5 vishay 0402 SMD capacitors AN1610 SOT23-5 REGULATORS mainboard layout
2008 - Not Available

Abstract: No abstract text available
Text: the GUI, see AN-1653 User's Graphical User Interface (GUI) for LP555x Evaluation Board PowerWise , to quickly and easily control the LP5552 for PowerWise Interface (PWI) compliance testing. Figure 3 , . PowerWise Interface 3. Input Caps 4. LDO Output Caps 5. Any remaining layout 4 AN-1610 LP5552 , these connections. 6.2 PowerWise Interface Routing The PowerWise SCLK and SPWI lines should then , restrictions in the PowerWise Interface 2.0 specification. 6.3 Input Capacitors Any additional input


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PDF SNVA231B AN-1610 LP5552
2006 - ARM926

Abstract: arm9 architecture powerwise interface
Text: APC / APC IC PowerWise PowerWise N-/P- PowerWise SoC SoC APC AMBA CMU PowerWise Interface PWI 3 CMU / APC2 2 , PowerWise PowerWise /IC AVS 3 (SoC) AVS 2 AVS 1 Vcore fixed , Vavs0 Vbatt VIO (EMU) PowerWise


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PDF 570624-003-JP ARM926 arm9 architecture powerwise interface
2008 - Not Available

Abstract: No abstract text available
Text: Voltage Scaling PowerWise ® Interface (PWI) Off-Chip PowerWise Adaptive Voltage Scaling Time , ® national.com/ powerwise ® 95 / P 2 ENOB Fs ch P Tr ch P tj ch 2 % 2.5 pJ/ 20 pJ 120 mW·pS AVS Domain 3 AVS Domain 2 AVS Domain 1 Vbatt VIO 100% Vcore fixed AVS Domain 0 Hardware Performance Monitor (HPM) HPM Clock System Clock , , , and PowerWise are registered trademarks of National Semiconductor Corporation. ARM is a registered


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2009 - AVS Technology

Abstract: No abstract text available
Text: Energy Management Unit (EMU) via an open-standard PowerWise ® Interface (PWI) to adjust the voltage , National Semiconductor PowerWise ® Adaptive Voltage Scaling Technology With the emphasis on lowering power consumption a concern for system designers, National Semiconductor has pioneered a new , Semiconductor Corporation, 2009. National Semiconductor, PowerWise , and are registered trademarks of National , rights reserved. To learn more about PowerWise AVS technology from National Semiconductor, visit


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2006 - UMC PMIC

Abstract: offline switcher ARM926EJ-S LP5550 powerwise interface ARM926 National Semiconductor Simplifying Power Design national pwi bus ARM ARCHITECTURE Semiconductor
Text: for leakage reduction PWI 1.0 ( PowerWise ® Interface : 1st generation bus standard) 12 © 2006 , Voltage and Freq scaling · Large safety margins High Power · Analog Control Loops · Generic interface 7 © 2006 National Semiconductor Corporation PowerWise ® Technology Adaptive Voltage Scaling · , © 2006 National Semiconductor Corporation PowerWise ® Technology Components · Energy Aware SoC ­ , Slave Power Controller (SPC) ­ Transient response correct for multi-loop control system · PowerWise


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2009 - Advance Power

Abstract: No abstract text available
Text: is sent by the APC via the PowerWise Interface (PWI) or System Power Management Interface (SPMI), a , National Semiconductor PowerWise ® Adaptive Voltage Scaling (AVS) for Portable Applications Adaptive Voltage Scaling (AVS) Adaptive Voltage Scaling (AVS) technology is a realtime, continuous, closed-loop power management technology. The AVS technology enables optimized power delivery to processors , Semiconductor Corp. http://www.national.com/avs PowerWise ® Adaptive Voltage Scaling (AVS) Implementation


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PDF 240MHz. Advance Power
2011 - Not Available

Abstract: No abstract text available
Text: PowerWise Interface (PWI) 1.0 or PWI 2.0 high-speed serial interface . A typical power saving of 40% can be , . Digital ground for VPWI and digital interface : SPWI and SCLK. PowerWise Interface (PWI) supply input, 1.8 V-10% to 3.3V+10%. A bypass capacitor of 1µF is recommended on this pin. PowerWise Interface (PWI) bi-directional data pin. This pin is internally pulled down to ground. PowerWise Interface (PWI) clock input , : 2b01 2b10 PWI version 1.0 PWI version 2.0 Description or Comment See PowerWise interface Selection


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PDF LM10500
2011 - AN-2080

Abstract: adc matlab audio block diagram LM10500 mosfet smd code fh temperature regulation matlab code powerwise interface
Text: . The device is controlled via PowerWise Interface (PWI) 1.0 or PWI 2.0 high-speed serial interface . A , and SCLK. 18 VPWI P PowerWise Interface (PWI) supply input, 1.8 V-10% to 3.3V+10%. A bypass capacitor of 1µF is recommended on this pin. 19 SPWI I/O PowerWise Interface (PWI) bi-directional data pin. This pin is internally pulled down to ground. 20 SCLK I PowerWise Interface , PWI version 1.0 2b10 PWI version 2.0 See PowerWise interface Selection section for


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PDF LM10500 LM10500 AN-2080 adc matlab audio block diagram mosfet smd code fh temperature regulation matlab code powerwise interface
2011 - Not Available

Abstract: No abstract text available
Text: process and temperature variations. The device is controlled via PowerWise Interface (PWI) 1.0 or PWI 2.0 , . Digital ground for VPWI and digital interface : SPWI and SCLK. PowerWise Interface (PWI) supply input, 1.8 V-10% to 3.3V+10%. A bypass capacitor of 1µF is recommended on this pin. PowerWise Interface (PWI) bi-directional data pin. This pin is internally pulled down to ground. PowerWise Interface (PWI) clock input , : 2b01 2b10 PWI version 1.0 PWI version 2.0 Description or Comment See PowerWise interface Selection


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PDF LM10500 LM10500 SNVS630F
2009 - AVS Technology

Abstract: powerwise interface
Text: voltage optimization command is sent by the APC via the PowerWise Interface (PWI) to the Energy , National Semiconductor PowerWise ® Adaptive Voltage Scaling (AVS) for Converged Network Adapter (CNA) Cards Adaptive Voltage Scaling (AVS) Adaptive Voltage Scaling (AVS) technology is a realtime, continuous, closed-loop power management technology. AVS technology enables optimized power delivery to , Semiconductor Corp. http://www.national.com/avs PowerWise ® Adaptive Voltage Scaling (AVS) Implementation


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2011 - CAPACITOR SMD MARKING CODE QP

Abstract: UF10V
Text: PowerWise Interface (PWI) 1.0 or PWI 2.0 high-speed serial interface . A typical power saving of 40% can be , . Digital ground for VPWI and digital interface : SPWI and SCLK. PowerWise Interface (PWI) supply input, 1.8 V-10% to 3.3V+10%. A bypass capacitor of 1µF is recommended on this pin. PowerWise Interface (PWI) bi-directional data pin. This pin is internally pulled down to ground. PowerWise Interface (PWI) clock input , : 2b01 2b10 PWI version 1.0 PWI version 2.0 Description or Comment See PowerWise interface Selection


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PDF LM10500 CAPACITOR SMD MARKING CODE QP UF10V
2008 - Not Available

Abstract: No abstract text available
Text: Supply 64% Dynamic Voltage Scaling PowerWise ® Interface (PWI) Off-Chip Clocks to Processor , PowerWise ® Solutions Enabling Energy-Efficient Designs www.national.com/ powerwise PowerWise , developed the PowerWise ® product line. With National's PowerWise ICs, design engineers can create products and systems that consume less power, extend battery life and generate less heat. PowerWise devices and subsystems, found in every National product family from interface products to high-speed data


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2006 - marking code 4h

Abstract: No abstract text available
Text: Supports high-efficiency PowerWise Technology Adaptive Voltage Scaling n PWI open standard interface for , I Type D D D A P A G D P A G P A A G D Description PowerWise Interface (PWI) clock input PowerWise , INFORMATION The LP5550 is a PowerWise Interface (PWI) compliant power management unit (PMU) for application or , . PowerWise (TM) INTERFACE To support DVS and AVS, the LP5550 is programmable via the low power, 2 wire PowerWise Interface (PWI). This serial interface controls the various voltages and states of all the


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PDF LP5550 LP5550 SNVS378F marking code 4h
2005 - marking code 4h

Abstract: No abstract text available
Text: Supports high-efficiency PowerWise Technology Adaptive Voltage Scaling n PWI open standard interface for , I Type D D D A P A G D P A G P A A G D Description PowerWise Interface (PWI) clock input PowerWise , INFORMATION The LP5550 is a PowerWise Interface (PWI) compliant power management unit (PMU) for application or , . PowerWise (TM) INTERFACE To support DVS and AVS, the LP5550 is programmable via the low power, 2 wire PowerWise Interface (PWI). This serial interface controls the various voltages and states of all the


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PDF LP5550 marking code 4h
2008 - 20-21031

Abstract: No abstract text available
Text: serial PWI 2.0 open-standard interface . The LP5552 operates cooperatively with PowerWise , input high for normal operation. PowerWise Interface (PWI) clock input PowerWise Interface (PWI , LP5552 LP5552 Operation GENERAL DESCRIPTION The LP5552 is a PowerWise Interface (PWI) 2.0 compliant , delivered. POWERWISE INTERFACE What follows is only a brief description of the parts of the PWI 2.0 spec , and AVS, the LP5552 is programmable via the low-power, 2-wire PowerWise Interface (PWI). This serial


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