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Part Manufacturer Description Datasheet Download Buy Part
LT1109ACS8-12#PBF Linear Technology LT1109A - Micropower DC/DC Converter Flash Memory VPP Generator Adjustable and Fixed 5V, 12V; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LT1109ACS8-5 Linear Technology LT1109A - Micropower DC/DC Converter Flash Memory VPP Generator Adjustable and Fixed 5V, 12V; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LT1109ACS8#TRPBF Linear Technology LT1109A - Micropower DC/DC Converter Flash Memory VPP Generator Adjustable and Fixed 5V, 12V; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LT1109ACN8-12 Linear Technology LT1109A - Micropower DC/DC Converter Flash Memory VPP Generator Adjustable and Fixed 5V, 12V; Package: PDIP; Pins: 8; Temperature Range: 0°C to 70°C
LT1109ACS8-12#TRPBF Linear Technology LT1109A - Micropower DC/DC Converter Flash Memory VPP Generator Adjustable and Fixed 5V, 12V; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LT1109ACS8#TR Linear Technology LT1109A - Micropower DC/DC Converter Flash Memory VPP Generator Adjustable and Fixed 5V, 12V; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C

power generation POWER COMMAND HM 1211 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
C-CUBE CL450

Abstract: CL9100
Text: 8.3.2 Interrupt Control Registers 8-11 8.3.3 Command /Status Registers 8-14 8.3.4 , Configurations 9-1 9.1.1 Command Process 9-4 9.1.2 Bitstream Transfer Process 9-5 9.1.3 , Command States 11-4 11.2.1 IDLE State 11-5 11.2.2 PLAY-SETUP State 11-5 11.3 Command FIFO 11.4 Command Latency 11.5 M acro Command Groups 11.5.1 Set-Type Commands 11-8 , acro Command Reference A ccessSC R O 11-14 11-15 ClearlntPinO 11-17 CopyDRAMO 11-19


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PDF 00DQ4Ã CL450 17b45bT C-CUBE CL450 CL9100
1995 - POWER COMMAND HM 1211

Abstract: power generation POWER COMMAND HM 1211 HP48-HP33 AR15-AR0 AR31-AR16 HP32 hp4841 HP48-41 hm 6164 HP19
Text: , status and host command ) 16377 Dword read/write locations corresponding to one Dword input data FIFO , written to the HI32. Supports parity generation , detection and reporting. Supports system error generation and reporting. HI32 features in the Universal Bus modes: 1. 2. 3. 4. 5. 6. 7. 8 , Register CSTR/CCMR Status/ Command Configuration Register HCVR Host Command Vector Register , as zero and should be written with zero Bit Name Function 0 HCIE Host Command


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PDF DSP56300 POWER COMMAND HM 1211 power generation POWER COMMAND HM 1211 HP48-HP33 AR15-AR0 AR31-AR16 HP32 hp4841 HP48-41 hm 6164 HP19
encoder/GEC 44 3A

Abstract: GEC 44 3A
Text: system flag generation require no external logic Two Mask registers allow masking of individual bits , cascading and system flag generation require no external logic. The LAN CAM is synchronously controlled by , facility converts between IEEE 802.3 (CSMA/CD) and 802.5 (Token Ring) address formats on command . Both , / Command Select, Input, TTL) The /CM input selects whether the inputs on the DQODQ15 lines are data or commands. /CM LOW selects Command cycles and /CM HIGH Data cycles. /FI (Full Input, Input, TTL) The


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PDF 37bflS22 PNC1480 1kx64-BIT 64-bit 16-bit 16-blt encoder/GEC 44 3A GEC 44 3A
Not Available

Abstract: No abstract text available
Text: cascading and system flag generation require no external logic. The LAN CAM is synchronously controlled by , facility converts between IEEE 802.3 (CSMA/CD) and 802.5 (Token Ring) address formats on command . Both , ext-freeaddress cycles Vertical cascading and system flag generation require no external logic Two M ask , ISTIC S Symbol 'cc Parameter Min Units 200 Average Power Supply Current Max , . /W LOW selects a Write cycle, and /W HIGH selects a Read cycle. /CM (Data/ Command Select, Input


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PDF DS3112-2 P1480 1kx64-BIT P1480 64-bit D05S4Q2
1999 - 44-PIN

Abstract: DS3112 P1480
Text: system flag generation require no external logic. The LAN CAM is synchronously controlled by four wires , converts between IEEE 802.3 (CSMA/CD) and 802.5 (Token Ring) address formats on command . Both random , , associative access, and write-at-next-freeaddress cycles I Vertical cascading and system flag generation , Output Voltage Logic "1" VOL Output Voltage Logic "0" Units 200 Average Power Supply , LOW selects a Write cycle, and /W HIGH selects a Read cycle. /CM (Data/ Command Select, Input, TTL


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PDF P1480 P1480 1kx64-Bit DS3112 64-bit 23all 44-PIN
2001 - Not Available

Abstract: No abstract text available
Text: communication with the device over a 16-bit bus. Vertical cascading and system flag generation require no , 802.5 (Token Ring) address formats on command . Both random access and associative operations are , write-at-next-freeaddress cycles I Vertical cascading and system flag generation require no external logic I Two Mask , fall below -0.5V. ELECTRICAL CHARACTERISTICS Symbol ICC VOH VOL IIZ IOZ Parameter Average Power , . /CM (Data/ Command Select, Input, TTL) The /CM input selects whether the inputs on the DQ0DQ15 lines


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PDF P1480 P1480 1kx64-Bit DS3112 64-bit 64-bits
1999 - P1480-12CG

Abstract: No abstract text available
Text: communication with the device over a 16-bit bus. Vertical cascading and system flag generation require no , 802.5 (Token Ring) address formats on command . Both random access and associative operations are , write-at-next-freeaddress cycles I Vertical cascading and system flag generation require no external logic I Two Mask , fall below -0.5V. ELECTRICAL CHARACTERISTICS Symbol ICC VOH VOL IIZ IOZ Parameter Average Power , . /CM (Data/ Command Select, Input, TTL) The /CM input selects whether the inputs on the DQ0DQ15 lines


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PDF P1480 P1480 1kx64-Bit DS3112 64-bit 64-bits P1480-12CG
2006 - 0315H

Abstract: MF24 mi 8025 0166H 09A7H
Text: cascading and system flag generation require no external logic. The LAN CAM is synchronously controlled by , facility converts between IEEE 802.3 (CSMA/CD) and 802.5 (Token Ring) address formats on command . Both , flag generation require no external logic I Two Mask registers allow masking of individual bits for , ELECTRICAL CHARACTERISTICS Symbol ICC VOH VOL IIZ IOZ Parameter Average Power Supply Current Output Voltage , memory cycle. /W LOW selects a Write cycle, and /W HIGH selects a Read cycle. /CM (Data/ Command Select


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PDF P1480 P1480 1kx64-Bit DS3112 64-bit 0315H MF24 mi 8025 0166H 09A7H
1999 - 09A7H

Abstract: No abstract text available
Text: communication with the device over a 16-bit bus. Vertical cascading and system flag generation require no , 802.5 (Token Ring) address formats on command . Both random access and associative operations are , write-at-next-freeaddress cycles I Vertical cascading and system flag generation require no external logic I Two Mask , fall below -0.5V. ELECTRICAL CHARACTERISTICS Symbol ICC VOH VOL IIZ IOZ Parameter Average Power , . /CM (Data/ Command Select, Input, TTL) The /CM input selects whether the inputs on the DQ0DQ15 lines


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PDF P1480 P1480 1kx64-Bit DS3112 64-bit 64-bits 09A7H
0927H

Abstract: D015 016Fh P1480-12CG Priority Encoder CAM p1480-12cgdpas 0504H SS22 P1480 0507H
Text: -bit bus. Vertical cascading and system flag generation require no external logic. The LAN CAM is , translation facility converts between IEEE 802.3 (CSMA/CD) and 802.5 (Token Ring) address formats on command , , associative access, and write-at-next-free-address cycles ■Vertical cascading and system flag generation , 'cc Average Power Supply Current 200 mA V0H Output Voltage Logic "1" 2.4 Volts 'OH = -2.0 mA VOL , . /CM (Data/ Command Select, Input, TTL) The /CM input selects whether the inputs on the DQO-DQ15 lines


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PDF P1480 DS3112-2 1kx64-BIT P1480 64-bit 64-bits 0DE54Q2 5C226 0927H D015 016Fh P1480-12CG Priority Encoder CAM p1480-12cgdpas 0504H SS22 0507H
1998 - power generation POWER COMMAND HM 1211

Abstract: POWER COMMAND HM 1211 manual POWER COMMAND HM 1211 PM19 Package D-18 DSP56300 DSP56305 BRF6
Text: Group column, change Power (VCC) to Power (VCC)5 and Ground (GND) to Ground (GND)5 · Change number of Power (VCC) connections to 45. · Change number of Ground (GND) connections to 38. · Add note 5 to , : DSP56305 VCCP VCC 44 Power Inputs4: PLL Internal Logic and I/O MODA/IRQA MODB/IRQB MODC , GPIO signals (PE[0­]2), respectively. TIO[0­2] can be configured as GPIO signals. The number of power , different package types and had different numbers of power and ground pins. Figure 2-1. Signals


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PDF DSP56305UMAD/D DSP56305 power generation POWER COMMAND HM 1211 POWER COMMAND HM 1211 manual POWER COMMAND HM 1211 PM19 Package D-18 DSP56300 BRF6
Not Available

Abstract: No abstract text available
Text: Vertical cascading and system flag generation require no external logic Device gives status information , cascading and system flag generation require no external logic, providing a system match and full flag. The , cycle. /CM (Data/ Command Select, Input, TTL) The /CM input selects whether the signals on DQ15DQO , connected to the /FI input of the next-lower priority device in the chain. VCC, GND (Positive Power Supply and Ground) These pins are the main power supply connections to the MU9C5480. VCC must be held


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PDF 64-bit MU9C1480 16-bit
Not Available

Abstract: No abstract text available
Text: -bit bus. Vertical cascading and system flag generation require no external logic. The LAN CAM is , translation facility converts between IEEE 802.3 (CSMA/CD) and 802.5 (Token Ring) address formats on command , cascading and system flag generation require no external logic Tw o M ask registers allow m asking of , Voltage Logic "1" VOL Output Voltage Logic “0" Units 200 Average Power Supply Current , (Data/ Command Select, Input, TTL) The /CM input selects whether the inputs on the DQODQ15 lines are


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PDF DS3112-3 P1480 1kx64-BIT P1480 64-bit 0D2T211
2011 - sandisk SDHC product manual

Abstract: CMD58 Transcend 1 GB SD "SD CARD COMMANDS" CMD55 sandisk sdhc sandisk SDHC product manual 4 GB fat32 library FAT16 SanDisk Secure Digital Card Product Manual
Text: Application Note Implementing a Secure Digital Card with a ZNEO Microcontroller AN032001- 1211 , file contents AN032001- 1211 Page 1 of 39 Implementing a Secure Digital Card with a ZNEO , maximum capacity. See Figure 1. Figure 1. SanDisk 2GB SD card AN032001- 1211 Page 2 of 39 , thru a simple command . The SD card, acting as the slave, responds to the CMD0 command , followed by a , FAT16 file map. AN032001- 1211 Page 3 of 39 Implementing a Secure Digital Card with a ZNEO


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PDF AN032001-1211 FAT16 FAT32 sandisk SDHC product manual CMD58 Transcend 1 GB SD "SD CARD COMMANDS" CMD55 sandisk sdhc sandisk SDHC product manual 4 GB fat32 library SanDisk Secure Digital Card Product Manual
2004 - winbond 2503

Abstract: heceta6 GPO41-40 LM 8523 EQUIVALENT Dell 3147 board diagram B 8530 transistor transistor tag 8530 PC8374L n82077 LM96012
Text: ) . 142 8.4.3 HM Status and Command Register (HMSTS , GPIO, and ACPI-compliant Power Management support. The PC8374L integrates miscellaneous analog and , Bridge functionality VSB3-powered Power Management with 19 wake-up sources Controls three LED indicators , Revision 1.0 and Advanced Configuration and Power Interface (ACPI) Specification Revision 2.0 compliant 128-pin PQFP package Block Diagram LPC Bus South Bridge Power Management Serial Interfaces


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PDF
2004 - winbond 2503

Abstract: transistor tag 8530 GPO41-40 PC8374L LM 8523 heceta6 INTEL 845 MOTHERBOARD CIRCUIT diagram GPE1 TAG 8546 PC MOTHERBOARD CIRCUIT MANUAL dell 1010
Text: ) . 142 8.4.3 HM Status and Command Register (HMSTS , as GPIO, and ACPI-compliant Power Management support. The PC8374L integrates miscellaneous analog , Bridge functionality VSB3-powered Power Management with 19 wake-up sources Controls three , Power Interface (ACPI) Specification Revision 2.0 compliant 128-pin PQFP package Block Diagram LPC Bus Power Management South Bridge System BIOS Serial Interfaces Parallel Port


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PDF PC8374L PC8374L PC837x PC837x winbond 2503 transistor tag 8530 GPO41-40 LM 8523 heceta6 INTEL 845 MOTHERBOARD CIRCUIT diagram GPE1 TAG 8546 PC MOTHERBOARD CIRCUIT MANUAL dell 1010
1995 - power generation POWER COMMAND HM 1211

Abstract: HAD31-HAD8 DSP56300 POWER COMMAND HM 1211 generator POWER COMMAND HM 1211 GB300 LT5013 intel 845 crb sa 7454 DSP56301
Text: ) . 2-17 2.2.11 Power & Ground (51 Pins , ). 6-9 6.1.1.1 Host Command Interrupt Enable (HCIE) Bit 0 . 6-9 , ). 6-25 6.1.4.1 PCI Bus Command (C3-C0) Bits 11-8 . 6-26 , Host Command Pending (HCP) Bit 0 . 6-28 6.1.5.2 Slave , 6-58 6.2.3 Host Command Vector Register (HCVR) . 6-58


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PDF DSP56301 24-BIT DSP56301 power generation POWER COMMAND HM 1211 HAD31-HAD8 DSP56300 POWER COMMAND HM 1211 generator POWER COMMAND HM 1211 GB300 LT5013 intel 845 crb sa 7454
Not Available

Abstract: No abstract text available
Text: system flag generation require no external logic o Two Mask registers allow masking of individual , . cascading and system flag generation require no external logic. The LANCAM™ is synchronously controlled , facility converts between IEEE 802.3 (CSMA/CD) and 802.5 (Token Ring) address formats on command . Both , Full condition. /FI (Full Input, Input, TTL) /CM (Data/ Command Select, Input, TTL) The /CM input selects whether the input signals on DQ0-DQ15 are data or commands. /CM LOW selects Command cycles and


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PDF MU9C1480 64-bit 16-bit
Not Available

Abstract: No abstract text available
Text: cascading and system flag generation require no external logic ■Two Mask registers allow masking of , allow communication with the device over a 16-bit bus. Vertical cascading and system flag generation , data or commands. /C M LOW selects Command cycles and /C M H IG H Data cycles. The /F I input is , in the chain. /EC (Enable Comparison, Input, TTL) VCC, GND (Positive Power Supply and Ground , H . These pins are the main power supply connections to the P1480. V C C must be held at + 5 V +


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PDF P1480 1kx64-BIT 64-blt 16-bit
DHT11

Abstract: BC417143 HM-10 BC417143* commands
Text: -Last Version V527 2014-04-12 20 HM Bluetooth module datasheet Note1: This command added in , -Last Version V527 2014-04-12 22 HM Bluetooth module datasheet Default: 0 This command , until next power on. 23. Query/Set filter of HM modules Send AT+FILT? Receive OK+ Get:[para1 , AT+CON,AT+CONNL 0: When power on, work immediately Default: 0 This command is only used for Central , state of HM -11. Send data to module UART port (not include any AT command and per package must less


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PDF HM-10! cn/Bluetooth40 cn/HMDongle40 DHT11 BC417143 HM-10 BC417143* commands
HM 1211

Abstract: 2758 eprom HM-6758 HM-6758H harris eprom harris hm-6716 HARRIS PACKAGE LOGIC harris 6716 HM-6611 HM-6716
Text: techniques that keep the active (operating) power low, and also give fast access times. The pinout of the HM , €¢ • •• I I I II I I I HM -6611 16 Pin Pkg. 12 1110 9 (MOS) HM -7649 20 Pin Pkg. T4 13 1211 9 8 , ITI (Ü SEMICONDUCTOR PRODUCTS DIVISION A DIVISION OF HARRIS CORPORATION Preview HM -6758 1K , €¢ SUPER LOW POWER STANDBY • LOW POWER OPERATION • FAST ACCESS • INDUSTRY STANDARD PINOUT â , MICROPROCESSOR INTERFACING • WIDE TEMPERATURE RANGE Description The HM -6758 is a CMOS 1024 x 8 ultra-violet


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PDF HM-6758 500/LlW 50mW/MHz 350ns HM-6758 HM-6611 HM-7649 HM 1211 2758 eprom HM-6758H harris eprom harris hm-6716 HARRIS PACKAGE LOGIC harris 6716 HM-6716
2011 - atan2

Abstract: UM0179 A21L 513 orient bc 316 eZ80eval zilog zds 3.68
Text: . Updated the Using the Command Processor section in Appendix D. 115 136 143 243, 359 459 UM014425- 1211 , Zilog Developer Studio II ­ eZ80Acclaim!® User Manual UM014425- 1211 Copyright ©2011 Zilog , other product or service names are the property of their respective owners. UM014425- 1211 Zilog , UM014425- 1211 Zilog Developer Studio II ­ eZ80Acclaim!® User Manual v Table of Contents Revision , . . . . . . . . . . . . Command Processor Toolbar . . . . . . . . . . . . . . . . . . . . . . . . .


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PDF eZ80Acclaim! UM014425-1211 atan2 UM0179 A21L 513 orient bc 316 eZ80eval zilog zds 3.68
5264165

Abstract: HITACHI 5264805 5264805
Text: circuit Power for DQ circuit Ground for DQ circuit No connection V ssQ NC HITACHI 6 HM , burst length is full-page, this command is illegal. HITACHI 13 HM 5264165, HM 5264805 , undefined, execute the mode register set command to set up the mode register. HITACHI 14 HM 5264165 , suspend Clock suspend mode exit Auto-refresh command (REF) Self-refresh entry (SELF) Power down entry n , mode entry: When this command is executed during the IDLE state, the synchronous DRAM enters power down


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PDF HM5264165 HM5264805 HM5264405 576-word 16-bit 152-word 304-word ADE-203-497 5264165 HITACHI 5264805 5264805
0309H

Abstract: No abstract text available
Text: Mask of all “1s”, followed by a VBC HM , S. Instruction: Temporary Command Override (TCO) Binary , ) Vertical cascading and system flag generation require no external logic Memory Array width can be , flag generation system that requires no external logic. The CacheCAM is synchronously controlled by , (Full Input, Input, TTL) (Data/ Command Select, Input, TTL) The /CM input selects whether the input signals on DQ15-DQ0 are data or commands. /CM LOW selects Command cycles and /CM HIGH Data cycles. /EC


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PDF 64-bit 16-bit 16-bit MU9C1640 0309H
ARMv5TEJ

Abstract: MCS1000-EVB-3 SHA-256 Cryptographic Accelerator sha256 SHA-256 MCS1000CB ARM926EJ-S MosChip mcs1000cb "ESP" MCS1000
Text: PCI_AD[31] PCI Address/Data bit 31 I/O Command /byte enable bit 0 W15 I/O Command /byte enable bit 1 PCI_CBE_N[2] U11 I/O Command /byte enable bit 2 PCI_CBE_N[3] Y5 I/O Command /byte enable bit 3 PCI_CLK Y3 I PCI clock PCI_DEVSEL_N 1.1 I/O Y18 , . 1.1 MCS1000 Security Processor Power Pin List Pin Name Location I/O/P Description , Power Pin List Pin Name Location I/O/P Description Thermal Ground K9 P Thermal


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PDF MCS1000 ARM926EJ-S 32-bit 200MHz 10/100Mbps 32-bit, 33MHz 14-Mar-2006 6-Apr-2006 ARMv5TEJ MCS1000-EVB-3 SHA-256 Cryptographic Accelerator sha256 SHA-256 MCS1000CB ARM926EJ-S MosChip mcs1000cb "ESP" MCS1000
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