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Part Manufacturer Description Datasheet Download Buy Part
LTC6905MPS5#TR Linear Technology IC PLL FREQUENCY SYNTHESIZER, PDSO5, PLASTIC, SOT-23, 5 PIN, PLL or Frequency Synthesis Circuit
LTC6905MPS5#TRM Linear Technology IC PLL FREQUENCY SYNTHESIZER, PDSO5, PLASTIC, SOT-23, 5 PIN, PLL or Frequency Synthesis Circuit
LT1310EMSE Linear Technology LT1310 - 1.5A Boost DC/DC Converter with Phase-Locked Loop; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LT1310EMSE#TR Linear Technology LT1310 - 1.5A Boost DC/DC Converter with Phase-Locked Loop; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LTM4601AIV#PBF-ES-WP Linear Technology LTM4601 - 12A DC/DC µModules with PLL, Output Tracking and Margining; Package: LGA; Pins: 133; Temperature: I
LT1310EMSE#PBF Linear Technology LT1310 - 1.5A Boost DC/DC Converter with Phase-Locked Loop; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C

pll 565 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2012 - MO-220-VNND-4

Abstract: adl537x D8P analog devices
Text: suppression Multiple chip synchronization interfaces High performance, low noise PLL clock multiplier Digital , : ADL5370, ADL537x family IQ Modulators with PLL and VCO: ADRF6701, ADRF670x family Clock Drivers: AD9516 , CLK_SEL PLL CONTROL PROGRAMMING REGISTERS SERIAL INPUT/OUTPUT PORT POWER-ON RESET MULTICHIP , CONSUMPTION 2× Mode, fDAC = 491.22 MSPS, IF = 10 MHz, PLL Off 2× Mode, fDAC = 491.22 MSPS, IF = 10 MHz, PLL On 8× Mode, fDAC = 800 MSPS, IF = 10 MHz, PLL Off AVDD33 CVDD18 DVDD18 Power-Down Mode (Register 0x01 =


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PDF 16-Bit, AD9122-EP AD9122-EP ADL537x 52809-A MO-220-VNND-4 72-Lead CP-72-7) MO-220-VNND-4 D8P analog devices
pll 566

Abstract: pll 565 application pll 565 DJZ capacitor CA1310 CA10 EM78565 elan microelectronics 1999 EM78567 ICE567
Text: EM78567/566/ 565 Manual ;= PLL = 0X06 RF = 0X0F , ) 5639977 FAX: (03) 5630118 EM78567/566/ 565 Manual EM78P567/566/ 565 Manual EM78R567 SPEC , capacitor 0.01u to 0.047u with GND . External interrupt 1 EM78567/566/ 565 Manual INT6 INT7 P7 , disable/enable internal pull low. 2 EM78567/566/ 565 Manual ICE TOP VIEW LEFT SIGHT 1 2 JP1 , /AD2 P93/AD1 P92/DAOUT P91 JP3 connection 1999/Jun/14 3 EM78567/566/ 565 Manual ICE


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PDF ICE567 EM78565 EM78566 EM78567 EM78567/566/565 EM78P567/566/565 EM78R567 DELAY22 1999/Jun/14 pll 566 pll 565 application pll 565 DJZ capacitor CA1310 CA10 EM78565 elan microelectronics 1999 EM78567 ICE567
Not Available

Abstract: No abstract text available
Text: Frequency Synthesizer 50Ω KSN-585A-119+ 565 to 585 MHz The Big Deal • Low phase , 565 to 585 MHz for CDMA cellular base station application. The KSN-585A-119+ is packaged in a metal , Surface฀Mount Frequency฀Synthesizer KSN-585A-119+ 50Ω฀฀฀฀฀฀฀ 565 to 585 MHz Features • Integrated VCO + PLL • Low phase noise and spurious • Robust design and construction • Low operating voltage (VCC VCO=+5V, VCC PLL =+5V) • Small size 0.80" x 0.58" x 0.15" CASE STYLE


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PDF KSN-585A-119+ DK801
2010 - pll 565

Abstract: ADF4118 565 application frequency synthesizer 56497
Text: -585A-119+ 565 to 585 MHz Features · Integrated VCO + PLL · Low phase noise and spurious · Robust design and construction · Low operating voltage (VCC VCO=+5V, VCC PLL =+5V) · Small size 0.80" x 0.58" x , Frequency Synthesizer 50 KSN-585A-119+ 565 to 585 MHz The Big Deal · Low phase noise and , Product Overview The KSN-585A-119+ is a Frequency Synthesizer, designed to operate from 565 to 585 MHz , General Description The KSN-585A-119+ is a Frequency Synthesizer, designed to operate from 565 to 585 MHz


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PDF KSN-585A-119+ DK801 pll 565 ADF4118 565 application frequency synthesizer 56497
2002 - F562

Abstract: 565 pin diagram pll 565 ocs4 565 pin dETAILS AF9706 microcontroller mb90560 AF9704 PCS23 pll 565 application
Text: F2MC-16LX MB90560/ 565 Series MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 s DESCRIPTION The MB90560/ 565 series is a general-purpose 16-bit microcontroller designed for industrial, OA, and , for processing long word (32-bit) data. s FEATURES · Clock · Internal oscillator circuit and PLL , , main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation clock multiplied by one to


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PDF DS07-13715-3E 16-bit F2MC-16LX MB90560/565 MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 F2MC-16L F0204 F562 565 pin diagram pll 565 ocs4 565 pin dETAILS AF9706 microcontroller mb90560 AF9704 PCS23 pll 565 application
2002 - 565 PLL

Abstract: DIP-64P-M01 F2MC-16LX FPT-64P-M06 FPT-64P-M09
Text: F2MC-16LX MB90560/ 565 Series MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 s DESCRIPTION The MB90560/ 565 series is a general-purpose 16-bit microcontroller designed for industrial, OA, and , for processing long word (32-bit) data. s FEATURES · Clock · Internal oscillator circuit and PLL , , main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation clock multiplied by one to


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PDF DS07-13715-3E 16-bit F2MC-16LX MB90560/565 MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 F2MC-16L F0204 565 PLL DIP-64P-M01 FPT-64P-M06 FPT-64P-M09
2002 - programmable timer

Abstract: FF201
Text: F2MC-16LX MB90560/ 565 Series MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 s DESCRIPTION The MB90560/ 565 series is a general-purpose 16-bit microcontroller designed for industrial, OA, and , for processing long word (32-bit) data. s FEATURES · Clock · Internal oscillator circuit and PLL , , main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation clock multiplied by one to


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PDF DS07-13715-3E 16-bit F2MC-16LX MB90560/565 MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 F2MC-16L programmable timer FF201
2001 - Not Available

Abstract: No abstract text available
Text: F2MC-16LX MB90560/ 565 Series MB90561A/562A/F562B/V560/567/568/F568 I DESCRIPTION The MB90560/ 565 , €¢ Internal oscillator circuit and PLL clock multiplication circuit • Oscillation clock Clock speed selectable from either the machine clock, main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the , instruction execution time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = × 4, VCC = 5.0 V) â


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PDF DS07-13715-5E 16-bit F2MC-16LX MB90560/565 MB90561A/562A/F562B/V560/567/568/F568 F2MC-16L
2001 - MB90F562BP

Abstract: DS07-13715-5E 565 PLL MB90561APMC MB90F562BPMC F2MC-16LX DIP-64P-M01 pll 565 application MB90F562 MB90560
Text: F2MC-16LX MB90560/ 565 Series MB90561A/562A/F562B/V560/567/568/F568 DESCRIPTION The MB90560/ 565 , oscillator circuit and PLL clock multiplication circuit · Oscillation clock Clock speed selectable from either the machine clock, main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation , execution time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = × 4, VCC = 5.0 V) · Maximum CPU


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PDF DS07-13715-5E 16-bit F2MC-16LX MB90560/565 MB90561A/562A/F562B/V560/567/568/F568 F2MC-16L MB90F562BP DS07-13715-5E 565 PLL MB90561APMC MB90F562BPMC DIP-64P-M01 pll 565 application MB90F562 MB90560
2001 - DIP-64P-M01

Abstract: F2MC-16LX FPT-64P-M06 FPT-64P-M09 DDR4 jedec FTP-64P-M09
Text: F2MC-16LX MB90560/ 565 Series MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 s DESCRIPTION The MB90560/ 565 series is a general-purpose 16-bit microcontroller designed for industrial, OA, and , for processing long word (32-bit) data. s FEATURES · Clock · Internal oscillator circuit and PLL , , main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation clock multiplied by one to


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PDF DS07-13715-2E 16-bit F2MC-16LX MB90560/565 MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 F2MC-16L DIP-64P-M01 FPT-64P-M06 FPT-64P-M09 DDR4 jedec FTP-64P-M09
CH8398

Abstract: CH8398A STG1703 TQD4133 stg170
Text: for "Green PC" applications Anti-sparkle circuitry Dual-programmable 135 MHz PLL clocks On-chip loop filters for PLL clocks Pin compatible to SGS-Thomson STG1703 Low power CMOS technology in 68-pin PLCC 5V , triple 256 x 6-bit palette RAM, and a triple 8-bit 110/135 MHz video DAC. The video clock PLL provides 16 programmable frequencies, and the memory clock PLL provides 8 programmable frequencies. The CH8398A pixel bus , BIOS or driver software can initialize the PLL RAM entries to the desired values. MIX-COLOR® mode


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PDF CH8398A 16-bit ATT20C498 T004133 CH8398 CH8398A STG1703 TQD4133 stg170
7S1 zener diode

Abstract: CH8398 STG1703 gi 9440 diode stg170
Text: features for "Green PC" applications Anti-sparkle circuitry Dual-programmable 135 MHz PLL clocks On-chip loop filters for PLL clocks Pin compatible to SGS-Thomson STG1703 Low power CMOS technology in 68 , -bit palette RAM, and a triple 8-bit 110/135 MHz video DAC. The video clock PLL provides 16 programmable frequencies, and the memory clock PLL provides 8 programmable frequencies. The CH8398 pixel bus is 16 bits , can initialize the PLL RAM entries to the desired values. MIX-COLOR® mode provides the simultaneous


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PDF CH8398 16-bit ATT20C498 CH8398 7S1 zener diode STG1703 gi 9440 diode stg170
gi 9440 diode

Abstract: CH8398 STG1703 7S1 zener diode
Text: "Green PC" applications Anti-sparkle circuitry Dual-programmable 135 MHz PLL clocks On-chip loop filters for PLL clocks Pin compatible to SGS-Thomson STG1703 Low power CMOS technology in 68-pin PLCC 5V , RAM, and a triple 8-bit 110/135 MHz video DAC. The video clock PLL provides 16 programmable frequencies, and the memory clock PLL provides 8 programmable frequencies. The CH8398 pixel bus is 16 bits , can initialize the PLL RAM entries to the desired values. MIX-COLOR® mode provides the simultaneous


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PDF CH8398 16-bit ATT20C498 D0023E gi 9440 diode STG1703 7S1 zener diode
2001 - Not Available

Abstract: No abstract text available
Text: SHEET DS07-13715-5E 16-bit Proprietary Microcontrollers CMOS F2MC-16LX MB90560/ 565 Series MB90561A/562A/F562B/V560/567/568/F568 ■DESCRIPTION The MB90560/ 565 series is a general-purpose 16 , FUJITSU Flexible Microcontroller. ■FEATURES • Clock • Internal oscillator circuit and PLL , clock, main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation clock multiplied by


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PDF
AM DEMODULATOR USING PLL 565

Abstract: NE565 PLL CIRCUIT DIAGRAM OF AM DEMODULATOR USING PLL 565 AM DEMODULATOR USING ne565 circuit diagram ne565 PLL NE565 Signetics NE565 565 PLL pin diagram Signetics 565
Text: Signetics AN 183 Circuit Description of the NE565 PLL Application Note Linear Products CIRCUIT DESCRIPTION OF THE NE565 PLL The 565 is a general purpose PLL designed to operate at frequencies , counter for frequency m ultiplication applications. W ith the 565 , it is also possible to break the toop , utput o f the Schm itt trigger. The com ple te circuit for the 565 is show n in Figure 2. T ransistors Q , connecting them to Pins 6 and 7. The free-running center frequency o f th e 565 is adjusted by m eans o f R


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PDF NE565 AN183 AM DEMODULATOR USING PLL 565 NE565 PLL CIRCUIT DIAGRAM OF AM DEMODULATOR USING PLL 565 AM DEMODULATOR USING ne565 circuit diagram PLL NE565 Signetics NE565 565 PLL pin diagram Signetics 565
PLL IC 565

Abstract: for PLL IC 565 565 PLL pin diagram lock range of 565 PLL IC 0420 LOP pll 565 FO56 Gigabit Logic 16G041-HA CERAMIC LEADLESS CHIP CARRIER
Text: °C operating temperature range 1 Patented, self-acquiring PLL GaAs IC design ■Available in standard frequencies: 100,155.52, 250, 565 , and 622.08 Mbit/s. Custom frequencies available upon request. • PLL , (GBLj GigaBit Logic 16G041-H Low Power, PLL Clock & Data Recovery Circuit 100 to 625 Mbit/s , -H integrates GigaBit's 16G041 PLL clock and data recovery GaAs IC together with a high performance loop filter and other components to realize a complete, 3-terminal (data in, clock and data out) PLL clock


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PDF 16G041-H PLL IC 565 for PLL IC 565 565 PLL pin diagram lock range of 565 PLL IC 0420 LOP pll 565 FO56 Gigabit Logic 16G041-HA CERAMIC LEADLESS CHIP CARRIER
Signetics NE561

Abstract: AM DEMODULATOR USING PLL 565 SIGNETICS PLL ne561 NE561 signetics Signetics NE562 566 vco Signetics NE565 NE561N UA711
Text: of a single external component. Signetics makes three basic classes of single-chip PLL circuits', the general pur pose PLL , the PLL with an added m ultiplier and the PLL tone decoder. The 560N. 562N and 565 , synchronous reception o f radio signals using PLL techniques was de scribed (Ref. 1) in the early thirties , of transistors. This com plexity made PLL techniques im practical or uneconomi cal in the m ajority , frequency-to-voltage transfer character istic. The 561N contains a complete PLL as those above, plus the additional m


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PDF 200Hz. Signetics NE561 AM DEMODULATOR USING PLL 565 SIGNETICS PLL ne561 NE561 signetics Signetics NE562 566 vco Signetics NE565 NE561N UA711
2013 - MO-220-VNND-4

Abstract: No abstract text available
Text: MSPS, IF = 10 MHz, PLL Off fDAC = 491.22 MSPS, IF = 10 MHz, PLL On fDAC = 800 MSPS, IF = 10 MHz, PLL , REFCLK frequency ( PLL mode) 1 GHz ≤ fVCO ≤ 2.1 GHz REFCLK frequency (SYNC mode) See Multichip , 1130 500 550 565 1000 1100 1130 800 900 900 1000 1100 1130 500 550 565 250 275 282.5 , ± 2% 1.9 V ± 2% 125 137.5 141.25 250 275 282.5 500 550 565 1000 1100 1130 250 275 282.5 500 550 565 1000 1100 1130 1000 1100 1130 500 550 565 800 900 900 1000 1100 1130


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PDF 16-BIT, V62/12654 5962-V036-13 V62/12654-01XE AD9122SCPZ-EP MO-220-VNND-4
2004 - Mobile Camera Module

Abstract: 55560-0201 PLL IC 565 565RGB 20 fpc digital camera FPC CONNECTOR 20pin CMOS Camera Module connector mobile camera vga camera pins VS6524P02S
Text: to QVGA, QQVGA and subQCIF ITU-R BT.656-4 YUV (YCbCr) 4:2:2 with embedded syncs, RGB 565 , RGB , syncs, 24 MHz clock Two-wire serial control interface On-chip PLL , 6.5 to 27 MHz clock , as a 2.8 V single supply camera or as a 1.8 V / 2.5 V supply camera. The integrated PLL allows for , MHz typ. (on-chip PLL ) Power consumption VS6524 VGA Mobile Camera Module 8-bit parallel , Camera Controller Video Processor Y Decoder Power-On Reset Readout SCL SDA PLL and


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PDF VS6524 10-bit 10-without Mobile Camera Module 55560-0201 PLL IC 565 565RGB 20 fpc digital camera FPC CONNECTOR 20pin CMOS Camera Module connector mobile camera vga camera pins VS6524P02S
37rgb

Abstract: rgb525 RGB524 pix15
Text: locked loop ( PLL ). The pixel clock generator provides the fundamental "dot" timings; it serves generally , clock; the clock generator simply drives the SYSCLK output of the chip. 2.2 PLL Input 2.2.1 REFCLK The , . As discussed below, following a reset the PLL driving the SYSCLK output is enabled with the start-up , SYSCLK frequency. Also, when the "direct programming" method is used to program the PLL frequencies (see , MHz,. 62 MHz). 2.3 SYSCLK PLL Output The system clock PLL drives the SYSCLK output. Two bits in the


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PDF RGB524 256x8 0x0002, RGB524/RGB528 0x0000) IBM37-RGB524-CF-17C IBM37-RGB524-CF-22C IBM37-RGB524-CF-17C-A IBM37-RGB524-CF-22C-A 37rgb rgb525 pix15
CH8391

Abstract: fs30j Generator control panel 1850 diagram CH8391V
Text: per pixel 1 1 0 5-6-5 bypass, 2 PCLKs per pixel 1 1 1 8-8-8 bypass, 3 PCLKs per pixel CRA: PLL Clock , circuitry • On-chip loop filters for PLL clocks • Low power CMOS technology in 44-pin PLCC • 5 V , palette RAM, and a triple 8-bit 110/135 MHz DAC. The video clock PLL provides 16 programmable frequencies, and the memory clock PLL provides 8 programmable frequencies. Upon power up, the video clock is preset , software initializes the PLL RAM entries to the desired values. CH8391 is fully compatible with VGA


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PDF CH8391 ATT20C490 CH8391Ã 0Q001Ã fs30j Generator control panel 1850 diagram CH8391V
FS10J

Abstract: No abstract text available
Text: . Spec ifies the source of the internal pixel clock. 00 01 10 LC LK inp ut Internal PLL output REFCLK inp , divided Pixel PLL o utp ut is used. SCLK IN VT - Inverts the SCLK out put. DDOT D IV - DDOTCLK divide fac , output sig nal. 000 Pixel PLL out/1 001 Pixel P LL out/2 010 Pixel P LL out/4 011 Pixel P L L out/8 100 , Pixel PLL Enable 0 1 Pixel PLL programming disabled. Pixel PLL program m ing enabled. October 9,1995 , of the 8 p artition s and b it 0 is not used. W ith 16 BPP ( 565 ) indirect color, the palettes are


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PDF RGB624/RGB624DB FS10J
2005 - PLL IC 566

Abstract: PLL IC 565 IC 566 function generator tb31223 application of IC 566 function generator PLL 566 TDA 8223 A pll 565 application s358m datasheet for PLL IC 565
Text: EM78567/566/ 565 8-BIT Microcontroller Product Specification DOC. VERSION 1.4 ELAN , Note: EM78567/566/ 565 Changed the POVD voltage from 1.6V to 2.0V Added 48-pin TQFP package Modified , Specification v EM78567/566/ 565 8-BIT Microcontroller Comment: Page: 1 1 General Description Comment: Page: 1 The EM78567/566/ 565 is an 8-bit RISC type microprocessor with low power, high , memory space. Comment: Page: 1 The EM78567/566/ 565 is an integrated single chip with on-chip


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PDF EM78567/566/565 EM78P567 ICE567 PLL IC 566 PLL IC 565 IC 566 function generator tb31223 application of IC 566 function generator PLL 566 TDA 8223 A pll 565 application s358m datasheet for PLL IC 565
EWM 1000

Abstract: 902950 902750 EWM-900-FDTC-HS pll 564 WM-900-FD pll 564 schematic PLL FSK DEMODULATOR 9600 baud wireless audio transmitter receiver schematic 926100
Text: 565 0 0 926.600 579 4 0 36 904.050 565 1 0 926.650 579 5 0 37 904.100 565 2 0 926.700 579 6 0 38 904.150 565 3 0 926.750 579 7 0 39 904.200 565 4 0 926.800 579 8 0 40 904.250 565 5 0 926.850 579 9 0 41 904.300 565 6 0 926.900 579 10 0 42 904.350 565 7 0 926.950 579 11 0 43 904.400 565 8 0


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PDF EWM-900-FDTC 902-928MHz EWM-900-FDTC EWM 1000 902950 902750 EWM-900-FDTC-HS pll 564 WM-900-FD pll 564 schematic PLL FSK DEMODULATOR 9600 baud wireless audio transmitter receiver schematic 926100
565 phase locked loop

Abstract: ISG2000EU LMX2336
Text: ) FIGURE 1 91-860 MHz DUAL PLL CABLE IN/OUT CLK DATA LD EN TX IN 5-65 MHz RX OUT 15 , DOCSIS COMPLIANT: 100-860 MHz Downstream 5-65 MHz Upstream The ISG2000EU is a complete RF , TX amplifier. The input frequency range spans 5-65 MHz. 4 TXIN- 5 TXIN+ TXIN+ is the non-inverting input to the TX amplifier. The input frequency range spans 5-65 MHz. 6 TXAGC The TXAGC , No. Pin Name Description 11 CLK Clock pin for the dual PLL . High impedance CMOS input


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PDF ISG2000EU ISG2000EU 24-Hour 565 phase locked loop LMX2336
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