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Part Manufacturer Description Datasheet Download Buy Part
LTC6360CDD#PBF Linear Technology LTC6360 - Very Low Noise Single-Ended SAR ADC Driver with True Zero Output; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C
LTC6360IDD#TRPBF Linear Technology LTC6360 - Very Low Noise Single-Ended SAR ADC Driver with True Zero Output; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC6360CDD#TRPBF Linear Technology LTC6360 - Very Low Noise Single-Ended SAR ADC Driver with True Zero Output; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C
LTC6360IMS8E#PBF Linear Technology LTC6360 - Very Low Noise Single-Ended SAR ADC Driver with True Zero Output; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C
LTC6360IMS8E#TRPBF Linear Technology LTC6360 - Very Low Noise Single-Ended SAR ADC Driver with True Zero Output; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C
LTC6360CMS8E#PBF Linear Technology LTC6360 - Very Low Noise Single-Ended SAR ADC Driver with True Zero Output; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C

plc shift register with latch outputs Datasheets Context Search

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bmw lvds cable

Abstract: TN1037 BLM31b601s plc shift register with latch outputs verilog code for lvds driver vhdl code for lvds driver BLM11B601SPB but prone bmw
Text: shift register brings data into the register from the PLC array. The parallel low-speed data from the , Description Input signal from associated pad via PIC. OUTD0 Input to shift register from PLC routing during output mode. OUTD1 Input to shift register from PLC routing during output mode. OUTD2 Input to shift register from PLC routing during output mode. OUTD3 Input to shift register from , 200 Mbits/s. · 420 MHz I/O performance to support UTOPIA 4 standards. · Input/output shift register


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PDF TN1036 LVCMOS18, bmw lvds cable TN1037 BLM31b601s plc shift register with latch outputs verilog code for lvds driver vhdl code for lvds driver BLM11B601SPB but prone bmw
R14C17

Abstract: R16C17
Text: from latch /FF outputs to the I/O pads. This is done for each PLC that is adjacent to a PIC. The , example, the latches/FFs can be used as a 4-bit shift register , and the LUT can be used to detect when a , functions, fO and f3, are also usable simultaneously with the logic gate outputs . The output of the , can be routed out on the o[4:0] PFU outputs or to the latch /FFs d[3:0] inputs. To increase memory , , the latch /FF input can also be tied to logic 0, which is the default. The four latch /FF outputs , q[3


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PDF ATT2T15 ATT2T15 ATT2C15 005002b R14C17 R16C17
2007 - MAX6922AQH D

Abstract: 68 20L Nippon capacitors
Text: and operated together. The output latch is transparent to the shift register outputs when LOAD is high , data from the shift register to the output latch when LOAD is high (transparent latch ), and latches the , , then the data shifted into the shift register at DIN appears at the OUT0 to OUTn-1 outputs . CLK and DIN , clocked out of the internal shift register to DOUT (MAX6932) on CLK's falling edge. For the MAX6933 , Input. Data is loaded into the internal shift register on CLK's rising edge. On CLK's falling edge, data


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PDF 32-Output, MAX6922/MAX6932/MAX6933/MAX6934 MAX6850 MAX6853. MAX6922/MAX6934 MAX6932 MAX6933 Q44-1* 21-0144F T4477-3* MAX6922AQH D 68 20L Nippon capacitors
T3168

Abstract: ATT ORCA fpga gc 5.5V .22f 207 525s oa259 ATT ORCA fpga architecture OA154 ATT1C05 op3120 D1313
Text: and next state of a latch / FF, build a 4-bit shift register , etc. Each of the outputs can drive any , or Raast 3. Latch /FF with Front-End Sslset Figure 12. Latch /FF Set/Reset Configurations PLC Routing , out of the PLC . The eight signals are the four LUT outputs (fO, f1,12, f3) and the four latch /FF , a PLC in the second row and third column is BC. PICs are indicated similarly, with PT (top) and PB , independently. For example, the latches/FFs can be used as a 4-bit shift register , and the LUT can be used to


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PDF QDS002fci 16-bit 84-Pln 132-Pin 208-Pin 240-Pin 304-PJn 225-Pm 280-Pin 364-Pin T3168 ATT ORCA fpga gc 5.5V .22f 207 525s oa259 ATT ORCA fpga architecture OA154 ATT1C05 op3120 D1313
Not Available

Abstract: No abstract text available
Text: paths from latch /FF outputs to the I/O pads. This is done for each PLC that is adjacent to a PIC , independently. For example, the latches/FFs can be used as a 4-bit shift register , and the LUT can be used to , ORCA Series Field-Programmable Gate Arrays Programmable Logic Cells ( PLC ) (continued) Each latch , /FF dO and latch /FF d3 inputs, or directly to the outputs oO and o3. The use of the LUT for two , , are also usable simultaneously with the logic gate outputs . ORCA Series Field-Programmable Gate


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PDF 16-bit DS92-099FPGA
ATT ORCA fpga

Abstract: ATT ORCA fpga architecture
Text: and next state of a latch /FF, build a 4-bit shift register , etc. Each of the outputs can drive any , the PLC . The eight signals are the four LUT outputs (fO, f1, f2, f3) and the four latch /FF outputs , latches/FFs can be used as a 4-bit shift register , and the LUT can be used to detect when a register has , routed to the latch /FF dO and latch /FF d3 inputs, or directly to the outputs oO and o3. The use of the , five-input combinatorial functions, fO and f3, are also usable simultaneously with the logic gate outputs


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PDF ATT1C03, ATT1C05, ATT1C07, ATT1C09) 16-bit DS95-084FPGA DS94-131FPGA) ATT ORCA fpga ATT ORCA fpga architecture
Not Available

Abstract: No abstract text available
Text: , read the present state and next state of a latch /FF, build a 4-bit shift register , etc. Each of the , -bit shift register , and the LUT can be used to detect when a register has a particular pattern in it , the latch /FF dO and latch /FF d3 inputs, or directly to the outputs oO and o3. The use of the LUT for , with the logic gate outputs . The output of the multiplexer is: f1 = (HLUTA x cO) + (HLUTB x cO) f1 = , on the o[4:0] PFU outputs or to the latch /FFs d[3:0] inputs. To increase memory address locations


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PDF arch1995 ATT1C03, ATT1C05, ATT1C07, ATT1C09) forATT1C09) 16-bit 84-Pin 100-Pin ATT1C03
1986 - AMD 2903

Abstract: AMD 2903 bit slice plc shift register with latch outputs MCR 100-6 1775-L1 Allen Bradley PLC Allen-Bradley PLC dc input bit-slice AMD 2903 instruction set
Text: Move status Shift Register X X X X X Logical Logical AND Logical AND with files Logical , power and communicates with other modules through the PLC -3 chassis backplane. Two main processor modules are available for your PLC -3 system: cat. no. 1775-L1 cat. no. 1775-L2 1 Product Data , ) Product Data Description The main processor module is used in PLC -3 programmable controller systems , quickly determines if outputs are: G true G false complete control over program execution program


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PDF 1775-L1, 1775-L1 1775-L2 PN955096-55 AMD 2903 AMD 2903 bit slice plc shift register with latch outputs MCR 100-6 1775-L1 Allen Bradley PLC Allen-Bradley PLC dc input bit-slice AMD 2903 instruction set
1995 - FX0-14MR-ES

Abstract: mitsubishi plc manual mitsubishi fx plc programming cable pin wiring di FX0-30MR-ES FX0-30MR-DS M8014 mitsubishi pin out plc to pc interface FX0-20MR-DS mitsubishi FX series instruction list mitsubishi plc FX SERIES
Text: 017-159 1 Specifying a PLC 1.1 What is a PLC ? Outputs Control PLC Inputs Actuators , common questions a user asks once he is committed to using a PLC . q The number of inputs and outputs (I , FX0 MEDOC protocol convertor with integral lead For 14 I/O FX0 Micro PLC For 20 I/O FX0 Micro PLC , relays x, y Max. no. of inputs and outputs 512 256 120 30 M General/ Latch 2048 , . Available with 14, 20 or 30 inputs and outputs . Each model is stand alone and powered by most world ac


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1995 - mitsubishi fx plc programming cable pin wiring di

Abstract: FX0-14MR-ES mitsubishi pin out plc to pc interface FX0-30MR-ES FX0-20MR-ES mitsubishi plc FX SERIES mitsubishi plc FX SERIES connection cable plc mitsubishi q series FX0-14MR mitsubishi plc cable fx series
Text: 232-4645 1 Specifying a PLC 1.1 What is a PLC ? Outputs Control PLC Inputs Actuators , common questions a user asks once he is committed to using a PLC . q The number of inputs and outputs (I , FX0 MEDOC protocol convertor with integral lead For 14 I/O FX0 Micro PLC For 20 I/O FX0 Micro PLC , relays x, y Max. no. of inputs and outputs 512 256 120 30 M General/ Latch 2048 , . Available with 14, 20 or 30 inputs and outputs . Each model is stand alone and powered by most world ac


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1998 - M8014

Abstract: d8042 FX0-14MR-ES D8041 FX-10DU-E FX0-20MR-ES mitsubishi plc manual M8012 FX0-20MT-D FX0-20MT
Text: problems occur when installed. Information- Inputs- Outputs - 1.2 Why use a PLC ? Flexibility q , is committed to using a PLC . q The number of inputs and outputs (I/O) required? q Are the I/O digital , FX0 MEDOC software only FX0 MEDOC protocol convertor with integral lead For 14 I/O FX0 Micro PLC For , . of outputs Max. no. of inputs and outputs General/ Latch Link Special Non-battery backed Battery , 24Vdc supply to power source inputs. The relay or transistor outputs are standard FX PLC specification


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PDF M8065 M8067 M8014 d8042 FX0-14MR-ES D8041 FX-10DU-E FX0-20MR-ES mitsubishi plc manual M8012 FX0-20MT-D FX0-20MT
1C05

Abstract: ATT ORCA fpga architecture PX110 C05 jj MXM pin assignment 2843B 1C03 1C07 1C09 PBD 1.27
Text: present state and next state of a latch /FF, build a 4-bit shift register , etc. Each of the outputs can , direct paths from latch /FF outputs to the I/O pads. This is done for each PLC that is adjacent to a PIC , :0]. The results are routed to the latch /FF dO and latch /FF d3 inputs, or directly to the outputs oO , usable simultaneously with the logic gate outputs . The output of the multiplexer is: f 1 = (HLUTA x CO , routed out on the o[4:0] PFU outputs or to the latch /FFs d[3:0] inputs. To increase memory address


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PDF ATT1C03, ATT1C05, ATT1C07, ATT1C09) forATT1C09) 16-bit 84-Pin 100-Pin 132-Pin 144-Pin 1C05 ATT ORCA fpga architecture PX110 C05 jj MXM pin assignment 2843B 1C03 1C07 1C09 PBD 1.27
2004 - TPA6116

Abstract: headphone op amp speaker speaker 8Ohm wm9712l LM4895 WM8750L EH11
Text: must be configured so that the same signal is present at both LOUT2 and ROUT2 outputs but with the , operating with a range of supply voltages, particularly relevant here are the SPKVDD, AVDD and HPVDD supply , plc www.wolfsonmicro.com January 2004, Rev 1.2 Copyright 2004 Wolfson Microelectronics plc WAN_0141 WM8750/51L SETUP LOUT2/ROUT2 REGISTER SETTINGS The LOUT2 and ROUT2 output pins are , ­(-R) = L+R]. REGISTER ADDRESS R40 (28h) LOUT2 Volume BIT LABEL DEFAULT DESCRIPTION


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PDF WM8750/51L WM9711/12L TPA6116 headphone op amp speaker speaker 8Ohm wm9712l LM4895 WM8750L EH11
1C07

Abstract: plj1 ATT ORCA fpga architecture ATT ORCA fpga HC s304 1C09 ic all pics IC PIN CONFIGURATION OF 74 47 1C05 att1765
Text: latch /FF, build a 4-bit shift register , etc. Each of the outputs can drive any number of the five PFU , /FFs, there are direct paths from latch /FF outputs to the I/O pads. This is done for each PLC that is , :0]. The results are routed to the latch /FF dO and latch /FF d3 inputs, or directly to the outputs oO , with the logic gate outputs . The output of the multiplexer is: f 1 = (HLUTA x CO) + (HLUTB x cO) f1 = , ., f[3:0], or the direct data input, wd[3:0]. The four latch /FF outputs q[3:0] can be arbitrarily


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PDF ATT1C03, ATT1C05, ATT1C07, ATT1C09) forATT1C09) 16-bit 84-Pin 100-Pin 132-Pin 144-Pin 1C07 plj1 ATT ORCA fpga architecture ATT ORCA fpga HC s304 1C09 ic all pics IC PIN CONFIGURATION OF 74 47 1C05 att1765
2007 - vfd control using plc

Abstract: MAX685x Nippon capacitors
Text: and operated together. The output latch is transparent to the shift register outputs when LOAD is high , data from the shift register to the output latch when LOAD is high (transparent latch ), and latches the , , then the data shifted into the shift register at DIN appears at the OUT0 to OUTn-1 outputs . CLK and DIN , clocked out of the internal shift register to DOUT (MAX6932) on CLK's falling edge. For the MAX6933 , Input. Data is loaded into the internal shift register on CLK's rising edge. On CLK's falling edge, data


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PDF 32-Output, MAX6922/MAX6932/MAX6933/MAX6934 MAX6850 MAX6853. MAX6922/MAX6934 MAX6932 MAX6933 21-0049D MAX6922AQH vfd control using plc MAX685x Nippon capacitors
2003 - TPA6116

Abstract: wm9712 speaker speaker 8Ohm wm9712l LM4895 MAX4167 WM8750 WM8750L
Text: 500mW but 0.1% at 180mW output. WOLFSON MICROELECTRONICS plc www.wolfsonmicro.com September 2003, Rev 1.1 Copyright 2003 Wolfson Microelectronics plc WAN_0141 WM8750 SETUP LOUT2/ROUT2 REGISTER , LOUT2 and ROUT2 outputs but with the ROUT2 output inverted as set by the INV bit in Table 2. Maximum , voltages. The WM8750L and WM9712L are capable of operating with a range of supply voltages, particularly , right channel are mixed to mono in the speaker [L­(-R) = L+R]. REGISTER ADDRESS R40 (28h) LOUT2


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PDF WM8750 WM9712 TPA6116 speaker speaker 8Ohm wm9712l LM4895 MAX4167 WM8750L
1994 - mitsubishi fx plc programming cable pin wiring di

Abstract: FX0-14MR-ES FX-10du-E FX0-30MR-ES M8014 mitsubishi plc FX SERIES connection cable mitsubishi pin out plc to pc interface FX0-30MR-DS mitsubishi FX series instruction list FX0-20MR-ES
Text: devices 5.6 Applied functions D17799 1 Specifying a PLC l PLCs are increasingly being used with their standard hardware and software instead of dedicated 1.1 What is a PLC ? computers with unique programs , PLC s o s s r l l Most PLCs are manufactured by well known i t r o y o a o Inputs Outputs t a r , quickly and cost effectively. with a product correctly specified for the application, l A PLC can be , number of inputs and outputs (I/O) required? l Are the I/O digital or analogue? Appropriate PLC l Are


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PDF D17799 M8061 D8061 M8064 D8064 M8065 D8065 M8066 D8066 M8067 mitsubishi fx plc programming cable pin wiring di FX0-14MR-ES FX-10du-E FX0-30MR-ES M8014 mitsubishi plc FX SERIES connection cable mitsubishi pin out plc to pc interface FX0-30MR-DS mitsubishi FX series instruction list FX0-20MR-ES
probug

Abstract: MC68701 MC6801 mc68701 probug MC68701L MC68A701L MC68701L-1 MC68701CL-1 MC68701CL AN/mc68701 probug
Text: bit is controlled by the state of PLC . Associated with the EPROM are an 8-bit data latch and a 16 , address latch is controlled by the PLC bit. A description of the RAM/EPROM Control Register follows , Register for Port 4 has been written with "1's" in the appropriate bits. These address lines will assert "1's" until made outputs by writing the Data Direction Register . MC68701 FIGURE 16 - MC68701 MEMORY , written with "1 's" in the appropriate bits. These address lines will assert "1's" until made outputs by


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PDF MC68701 M6800 MC6801/03 A13281-3 C198S4 probug MC6801 mc68701 probug MC68701L MC68A701L MC68701L-1 MC68701CL-1 MC68701CL AN/mc68701 probug
probug

Abstract: mc68701 probug AN/mc68701 probug MC68B701S MC68701 MC6801 MC68701S pdd 3010 application circuits for MC68701 7812 cc
Text: will not contain addresses until the Data Direction Register for Port 4 has been written with "Vs" in , the Data Direction Register for Port 4 has been written with "1 s" in the appropriate bits These address lines will assert "1 s" until made outputs by writing the Data Direction Register . 1) MCU read of , associated with IS3 are controlled by the Port 3 Control and Status Register and are discussed in the Port 3 , by an F53 negative edge. The latch is transparent after a read of Port 3 Data Register . LATCH ENABLE


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PDF MC68701 MC68701 M6800 MC6801/MC6803 MC68701S MC68701CS MC68701CL probug mc68701 probug AN/mc68701 probug MC68B701S MC6801 pdd 3010 application circuits for MC68701 7812 cc
2013 - AT01084

Abstract: No abstract text available
Text: Description Lookup table including truth table register and decoder Delay element, created with a programmable , LUT0: PORTC or PORTD (see PORTSEL in CTRLA register ). Important remark: The port selected with PORTSEL , CTRLA register ). Important remark: This port is common for inputs and outputs and for LUT0 and LUT1. Pin , . Register configuration: To use LUT0 and LUT1 as separated LUT with two inputs and one output, the user has , to output with ACEVOUT register . 3.5.3 Event system as LUT input Event system is proposed as


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PDF AT01084: 16-bit AT01084
6N0 953 235

Abstract: No abstract text available
Text: , allowing, for instance, a comparator function in the LUTs simultaneously with a shift register in the FFs , , or longer arithmetic functions, with the new option to register the PFU carry-out. ■New , . The PICs provide device inputs and outputs and can be used to register signals and to perform input , , and local set/reset. The SLIC is connected to PLC routing resources and to the outputs of the PFU , PLC array can be routed to each output flip-flop, and logic can be associated with each I/O pad. The


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PDF 16-bit 208-Pin 240-Pin 256-Pin 352-Pin 432-Pin 600-Pin PS208 PS240 BA256 6N0 953 235
BR16 switch transistors

Abstract: Lucent wifi PB11D R2C15 PTC 8750 R5C13 5s805 W847 R12G5
Text: , a comparator function in the LUTs simultaneously with a shift register in the FFs. 8 K4_1 K4_2 K4 , arithmetic functions, with the new option to register the PFU carry-out. New soft-wired LUTs (SWL) allow , . Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC . Implemented in five , other global input is maintained. On the output side of each PIO, two outputs from the PLC array can be , latched/ registered outputs (one from each latch /FF), a carry out (COUT), and a registered carry-out


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PDF 16-bit p65900 DS97-282FPGA BR16 switch transistors Lucent wifi PB11D R2C15 PTC 8750 R5C13 5s805 W847 R12G5
1995 - F1-40MR-ES

Abstract: plc based phase sequence indication and controlling cable plc mitsubishi f1-30mr mitsubishi f1-60mr mitsubishi cable sc03 F1-20MR-ES F1-60MR-ES F2-20GF1 F1-12MR-ES F1 60mr programming manual
Text: for use with F1 PLC 5.7 F1-F2 series programming manual 6 Programming 6.1 Basics 6.2 Memory map F1 , PLC range, which is no longer available, but many of these items may be used with either items from , Opto-isolated inputs and relay outputs q Screw terminal connections, with the 40 and 60 I/O versions having , -60ER-ES 318-294 318-301 318-317 318-323 The following F2 PLC system components are compatible with the F1 , panel is compatible with all RS PLC base units (F1 and F2). The unit offers a large LCD display area


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1997 - F1-40MR-ES

Abstract: F1 60mr programming manual F2-20GF1 mitsubishi f1-60mr mitsubishi cable sc03 fx 20mr-es mitsubishi plc manual mitsubishi plc F1-30MR-es plc based phase sequence indication and controlling F-20P-CAB
Text: for use with F1 PLC 5.7 F1-F2 series programming manual 6 Programming 6.1 Basics 6.2 Memory map F1 , PLC range, which is no longer available, but many of these items may be used with either items from , Opto-isolated inputs and relay outputs q Screw terminal connections, with the 40 and 60 I/O versions having , -60ER-ES 318-294 318-301 318-317 318-323 The following F2 PLC system components are compatible with the F1 , panel is compatible with all RS PLC base units (F1 and F2). The unit offers a large LCD display area


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2003 - PB21D

Abstract: No abstract text available
Text: simultaneously with a shift register in the FFs. Programmable Logic Cells (continued) The LUTs can be , used independently or with arithmetic functions. The PFU is the main logic element of the PLC , PFU, captured at the LUTs associated latch /FF, or multiplexed with the adjacent F4 LUT output using , slew-limited). - Fast-capture input latch and input flip-flop (FF)/ latch for reduced input setup time and zero hold time. - Fast open-drain drive capability. - Capability to register 3-state enable signal. -


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PDF OR4E04 OR4E06 PB21D
Supplyframe Tracking Pixel