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LT1017MJ8/883 Linear Technology LT1017 - Micropower Dual Comparator; Package: CERDIP; Pins: 8; Temperature: Military
LM108AJ8 Linear Technology LM108A - Operational Amplifiers; Package: CERDIP; Pins: 8; Temperature: Military
LT1175CDWF#MILDWF Linear Technology LT1175 - 500mA Negative Low Dropout Micropower Regulator; Pins: 5
LT1018MJ8/883 Linear Technology LT1018 - Micropower Dual Comparator; Package: CERDIP; Pins: 8; Temperature: Military
LTC1041MJ8/883 Linear Technology LTC1041 - BANG-BANG Controller; Package: CERDIP; Pins: 8; Temperature: Military
LTC2905HDDB#TRMPBF Linear Technology LTC2905 - Precision Dual Supply Monitor with Pin-Selectable Thresholds; Package: DFN; Pins: 8; Temperature Range: -40°C to 125°C

pin diagram ic 7420 Datasheets Context Search

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2003 - pin diagram ic 7420

Abstract: S-8521F48mc-bqh-t2 toyota IC regulator built TM6201
Text: IC direction in tape specifications Product code *2 *1 Rev. 7.4_20 Package code MC: SOT , Rev. 7.4_20 Table 3 Pin No. 1 Pin name ON / OFF Pin description Shutdown pin "H": Normal , external transistor IC power supply pin Figure 3 Absolute Maximum Ratings Table 4 (Ta=25 °C , value than that of R1 and R2 in the IC . 22 Seiko Instruments Inc. Rev. 7.4_20 PWM CONTROL , Rev. 7.4_20 PWM CONTROL, PWM/PFM SWITCHING CONTROL STEP-DOWN SWITCHING REGULATOR CONTROLLERS S


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PDF S-8520/8521 S-8520 S-8521 pin diagram ic 7420 S-8521F48mc-bqh-t2 toyota IC regulator built TM6201
2003 - toyota IC regulator built

Abstract: pin diagram ic 7420
Text: , PWM/PFM SWITCHING CONTROL STEP-DOWN SWITCHING REGULATOR CONTROLLERS Rev. 7.4_20 S-8520/8521 Series Pin , for external transistor IC power supply pin Figure 3 Absolute Maximum Ratings Table 4 (Ta , CONTROLLERS Rev. 7.4_20 S-8520/8521 Series 5-2. Bipolar PNP type Figure 10 shows a sample circuit diagram , SWITCHING REGULATOR CONTROLLERS Rev. 7.4_20 S-8520/8521 Series 3. EXT pin output current "H" (IEXTH)-Input , Rev. 7.4_20 PWM CONTROL, PWM/PFM SWITCHING CONTROL STEP-DOWN SWITCHING REGULATOR CONTROLLERS S


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PDF S-8520/8521 S-8520 S-8521 toyota IC regulator built pin diagram ic 7420
pin diagram ic 7420

Abstract: 7420 ic details pin diagram of ic 7420 IC 7420 7420 ic
Text: MIL-STD-883 B lock Diagram Pin Definition A0-A16 OE WE4 WE3 WE2 WE1 © _© D 8 WE2 @ > © D 9 , 1.74V M o s a ic S e m ic o n d u c to r, In c ., 7420 C a r r o l l R d . S u ite 300, S an D ie g o , M o s a ic S e m ic o n d u c to r , In c ., 7420 C a r r o l l Rd. S u ite 300, S a n D ie g o , . Write Cycle No.1 Timing Waveform twc M o s a ic S e m ic o n d u c to r, In c ., 7420 C arroll R d , Consumption Memory Type M o s a ic S e m ic o n d u c to r, In c ., 7420 C a r r o l l Rd. S u ite 300, S


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PDF PUMA2S4000 100ns 120ns. MIL-STD-883. 2S4000-70/85/10/12 2S4000-7 2S4000LMB-10 S4000 pin diagram ic 7420 7420 ic details pin diagram of ic 7420 IC 7420 7420 ic
pin diagram ic 7420

Abstract: pin diagram of ic 7420 IC 7420 7420 TTL diagram 7420 ic TTL 7420 cmos 7420 pinout 7420
Text: =5V±10% Output Load i/o Pin ° 166n ? vW * O 1-76V Mosaic Semiconductor, Inc., 7420 Carroll Rd , processed in accordance with MIL-STD-883. Pin Definition W AO A1 A2 A3 A4 1 C 2 c 3 c 4 c 5 CS , A14 23 A13 22 A12 21 A11 20 D A10 19 NC c c 17 c 18 Pin Functions A0-A18 D0-7 CS OE WE NC Vcc , any pin relative to Vss Power Dissipation Storage Temperature vT PT " ^ " s T G -0.5V to +7 1 -55 , Semiconductor, Inc., 7420 Carroll Rd. Suite 300, San Diego, CA 92121 b35337c ì GG2712 71D z > 10


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PDF MSM8512J MSM8128 MIL-STD-883. MSM8512J-015/020/025 JEDEC1014 8512J B-015 0D0271Ö pin diagram ic 7420 pin diagram of ic 7420 IC 7420 7420 TTL diagram 7420 ic TTL 7420 cmos 7420 pinout 7420
Not Available

Abstract: No abstract text available
Text: with MIL-STD-883 Block Diagram Pin Definition (see page 12 for Block Diagram of option /A ) (seepage 12 for Pin Definition of option/A) n A 0-A 14 9 8 7 n 6 n 5 n 4 n 3 , , inc. Description ThePUMA67E1001/AisalMbitCMOS EEPROM module in a JEDEC 68 pin J leaded Ceramic , 32 33 34 35 36 37 38 39 40 41 42 43 U U U U U U T ] ' L 1 U U U U U U L J >< <<< Pin , Condition ^INl ^IN2 VIN -0V Cqut v OT U =ov v,N =ov Mosaic Semiconductor, Inc., 7420


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PDF PUMA67E1001/A-90/12 ThePUMA67E1001/AisalMbitCMOS of90and MIL-STD-883orD0 MIL-STD-883 32Kx32 as64Kx 16and 128Kx8 PUMA67
2005 - TTL 7420

Abstract: No abstract text available
Text: Optoway GBB- 7420 * GBB- 7420 1310 nm TX / 1550 nm RX , 5V / 1250 Mbps 1-Fiber Single-Mode WDM Gigabit Interface , ) * FEATURES DESCRIPTION l l l l The GBS- 7420 series single-mode optical transceivers meet the , (IDP) mounted in an optical header and a limiting post-amplifier IC . A PECL input / output logic interface is used. TTL RX-LOS output simplifies interface to external circuitry. A 20- pin SCA-2 host


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PDF GBB-7420 GBS-7420 using5979737 TTL 7420
pin diagram ic 7420

Abstract: IC 7420 pin diagram of ic 7420 7420 ic
Text: L-STD-883 or w ith BS9400 · Data Retention Tim e of lOOyears. requirements. Block Diagram Pin , levels: 1.5V * O utput load: See Diagram *V C C =5V ±10% _< Ô II O < O utput Test Load I/O Pin , ic packages including th e space saving VILTM .T h e device featu res · Byte and Page W rite (256 , 27 26 25 24 H 23 22 21 3 20 19 3 18 17 Pin Functions Package D e ta ils - see page 1 0 & 11 for d im en sion draw ings. Pin Count Description 32 0.1" V ertica l-in -L ln e (VILTM) Package


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PDF MEM8128-12/ 150ns, 170ns, 200ns, 250ns. MEM8128VMB-15 120ns 150ns 170ns MIL-STD-883 pin diagram ic 7420 IC 7420 pin diagram of ic 7420 7420 ic
ic 7420

Abstract: No abstract text available
Text: = 68 pin "J" Leaded PLCC M osaic Sem iconductor, Inc., 7420 Carroll Rd. Suite 300, San Diego , organised as 128K x 32 in a JEDEC 68 pin surface mount PLCC, available with access times of 20, 25, 35 , with 2V data retention mode is available._ Block Diagram • Very Fast , €¢ Single 5V±10% Power supply. 2.86 W (max) 44 mW (max) Pin Definition A0-A16 z < < < < < < l , U U U U U U U U U U I Pin Functions Address inputs A O - A16 Data Input/Output DO - D31


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PDF 68S4000-020/025/35/45 PUMA68S4000 128Kx8 h3S337 68S4000LM B-020 STD-883 S4000 ic 7420
pin configuration ic 7420

Abstract: PUMAS 7420 ic details pinout 7420 pin diagram ic 7420 4007A
Text: Endurance of 104 Erase/Write Cycles and Data Retention Time of lOOyears. Block Diagram (see page 11 for Block Diagram of A version) Pin Definition (see page 11 for A version Pinout) O o i - w to Tt Z , ISSUE 4.1 :Junel996 Pin Oefinifion version A' Block Diagram version A I< * >Q mi.v. 2 W ^ to n , U L I L I U U U U U U U U L J U U U L J I *- O J CO ''f io < 0 » * r ~ IL L I IC M O U O O O Q O *! < < < < < <|i3lolo z z z z z § z Pin Functions A0~16 Address Inputs CS1


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PDF PUMA67E4007/A 16or32 250ns. 100years. MIL-STD-883. 128Kx PUMA67E4007/9 7E4007-15/17/20/25 Junel996 67E4007AMB-15 pin configuration ic 7420 PUMAS 7420 ic details pinout 7420 pin diagram ic 7420 4007A
Not Available

Abstract: No abstract text available
Text: accordancewith MIL-STD-883., Block Diagram Pin Definition (see page 11 for Block Diagram of option /A , . 0.64 (0.025) min o c ö o h* in ö C O CI N Block Diagram version /A Pin , module in a JEDEC 68 pin J leaded Ceramic Surface Mount Substrate. Accesstimes of 120,150 , o UU U Ü Û O 8 £ 2 ffl » in œr z > < < < < < < 8 ° ‘0 Z Z Z 2 Z <3 z Pin Functions AO , 67E4001A version only. Mosaic Semiconductor, Inc., 7420 Carroll Rd. Suite 300, San Diego, CA 92121 â


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PDF 128Kx PUMA67E4001/A-12/15/17/20 304bitCMOS ThePUMA67E4001/Aisa4MbitCMOS 170and200nsareavailable 100years. PUMA67E4001/A-15/17/20 67E4001AMB-15E MIL-STD-883 128Kx32
pin diagram ic 7420

Abstract: 7420 ic
Text: Module in a 6 8 pin JLCC package, with access times of 90,120 and 150 ns. The oyput width is configurable , be screened in accordance with MIL-STD-883. / ; Pin Definition n /^ 9 DO e 10 D 1 c 11 D 2 C 12 D 3 , bit wide. · Operating Power 880/451/237 mW (max). Block Diagram lo o lo I , I L L ) |CM h» C O Q Q Ü > < < < < < < o fo < < u u Ûo z z o Pin Functions A0-A18 CE1-4 OE GND , i Voltage on any pin w.r.t. Gnd Supply Voltage(2 ) Voltage on A9 w.r.t. G nd (3 ) StorageTemperature


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PDF PUMA67F16006 67F16006 b3S337c F16006MB-90 MIL-STD-883 512Kx 1Mx16and pin diagram ic 7420 7420 ic
Not Available

Abstract: No abstract text available
Text: : See Load Diagram I/O Pin 166ft o- <> v W — o — 1.76V b 30pF *V c =5V±10% , Semiconductor, Inc., 7420 Carroll Rd. Suite 300, San Diego, CA 92121 baSBiTT QÜ0237Ô TÔT = 32 pin , Pinout. May be screened in accordance with MIL-STD-883. Block Diagram ^ ^ P in Definition A4 A5 , / Pin Functions A0-A16 DO-7 CS OE WE NC Vcc GND 1 ,3 5 3 3 7 ^ A A I I II Œ Pin , OPERATING CONDITIONS Absolute Maximum Ratings(1 > Voltage on any pin relative to Vss(2 ) VT Power


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PDF 128Kx MSM8128X-020/25/35 MSM8128X MIL-STD-883 MSM8128SXLMB-35 MIL-STD-883
7420 ic details

Abstract: pin diagram ic 7420 UV-EPROM A0-A12, D0-D7 ER410 TI645 EPROM128KX8 pinout 7420 2758 eprom
Text: configurable as x8) PUM A2 = Ceram ic 66 Pin Grid Array ModuleType Mosaic Semiconductor, Inc., 7420 , Data A cce sstim e so f8 5 to 15 0n s. Completely Static Operation Pin Definition Block Diagram Q , respectively; for example, pin 41, allocated A8/A9, connects to A8 on the EPROMs, and to A9 on the SRAMs. Pin Functions A0-A16 CS1-4 W E3-4 Vpp GND Address Inputs Chip Selects Write Enables ProgrammingVoltage , SRAM part. Absolute Maximum Ratings (i) Temperature UnderBias Storage Te m peratu re Voltage on Any Pin


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PDF PUMA2US2500 128K8 16bitwide 250ns 150ns US2500 0US2500 OCTOBER1995 170ns MIL-STD-883 7420 ic details pin diagram ic 7420 UV-EPROM A0-A12, D0-D7 ER410 TI645 EPROM128KX8 pinout 7420 2758 eprom
7420 ic details

Abstract: pin diagram ic 7420 IC 7420 function ic 4026 IC 4026 pin diagram 7420 ic
Text: Diagram DO-* D7 Pin Definitions 8 - Y ADDRESS 1 I H DECODE SUFFER X ADDRESS DEOOOr E jUF+FR I no , Pin Count 28 Description 0.1" Vertical-in-Llne (VILTM) Package Type V Pin Functions A0-A14 Address , Absolute Maximum Ratings Voltage on any pin relative to GND Voltage on OE and A9 relative to GND All output , Supply Current IC C 1 Standby Current (TTL) ^ S B 1 Standby Current -L Version lS B 2 Output Voltage v 0L , 12 Capacitance calculated, not measured. M osaic Sem iconductor, Inc., 7420 Carroll Rd. Suite


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PDF MEM832 MILSTD-883. MEM832-20/25 b353371 MEM832VLMB-20 0002b0? 7420 ic details pin diagram ic 7420 IC 7420 function ic 4026 IC 4026 pin diagram 7420 ic
2005 - IC 7400 SERIES list

Abstract: IC 7400 diagram and truth table pin configuration ic 7410 IC 7410 truth table pin diagram of ic 7410 pin configuration of ic 7410 tPHL 7400 ACML-7410 pin diagram ic 7420 working of ic 7493
Text: ACML-7400, ACML-7410 and ACML- 7420 3.3 V/5 V 100 MBd High Speed CMOS Digital Isolator Data , lead-free product Description ACML-7400, ACML-7410 and ACML- 7420 are multi-channel high speed CMOS , distortion of 3 ns. They are capable of running at a 100 MBaud data rate ACML-7400, ACML-7410 and ACML- 7420 are available in 16- pin SOIC wide-body packages. They operate at dual 3.3 V/5 V supply voltages. The , -7400, ACML-7410 and ACML- 7420 are built using CMOS input buffers and CMOS output drivers to eliminate the


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PDF ACML-7400, ACML-7410 ACML-7420 ACML-7420 ACML-7400 AV02-2675EN IC 7400 SERIES list IC 7400 diagram and truth table pin configuration ic 7410 IC 7410 truth table pin diagram of ic 7410 pin configuration of ic 7410 tPHL 7400 pin diagram ic 7420 working of ic 7493
Not Available

Abstract: No abstract text available
Text: as 128K x 32 in a JEDEC 68 pin surface mount PLCC, available with access times of 150, 170 and , cycles with a data retention time of 10 years. Block Diagram • Access Times of 150,170 and , Time of 10 years. Pin Definition Ü r Q < r < W < -T U I—r u g 9 8 7 , w ^ io ® I lli I cm q tw > < < < < < < |o ou œ ? < |o z Pin Functions A0~16 , WE=V, H lO T , , U=0mA, /=5MHz - 240 - 126 69 'm 'C C 3 2 16 bit IC 16 As above


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PDF 128Kx 68F4001-15/17/20 68F4001 200ns. 68F4001MB-15 256Kx 512Kx8 b3S33 MIL-STD-883
Not Available

Abstract: No abstract text available
Text: immunity. • Single 5V±10% Power supply. Block Diagram Pin Definition Refer to page 7 for 'A' version Block Diagram Refer to page 7 for 'A' version Pinout o i- C z < < pin Definition 'A' version Mosaic Semiconductor, Inc., 7420 Carroll Rd. Suite 300, San Diego , Speed Static RAM organised as 128K x 32 in a JEDEC 68 pin surface mount PLCC, available with access , €¢ JEDEC 68 pin surface mount PLCC, available in two pinouts : Single WE, WE1-4 is version A. â


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PDF 68S4000/A-020/025/35/45 68S4000/A b35337T 68S4000ALM B-020 STD-883 S4000 b3S337T
Not Available

Abstract: No abstract text available
Text: footprint. Pin Definitions Block Diagram X. idr B u lle r □□ □r □ Column t/O | , : See Diagram *V cc=5V±10% Mosaic Sem iconductor, Inc., 7420 Carroll Rd. Suite 300, San Diego, CA , €¢> _ _ < N -» O 5 12 ID J,W PACKAGE TOP VIEW DO 13 Package Details Pin Count , ) W 32 J-Leaded Chip Carrier (JLCC) J Pin Functions A0-A14 DO-7 CS OE WE Vcc GND , Absolute Maximum Ratings <> 1 Voltage on any pin relative to Vss(2 > VT Power Dissipation PT


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PDF MSM832-55/70/85/10 MSM832 MIL-STD-883. MSM832SLMB-70 MIL-STD-883
11A9

Abstract: MSM8128
Text: compatible JEDEC Standard 32 pin DIL footprint May be processed in accordance with MIL-STD-883C Block Diagram Pin Definition NC A16 A14 A12 A7 AS A5 A4 A3 A2 A1 AD C 1 C 2 c 3 c 4 c S c 6 c 7 c 8 TOPVIEW , ,5V * Output load: See Load Diagram * V =5V±10% Output Load I/O Pin 166° o- -v W - o , 2I im 32 i 31 ! 3 I2 0 nnnnnnnnn Package Détails Pin Count Description 32 32 32 0.6 , J Pin Functions A0-A16 DO-7 CS1 CS2 OE WE NC V gnd Vcc Address Inputs Data Input


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PDF MSM8128 128Kx8 MIL-STD-883. MSM8128-45/55 MSM8128SLMB-45 MIL-STD-883 b3S337^ 11A9
Not Available

Abstract: No abstract text available
Text: _ Block Diagram A3 A4 A5 A6 B iflA ? A7 JÜ .-Q A8 — '» 'g a A12A13A14- D0 ) Pin Definitions V L B o flt -™ 3JL* jSfo ï| 1 1 fr* :"\i ÎV I’1 * ’*."'1 , Pin Count 32 32 28 28 Description Package Type J-Leaded Chip Carrier (JLCC) Leadless Chip Carrier (LCC) 0.1" Vertical-in-Llne (VIL™) 0.3" Dual-in-line (SKINNY DIP) J W V T Pin , Absolute Maximum Ratings (1 > Voltage on any pin relative to Vss(2 ) VT Power Dissipation -0.5V


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PDF MSM832-020/025/35/45 MSM832 MIL-STD-883. 00242A MIL-STD-883
ic 7421

Abstract: TTL 7421 7421 ttl AND gate IC 7420 pin configuration ic 7421 TTL 7420 function ic 7421 7421 IC ic ttl 7421 pin configuration ic 7420
Text: Signetics I 7420 , 7421, LS20, LS21, S20 Gates H Dual Four-Input NAND ('20) AND ('21) Gate Product Specification Logic Products TYPE 7420 74LS20 74S20 7421 74LS21 TYPICAL PROPAGATION DELAY , ) is 50juA l|H and -2.0m A I|l, and 74LS unit load (LSul) is 2 0 iiA l|H and -0.4m A l|L. PIN , 5 853-0546 81501 Signetics Logic Products Product Specification Gates 7420 , 7421 , 4, 1985 5 -4 6 Signetics Logic Products Product Specification Gates 7420 , 7421, LS20


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PDF 74LS20 74S20 74LS21 N7420N, N74LS20N, N74S20N N7421N, N74LS21N N74LS20D, N74S20D, ic 7421 TTL 7421 7421 ttl AND gate IC 7420 pin configuration ic 7421 TTL 7420 function ic 7421 7421 IC ic ttl 7421 pin configuration ic 7420
pinout 7420

Abstract: No abstract text available
Text: accordance with MIL-STD-883. Block Diagram (see page 11 for Block Diagram of A) Pin Definition (see , Test Load I/O Pin 645n o- · - V W * - O Mosaic Semiconductor, Inc., 7420 Carroll Rd. Suite , organised as 128k x 32 in a 6 8 pin JEDECJleaded Ceramic Surface Mount Substrate. The output w id th is u s , ° l o z z z J Pin Functions AO-16 CS1-4 WE Vcc Address Inputs Chip Select Write Enable , only. (2) These parameters are calculated not measured. Mosaic Semiconductor, Inc., 7420 Carroll Rd


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PDF PUMA67E4005/A 200ns. MIL-STD-19 PUMA67E4005/A15/17/20 PUMA67E4005AMB-15 150ns 170ns MIL-STD-883. 128Kx32 512Kx8 pinout 7420
pinout 7420

Abstract: No abstract text available
Text: immunity. Single 5V±10% Power supply. Block Diagram BS3 BS2 CS2 bs T Pin Definition Ï? o £|S5|Si Is , load: see diagram * VC C =5V±10% I/O Pin o- vW - r- 1 0 0 p F 645S2 O 1.76V , organised as 256K x 32 in a JEDEC 68 pin surface mount PLCC, available with access times of 15, 17, 20, or , dramatic space saving advantage over two standard 256Kx16 devices. The PUMA 68S8000X is an pin compatible , 52 Ì A 0 -A 1 7 DO - D31 C S 1 -2 BSO-3 WE OE NC Chip Select Byte Select Write Enable Pin


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PDF PUMA68S8000X 68S8000X 256Kx16 68S2000X. 68S8000X-15/17/20/25 68S8000XLI-15 S8000 256Kx32 or512Kx16. pinout 7420
7420 pin nc

Abstract: No abstract text available
Text: chip erase. Block Diagram A0-A20 A21-A23M u l t i - c h ip A d a p t a b l e PGA - M A P 16Mx 32 , Applications. 5.0 V +/-10% read, writeand erase minimising system level powerrequirements. Hardware RESET pin - resets internal state machine to the read mode. Pin Functions A0~A23 Address Inputs \ s. D0~D31 Data , Pin C51 OE1 WEI RY/BY1 CS2ÖE2 WE2RY/BY2 CS3OE3 WE3RY/BY3 CS4OE4 WE4 . RY/BY4 . D0-D7. D8-D15 . D16-D23. D24-D31. Note: RY/BYsignal requires externall pull-up resisitor{PrototypeOnly} ^ Pin Definition


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PDF 150and 170ns. A0-A20 A21-A23M F516M-12/15/17 F516MMB-12 MIL-STD-883. 512Mbit, 7420 pin nc
Not Available

Abstract: No abstract text available
Text: . r Block Diagram Pin Definition AO C 1 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 , 100pF * Output load: See Load Diagram *V =5V±10% Mosaic Semiconductor, Inc., 7420 Carroll Rd , BUFFER WE c 14 A6 c 18 19 □ NC Pin Functions Package Details Pin Count , Ratings(1 > Voltage on any pin relative to Vss (2) VT -0.5V to +7 Power Dissipation PT , : typ This parameter is sampled and not 100% tested. Mosaic Semiconductor, Inc., 7420 Carroll Rd


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PDF MSM8512G-020/025/35 MSM8512G MSM8128 MSM8512GLMB-35 MIL-STD-883 b3S337
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