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Part Manufacturer Description Datasheet Download Buy Part
LTC2938CMS#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: 0°C to 70°C
LTC2939CMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C
LTC2938HMS#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: -40°C to 125°C
LTC2939IMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C
LTC2938HDE#PBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: DFN; Pins: 12; Temperature Range: -40°C to 125°C
LTC2939HMS#PBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C

pin configuration of BFW10 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
bfw10 transistor

Abstract: pin configuration of BFW10 BFW10 pins bf 194 pin configuration CIL 108 transistor bf 194b transistor BF 245 transistor bf 179 PIN CONFIGURATION BF 494 BF 194 transistor
Text: ooQaoaT Ô ■f- M -4.77max. TO-204AA Pin Configuration : 1 :Base 2:Emitter Body : Collector 4.09 10.67 all dimensions in m.m. SEE NOTE-2 NOTES: _1. Threads to extend to within 2—1 /2 threads of , min max max min/max typ. min/max typ. typ. Package BFW10 • 300 30 0.1 8 3500


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PDF O-237 bfw10 transistor pin configuration of BFW10 BFW10 pins bf 194 pin configuration CIL 108 transistor bf 194b transistor BF 245 transistor bf 179 PIN CONFIGURATION BF 494 BF 194 transistor
BFW10 pins

Abstract: TRANSISTOR BFW 11 pin configuration of BFW10 BFW10 CIL 108 BF 494 C bf 494 transistor BF494 BF200 transistor transistor bf 194b
Text: ” ■f- m -4.77max. TO-204AA Pin Configuration : 1 :Base 2:Emitter Body : Collector 4.09 10.67 all dimensions in m.m. SEE NOTE-2 NOTES: _1. Threads to extend to within 2—1 /2 threads of lock , min max max min/max typ. min/max typ. typ. Package BFW10 • 300 30 0.1 8 3500


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PDF O-237 BFW10 pins TRANSISTOR BFW 11 pin configuration of BFW10 BFW10 CIL 108 BF 494 C bf 494 transistor BF494 BF200 transistor transistor bf 194b
FET BFW10

Abstract: BFW10 pins OF FET BFW11 OF FET BFW10 BFW10 FET BSV81 BF327 BFW10 FET transistor BFS28 FET BFW11
Text: T1 instead of k T2 instead of a Pin 1 2 3 t, 5 6 AZ1 e1 e2 c2 b2 b1 c1 AZ2 s1 d1 q! s2 d2 q2 63 , 3 6 11 7 13 18 15 Gp= 11dB typ. at 800MHz. Rs =47fi BFW10 TO—72 BA3 30 -30 30 10 200 300 8 0.5 , drawings. 58 Pressure must avoid flexing Preferred area 0,'lnn9e of pressure / X SOD-46 T 000 0.66 , 10.72 For triacs read T1 instead at k T2 instead of a TO-60 y ' M ►1 5.1 [•  , — max Pin 1 2 3 BB1 e b c BB2 b e c BB3 d s g BB4 <3 a k BB5 b c e 1 ? 3 4 BA1 b e


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PDF BSV81 h--22-> crt6-25 FET BFW10 BFW10 pins OF FET BFW11 OF FET BFW10 BFW10 FET BF327 BFW10 FET transistor BFS28 FET BFW11
BGY41

Abstract: BFW10 FET transistor CQY58 germanium germanium transistor zener phc 283 to92 600a transistor bf199 bd643 BTW58
Text: -89 encapsulation is given in Fig. 3. direction of unreeling Fig. 1 Configuration of bandolier. Dimensions in , Fig. 2 Configuration of reel and flange (dimensions in mm). Flange diameter A thickness t , per reel is 1000. 7Z95864 direction of unreeling Fig. 3 Configuration of bandolier , transistors Selection guide INTRODUCTION The following tables represent our complete range of , -72 BFW10 BFW13 c„ (PF) 0.85 0.2- 1.5 5 BFW12 (V ) iy j min. f = 1 kHz (mS


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PDF LCD01 BGY41 BFW10 FET transistor CQY58 germanium germanium transistor zener phc 283 to92 600a transistor bf199 bd643 BTW58
NPD5564

Abstract: NPD5566 BFY91 IMF3958 2N3050 NF5458 Fairchild E212 MP842 J9100 SST5638
Text: Introduction Linear Integrated Systems is a U.S. based, full service semiconductor manufacturer of specialty linear products. Since 1987, we have been supplying pin for pin replacements for over 2000 discrete devices which are currently offered or were discontinued by Calogic, Interfet, Intersil, Micro Power Systems, Motorola, National, Fairchild, Phillips, and SiliconixVishay. We strive to provide our , BFS68P BFS70 BFS71 BFS72 BFS73 BFS74 BFS75 BFS76 BFS77 BFS78 BFS79 BFS80 BFT46 BFW10


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PDF IntegraU404 LSU405 LSU406 LS841 LS842 LS421 LS422 LS423 LS424 NPD5564 NPD5566 BFY91 IMF3958 2N3050 NF5458 Fairchild E212 MP842 J9100 SST5638
E112 jfet

Abstract: siliconix E412 NPD5564 jfet e300 NPD5566 DATA SHEET OF FET BFW10 E402 dual jfet E430 jfet E310 JFET N NPD5565
Text: Introduction Linear Integrated Systems is a U.S. based, full service semiconductor manufacturer of specialty linear products. Since 1987, we have been supplying pin for pin replacements for over 2000 discrete , component of any life support system unless a specific written agreement pertaining to such intended use is , BFS68P BFS70 BFS71 BFS72 BFS73 BFS74 BFS75 BFS76 BFS77 BFS78 BFS79 BFS80 BFT46 BFW10 BFW11


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PDF LS422 LS423 LS424 LS425 LS426 LS832 LS833 LS4391 LS5911 E112 jfet siliconix E412 NPD5564 jfet e300 NPD5566 DATA SHEET OF FET BFW10 E402 dual jfet E430 jfet E310 JFET N NPD5565
pin configuration of latch switch

Abstract: EPCS16 EPCS128 EPC16 EP2S90 EP2S60 EP2S30 EP2S180 EP2S15 EPCS64
Text: indicates configuration is complete and initialization of the device can begin. The CONF_DONE pin must , after configuration and the state of these pins depends on the dual-purpose pin settings. Table 13­9 , . Stratix II and Stratix II GX devices can be configured using one of five configuration schemes: the fast , devices, refer to the Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet in volume 2 of the , configuration scheme. Serial configuration devices offer a low cost, low pin count configuration solution


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PDF SII52007-4 pin configuration of latch switch EPCS16 EPCS128 EPC16 EP2S90 EP2S60 EP2S30 EP2S180 EP2S15 EPCS64
pin configuration 1K variable resistor

Abstract: EP1S60 EPC16
Text: the first frame of configuration data), the INIT_DONE pin will go low. DCLK should not be left , end of configuration , it resets the chain by pulsing its OE pin low for a few microseconds. This low , shows the status of the device DATA pins during and after configuration . Table 1­7. DATA Pin Status , configuration device, the pull-up resistors on the DATA0 and DCLK pins are not necessary. Pin 6 of the header , configuration data one bit at a time on the DATA0 pin of the Stratix or Stratix GX device. The least


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PDF S52013-3 pin configuration 1K variable resistor EP1S60 EPC16
CII51013-3

Abstract: EP2C20 EP2C35 EP2C50 EPC1441 EPC16 EPCS16 EPCS64 JESD-71
Text: configuration after error option in the Quartus II software from the General tab of the Device & Pin Options , transitions its nCEO pin low, initiating the configuration of the next device in the chain. You can leave the nCEO pin of the last device unconnected or use it as a user I/O pin after configuration if the , user I/O pin after configuration . The software setting is in the Dual-Purpose Pins tab of the Device , device asserts nCEO (after receiving all of its configuration data), it releases its CONF_DONE pin


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EP2S15

Abstract: EP2S180 EP2S30 EP2S60 EP2S90 EPC16 EPCS128 EPCS16 EPCS64
Text: . VCCSEL Pin The VCCSEL pin selects the type of input buffer used on configuration input pins and it , to last byte of the configuration data successfully, it releases the open-drain CONF_DONE pin , which , configuration is complete and initialization of the device can begin. The CONF_DONE pin must have an external , after configuration and the state of these pins depends on the dual-purpose pin settings. Table 7­9 , . Stratix II and Stratix II GX devices can be configured using one of five configuration schemes: the fast


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PDF SII52007-4 EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 EPC16 EPCS128 EPCS16 EPCS64
pin configuration 1K variable resistor

Abstract: TMs 1122 pin configuration 20K variable resistor EP1S60 EPC16
Text: the first frame of configuration data), the INIT_DONE pin will go low. DCLK should not be left , . Configuration data is clocked into the target Stratix devices via the DATA0 pin at each rising edge of DCLK , programming hardware then places the configuration data one bit at a time on the DATA0 pin of the Stratix or , of time. If the target device detects an error during configuration , it drives its nSTATUS pin low , dual-purpose pin settings. FPP Configuration Parallel configuration of Stratix and Stratix GX devices


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PDF S52013-3 pin configuration 1K variable resistor TMs 1122 pin configuration 20K variable resistor EP1S60 EPC16
2003 - EPC16

Abstract: fpga JTAG Programmer Schematics
Text: configuration (n = 1, 2, 4, and 8) of Altera FPGAs Pin-selectable 2-ms or 100-ms power-on reset (POR) time , migration between all devices supported in the 100- pin PQFP package Supply voltage of 3.3 V (core and I/O , ) boundary scan nINIT_CONF pin allows private JTAG instruction to initiate FPGA configuration Internal , solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two , configuration data for systems made up of one or more Altera FPGAs. Unused portions of the flash memory can be


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PDF EPC16) CF52002-1 EPC16 16-Mbit 100-pin EPC4QC100 EPC4QI100 EPC16 fpga JTAG Programmer Schematics
EP20K100E

Abstract: EP20K160E EP20K200C EP20K200E EP20K300E EP20K30E EP20K60E
Text: from the General tab of the Device & Pin Options dialog box. For successful configuration of APEX , INIT_DONE is programmed into the device (during the first frame of configuration data), the INIT_DONE pin , of configuration , it resets the entire chain by pulling its OE pin low. This low signal drives the , amount of time. If an error occurs during configuration , the FPGA drives its nSTATUS pin low, resetting , 20KC devices can be configured using one of four configuration schemes. All configuration schemes use


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PDF CF51005-2 EPC16) EP20K100E EP20K160E EP20K200C EP20K200E EP20K300E EP20K30E EP20K60E
1999 - 2.5-V Devices

Abstract: apex display EP20K600E EP20K400E EP20K400 EP20K200 EP20K1000E EP20K100 t flex 440 resistor 10k
Text: going high at the end of configuration , it resets the chain by pulsing its OE pin low for a few , configuration data one bit at a time on the DATA pin of the target device (the DATA0 pin for APEX 20K and FLEX , one of six configuration schemes, which are ideal for a variety of systems. All configuration schemes , & Configuration of Multiple Devices (APEX 20K & FLEX 10K Devices Only , clock cycles of configuration . DCLK should not be left floating. It should be driven high or low


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PDF EPC1441 2.5-V Devices apex display EP20K600E EP20K400E EP20K400 EP20K200 EP20K1000E EP20K100 t flex 440 resistor 10k
EP2S15

Abstract: pull-up resistor 10K EPCS64 EPCS16 EPC16 EP2S90 EP2S60 EP2S30 EP2S180 EPCS 16 soic
Text: Pin The VCCSEL pin selects the type of input buffer used on configuration input pins and it selects , capability of receiving byte-wide configuration data per clock cycle. Table 7­8 shows the MSEL pin settings , . Stratix II and Stratix II GX devices can be configured using one of five configuration schemes: the fast , Altera Enhanced Configuration Devices chapters in volume 2 of the Configuration Handbook. The Altera , configuration devices offer a low cost, low pin count configuration solution. 1 For information on serial


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PDF SII52007-4 EP2S15 pull-up resistor 10K EPCS64 EPCS16 EPC16 EP2S90 EP2S60 EP2S30 EP2S180 EPCS 16 soic
2003 - EPC2T

Abstract: EPC8QC100 EPC8QC100 Pinout
Text: FPGA on the rising edge of DCLK. The DCLK output pin from the enhanced configuration device serves as the FPGA configuration clock. DATA is latched by the FPGA on the rising edge of DCLK. The nCS pin is , offered in different densities and provide a variety of features. The Altera enhanced configuration , memory is through the external flash interface of the enhanced configuration devices. Fast passive , configuration solution for Cyclone devices. Serial configuration devices offer a low cost, low pin count


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PDF EPC16) EPC1441 EPC1441 32-pin EPC2T EPC8QC100 EPC8QC100 Pinout
2009 - format .pof

Abstract: format .rbf CF52007-2 .pof altera Date Code Formats EPC16 EPF10K20
Text: of the Device & Pin Options dialog box (Figure 5­1). Figure 5­1. Configuration Dialog Box , configuration is complete through the Dual-Purpose Pins tab of the Device & Pin Options dialog box. Figure 5­2 , INIT_DONE is programmed into the device (during the first frame of configuration data), the INIT_DONE pin , configuration options can be set in the Device & Pin Options dialog box. To open this dialog box, choose Device (Assignments menu), then click on the Device & Pin Options. button. You can specify your configuration


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2009 - Numonyx P30

Abstract: implement AES encryption Using Cyclone II FPGA Circuit altera cyclone 3 Altera Cyclone III TSMC 60nm sram EP3C40 EP3C25 EP3C16 EP3C120 EP3C10
Text: Settings section in volume 2 of the Configuration Handbook. Configuration and JTAG Pin I/O Requirements , resistor at the near end of the TDO and TDI pin or the serial configuration device for the DATA[0] pin , output pin low, which connects to the nCS pin of the configuration device. The Cyclone III device family , the nCEO pin of the last device unconnected or use it as a user I/O pin after configuration if the , nCE pin of another device. (4) The MSEL pin settings vary for different configuration voltage


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PDF CIII51016-1 Numonyx P30 implement AES encryption Using Cyclone II FPGA Circuit altera cyclone 3 Altera Cyclone III TSMC 60nm sram EP3C40 EP3C25 EP3C16 EP3C120 EP3C10
format .rbf

Abstract: SRUNNER JESD-71 EPCS64 EPCS16 EPC16 EPC1441 EP2C50 EP2C35 EP2C20
Text: configuration after error option in the Quartus II software from the General tab of the Device & Pin Options , transitions its nCEO pin low, initiating the configuration of the next device in the chain. You can leave the nCEO pin of the last device unconnected or use it as a user I/O pin after configuration if the , user I/O pin after configuration . The software setting is in the Dual-Purpose Pins tab of the Device , device asserts nCEO (after receiving all of its configuration data), it releases its CONF_DONE pin


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PDF CII51013-3 format .rbf SRUNNER JESD-71 EPCS64 EPCS16 EPC16 EPC1441 EP2C50 EP2C35 EP2C20
EP1K10

Abstract: EP1K30 EP1K50 EP1M120 EP20K100 EP20K200 EP20K400 ep20k100 board CF510
Text: configuration process. When nCONFIG goes high, the device comes out of reset and releases the nSTATUS pin , INIT_DONE is programmed into the device (during the first frame of configuration data), the INIT_DONE pin , Configuration After Error option (available in the Quartus II software from the General tab of the Device & Pin , connected to VCC (VCCIO of the I/O bank where the MSEL pin resides) or to ground. If your application , configuration takes precedence over other configuration schemes, which means MSEL pin settings are ignored


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PDF CF51006-2 EP1K10 EP1K30 EP1K50 EP1M120 EP20K100 EP20K200 EP20K400 ep20k100 board CF510
2012 - EP4CE15

Abstract: EP4CG E144 package TSMC 60nm sram
Text: Settings section in volume 2 of the Configuration Handbook. Configuration and JTAG Pin I/O Requirements , (during the first frame of configuration data), the INIT_DONE pin goes low. When initialization is , Configuration tab of the Device and Pin Options dialog box. 1 EPCS1 does not support Cyclone IV devices because , configuration device by driving the nCSO output pin low, which connects to the nCS pin of the configuration , leave the nCEO pin of the last device unconnected or use it as a user I/O pin after configuration . The


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PDF CYIV-51008-1 EP4CGX15, EP4CGX22, EP4CGX30 EP4CE15 EP4CG E144 package TSMC 60nm sram
2010 - Ethernetblaster

Abstract: pin configuration of buffer EP3SE50 EPCS128 EPCS16 EPCS64
Text: pin is independent of the I/O bank's power supply V CCIO during the configuration . Therefore, no , Dual-Purpose Pins tab of the Device and Pin Options dialog box. The configuration clock (DCLK) speed must be , pins after configuration . The state of these pins depends on the dual-purpose pin settings. (7) If , configuration device by driving the nCSO output pin low, which connects to the chip select (nCS) pin of the , configuration device provides data on its serial data output (DATA) pin , which connects to the DATA0 input of


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PDF SIII51011-1 Ethernetblaster pin configuration of buffer EP3SE50 EPCS128 EPCS16 EPCS64
8EPC2

Abstract: A-DS-EPROM-11 EP20K30E EP20K60E EPC1064 EPC1064V EPC1213 EPC1441
Text: tri-states its DATA pin . The nCS pin controls the output of the configuration device. If nCS is held high , initiate configuration of the ACEX, APEX, FLEX, or Mercury device via an additional pin , nINIT_CONF, that , sends a serial bitstream of configuration data to its DATA pin , which is routed to the DATA0 or DATA , Mercury Configuration (Part 2 of 2) Pin Name Pin Number 8- Pin PDIP (1) 20- Pin 32- Pin PLCC TQFP , , APEX, FLEX & Mercury Devices Data Sheet Table 5 describes the pin functions of all configuration


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PDF -DS-EPROM-11 8EPC2 A-DS-EPROM-11 EP20K30E EP20K60E EPC1064 EPC1064V EPC1213 EPC1441
2005 - BITBLAST

Abstract: No abstract text available
Text: buffer. The configuration device sends a serial bitstream of configuration data to its DATA pin , which is , configuration of the FPGA via an additional pin , nINIT_CONF. The nINIT_CONF pin of the EPC2 device can be , , which allows the INIT_CONF JTAG instruction to initiate FPGA configuration . The nCS pin of the master configuration device is connected to the CONF_DONE of the FPGA(s), while its nCASC pin is connected to nCS of , of 200 ms. During POR, the configuration device drives its OE pin low. This low signal delays


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PDF CF52005-2 EPC1441 EPC1441 32-pin 20-pin BITBLAST
2006 - ac 187 pin configuration

Abstract: EPCS 16 soic F324 F256 EPCS64 EPCS16 EP3C40 EP3C25 U484 EP3C10
Text: and latch configuration data on the falling edge of DCLK. 1 The FLASH_nCE pin and DATA[1] pin are , connects to the chip select (nCS) pin of the configuration device. The Cyclone III device uses the serial , device (during the first frame of configuration data), the INIT_DONE pin goes low. When initialization , the first device captures all of its configuration data from the bitstream, it drives the nCEO pin , receiving all of its configuration data), it releases its CONF_DONE pin . However, the subsequent devices in


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PDF CIII51010-1 S29WS-N ac 187 pin configuration EPCS 16 soic F324 F256 EPCS64 EPCS16 EP3C40 EP3C25 U484 EP3C10
Supplyframe Tracking Pixel