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LTC2938CMS#PBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: 0°C to 70°C
LTC2939CMS#PBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C
LTC2938CMS#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: 0°C to 70°C
LTC2939CMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C
LTC2938HDE#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: DFN; Pins: 12; Temperature Range: -40°C to 125°C
LTC2939HMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C

pin configuration of 74LS154 Datasheets Context Search

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pin configuration of 74LS154

Abstract:
Text: lOul 74LS 1LSul 10LSul PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 5E 1 [I 2 , Signetics 74154, LS154 Decoder/Demultiplexers 1- of -16 Decoder/Demultiplexer Product , 2-input enable gate for strobing or expansion TYPE 74154 74LS154 TYPICAL PROPAGATION DELAY 21ns , it can be used for expansion of the decoder. The enable gate has two AND'ed inputs which must be LOW to enable the outputs. The '154 can be used as a 1- of -16 demultiplexer by using one of the enable


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PDF LS154 1-of-16 16-line 74LS154 1N916, 1N3064, 500ns pin configuration of 74LS154 circuit diagram of 74ls154 LS154 1 to 16 74154 demultiplexer decoder 74154 pin diagram decoder 74154 pin configuration of 74154 N74LS154N 74LS154 pin diagram of 74ls154
TTL 74154

Abstract:
Text: ln_. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) Ö E Hl vcc ï Œ m *o 2d iE , Signetics 74154, LS154 Decoder/Demultiplexers 1- of -16 Decoder/Demultiplexer Product , it can be used for expansion of the decoder. The enable gate has two AND'ed inputs which must be LOW to enable the outputs. The '154 can be used as a 1- of -16 demultiplexer by using one of the enable , state of the applied data. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74154 21ns


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PDF LS154 1-of-16 16-line 1N916, 1N3064, 500ns TTL 74154 pin configuration of 74154 pin configuration of 74LS154 74ls154 pin diagram of 74ls154 74154 circuit diagram of 74ls154 decoder 74154 74154 demultiplexer 74154 decoder
1 to 16 74154 demultiplexer

Abstract:
Text: 1ul 10ut 74LS 1LSul 10LSul PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) ·E , Signetics 74154 , LSI54 Decoder/Demultiplexers 1- of -16 Decoder/Demultiplexer Product , 2-input enable gate for strobing or expansion TYPE 74154 74LS154 TYPICAL PROPAGATION DELAY 21ns , it can be used for expansion of the decoder. The enable gate has two AND'ed inputs which must be LOW to enable the outputs. The '154 can be used as a l-of-16 demultiplexer by using one of the enable


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PDF LSI54 1-of-16 16-line 74LS154 1N916, 1N3064, 500ns 500ns 1 to 16 74154 demultiplexer 74LS154 decoder TTL 74154 pin configuration of 74LS154 decoder 74LS154 circuit diagram of 74ls154 74ls154 max3633 N74LS154 74154 demultiplexer
pin configuration of 74LS154

Abstract:
Text: static random access memory module in a 36 pin single-inline-package format. Physically it consists of an FR4 PC material substrate mounted with sixteen 32K x 8 SOP (small outline package) ICs, the 1- of -16 decoder, four 0.1 microfarad decoupling capacitors, and 36 edge-clip I/O pins. The module can use any of the 32K x 8 SRAMs made by any of a large number of manufacturers in both Mix-MOS and CMOS technologies , density > > On board 1- of -16 Decoder > > Completely Static operation > > TTL compatible > > Low power


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PDF AEPSX512K8 1-of-16 pin configuration of 74LS154 ic 74ls154 74hct154 pin diagram of 74ls154 74F154 OF 74LS154 decoder 74LS154 74LS154 decoder 128K X 8 BIT LOW POWER CMOS SRAM 1 of 16 Decoder 74HC154
Demultiplexer IC 74154

Abstract:
Text: and -0.4mA I|l- PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 5 E îE i\r *E , Signetìcs 74154, LS154 Decoder/Demultiplexers 1- of -16 Decoder/Demultiplexer Product , 2-input enable gate for strobing or expansion TYPE 74154 74LS154 TYPICAL PROPAGATION DELAY 21ns , it can be used for expansion of the decoder. The enable gate has two AND'ed inputs which must be LOW to enable the outputs. The '154 can be used as a 1- of -16 demultiplexer by using one of the enable


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PDF LS154 1-of-16 16-line 74LS154 1N916, 1N3064, 500ns 500ns Demultiplexer IC 74154 decoder IC 74154 IC 74154 IC 74154 pin diagram decoder IC 74154 pin diagram cI 74154 pin diagram of iC 74154 TTL 74154 IC TTL 74154 of Demultiplexer IC 74154
Advanced Electronic Packaging

Abstract:
Text: m aximize bit density > > On board 1- of -16 D eco d er > > Com pletely Static operation > > TTL com , high density 512 Kilo-word by 8 bit static random access memory module in a 36 pin single-inline-package format. Physically it consists of an FR4 PC material substrate mounted with sixteen 32K x 8 SOP (small outline package) ICs, the 1- of -16 decoder, four 0.1 microfarad decoupling capacitors, and 36 edge-clip I/O pins. The module can use any of the 32K x 8 SRAMs made by any of a large number of


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PDF AEPSX512K8 1-of-16 Advanced Electronic Packaging 74F154 512 x 8 static ram 512K x 8 bit Low Power CMOS Static RAM decoder 74LS154 ic 74ls154 pin diagram of 74ls154
Not Available

Abstract:
Text: > > Double sided to maximize bit density > > On board 1- of -16 Decoder > > Completely Static operation , AEPSX512K8 is a high density 512 Kilo-word by 8 bit static random access memory module in a 36 pin single-inline-package format. Physically it consists of an FR4 PC material substrate mounted with sixteen 32K x 8 SOP (small outline package) ICs, the 1- of -16 decoder, four 0.1 microfarad decoupling capacitors, and 36 edge-clip I/O pins. The module can use any of the 32K x 8 SRAMs made by any of a large number of


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PDF AEPSX512K8 1-of-16 AEPSX512K8
74ls154

Abstract:
Text: fail to connect ADC pin to Vqq or GND when using. Fig. 6 shows the relations between Y address of RAM , > Page 6 DB7 DBO e Page 7 DB7 X = 6 X = 7 Fig. 8 Address Configuration of Display Data RAM 13 , . 15 HD 61202 b) Example of connection with HD6801 74LS154 PIO Pli P12 P13 (lOS)SCl (R/W)SC2 P14 , driving signals. Each bit data of display RAM corresponds to ON/OFF of each dot of liquid crystal display , liquid crystal graphic display system configuration by combining the row (common) driver HD61203. â


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PDF HD61202 HD61202 HD6801 74LS154 HD61202. HD6800 HD6801, yl-63 HD61203 pin configuration of 74LS154 pin diagram of 74ls154 LS2074 circuit diagram of 74ls154 61202
Not Available

Abstract:
Text: density > > On board 1- of -16 Decoder > > Completely Static operation > > TTL compatible » Low , Kilo-word by 8 bit static random access memory module in a 36 pin single-inline-package format. Physically it consists of an FR4 PC material substrate mounted with sixteen 32K x 8 SOP (small outline package) ICs, the 1- of -16 decoder, four 0.1 microfarad decoupling capacitors, and 36 edge-clip I/O pins. The module can use any of the 32K x 8 SRAMs made by any of a large number of manufacturers in both Mix-MOS


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PDF DSS47T3 AEPSX512K8 1-of-16 AEPSX512K8
74LS154 truth table

Abstract:
Text: (OPR) = 2 V to 6 V PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS154 B1R (Plastic Package) M1R (Micro Package) ORDER CODES : M74HC154B1R M74HC154M1R PIN CONNECTIONS (top view) DESCRIPTION , MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. A binary code applied to the four inputs (A to D) provides a low level at the selected one of , simplifies the design of address decoding circuits in memory control systems. All inputs are equipped with


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PDF M74HC154 54/74LS154 M74HC154B1R M74HC154M1R 74HC154 16-LINE 74LS154 truth table 74LS154 truth table demultiplexer M74HC154B1R 1 of 16 Decoder 74HC154 P043A M74HC154M1R M74HC154 ic 74ls154 16-LINE
1 to 16 74154 demultiplexer

Abstract:
Text: l|L. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 3 E El vcc ' ΠH] *0 1[T 11 *1 , Sgnetics 74154, LS154 Decoder/Demultiplexers 1- of -16 Decoder/Demultiplexer Product , it can be used for expansion of the decoder. The enable gate has two AND'ed inputs which must be LOW to enable the outputs. The '154 can be used as a 1- of -16 demultiplexer by using one of the enable , state of the applied data. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74154 21ns


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PDF LS154 1-of-16 16-line WF064S0S 1N916, 1N3064, 500ns 1 to 16 74154 demultiplexer TTL 74154 cI 74154 74154 demultiplexer pin configuration of 74154 74154 decoder 74154 74154 pin diagram ls154 pin diagram decoder 74154
Not Available

Abstract:
Text: (Micro Package) WIDE OPERATING VOLTAGE RANGE Vcc (OPR) = 2 V to 6 V PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS154 ORDER CODES : M74HG154B1R M 74H C 154M 1R PIN CONNECTIONS (top view) n H E E £ , /DEMULTIPLEXER fabricated in siNcon gate C^MOS technology. It has ttie same high speed performance of LSTTL , a low level at the selected one of sixteen outputs excluding the other fifteen outputs, when both , INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No I, 2, 3, 4, 5, 6, 7, 8, 9, 10, I I , 13, 14


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PDF M74HC154 54/74LS154 M74HG154B1R 74HC154 16-LINE
MM74HC pin configuration

Abstract:
Text: , and is functionally and pin equivalent to the 54LS154/ 74LS154 . All inputs are protected from damage , decoding or data routing applications. It possesses high noise immunity, and low power consumption of CMOS , inputs (A, B, C, and D). If the device is enabled these inputs determine which one of the 16 normally high outputs will go low. Two active low enables (GT and G2) are provided to ease cascading of decoders , (V0ut) - 0.5 to VCc + 0.5V Clamp Diode Current (I|k, Iok) ±20 mA DC Output Current, per pin (Iout) Â


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PDF MM54HC154/MM74HC154 4-to-16 MM74HC pin configuration pin configuration of 74LS154 circuit diagram of 74ls154 T55B D2132 G1.L decoder 74LS154 54LS154 74HC MM54HC154J
decoder IC 74hc154

Abstract:
Text: VOLTAGE RANGE VCc (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS154 PIN CONNECTIONS (top view , of LSTTL combined with true CMOS low power consumption. A binary code applied to the four inputs (A to D) provides a low level at the selected one of sixteen outputs excluding the other fifteen outputs , decoding lines through cascading, and simplifies the design of address decoding circuits in memo ry control , Output Pin DC Vcc or Ground Current Power Dissipation Storage Temperature Parameter Value -0 .5 to 7


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PDF M54HC154 M74HC154 16-LINE 54/74LS154 M74HC154 M54/74HC154 decoder IC 74hc154 74hc154 1 of 16 Decoder 74HC154 circuit diagram of 74ls154 ic 74ls154 M74HC154B1N
74LS154 decoder

Abstract:
Text: levels of high performance to microprocessor applications not previously possible with MOS technology. In the majority of cases, the choice of a bipolar microprocessor slice, as opposed to a MOS device , of executing all instructions in 250 ns. The 8X300 is optimized for control and data movement , a clock. The unique features of the 8X300 IV bus and instruction set permit 8-bit parallel data to , and merged into any set of from 1 to 8 contiguous bits at the destination. The entire process of input


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PDF 8X300KT100SK 8X300 13-bit 16-bit 74LS154 decoder NE556A NE556A timer CI 74LS04 signetics 74ls04 74LS04 SIGNETICS 74LS74 SIGNETICS Signetics NE556A decoder 74LS154 74LS04 INVERTER
1 of 16 Decoder 74HC154

Abstract:
Text: (Plastic Package) M1R (Micro Package) WIDE OPERATING VOLTAGE RANGE Vcc (OPR) = 2 V t o 6 V PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS154 ORDER CODES : M74HC154B1R M74HC154M1R PIN CONNECTIONS (top view , silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low , selected one of sixteen outputs excluding the otherfifteenoutputs, when both the stro be inputs, G1 and G2 , simplifies the design of address decoding circuits in memory control systems. Alt inputs are equipped with


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PDF 54/74LS154 M74HC154B1R M74HC154M1R 74HC154 16-LINE 1 of 16 Decoder 74HC154 ic 74ls154 circuit diagram of 74ls154 pin diagram of 74ls154 USC16 y12 t
74LS154

Abstract:
Text: liquid crystal graphic display system configuration . Pin Arrangement Z ü iiiiè îïiis s ii Ym Ym Y li , further details on HD6800 and HD6801, refer to their manuals. 74LS154 Figure 8 Example of Connection , state of each dot o f a liquid crystal display to provide more flexible than character display. The , Information Type No. HD44102CH HD44102D Package 80- pin plastic OFP(FP-80) Chip · · · · · · · , of 65 Hz, in checker pattern display. Access from the CPU is stopped. 12. Measured by terminal at no


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PDF HD44102------------------------ HD44102CH HD44102 HD6303 HD44102CH HD6303 74LS154 HITACHI hd6303
54LS154

Abstract:
Text: , and is functionally and pin equivalent to the 54LS154/ 74LS154 . All inputs are protected from damage , noise Immunity, and low power consumption of CMOS with speeds similar to low power Schottky TTL circuits , Inputs deter mine which one of the 16 normally high outputs will go low. Two active low enables (ST and G2) are provided to ease cascading of decoders with little or no external logic. -6 7 -3 /-.S 7 , Number MM54HC154* or MM74HC154* ·Please look into Section 8, Appendix D for availability of various


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PDF bS01152 MM54HC154/MM74HC154 4-to-16 MM54HC154/MM74HC154 54LS154 ic 74ls154
1999 - decoder 74LS154

Abstract:
Text: functionally and pin equivalent to the 74LS154 . All inputs are protected from damage due to static discharge , data routing applications. It possesses high noise immunity, and low power consumption of CMOS with , , and D). If the device is enabled these inputs determine which one of the 16 normally HIGH outputs will go LOW. Two active LOW enables (G1 and G2) are provided to ease cascading of decoders with , Pin Assignments for DIP, SOIC and TSSOP Inputs G1 G2 Low D C B A Output (Note 1


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PDF MM74HC154 4-to-16 MM74HC154 decoder 74LS154 pin diagram of 74ls154 74LS154 truth table 74LS154 data sheet circuit diagram of 74ls154 DATA SHEET OF 74LS154 MM74HC154WM M24B MM74HC154MTC
2003 - circuit diagram of 74ls154

Abstract:
Text: and pin equivalent to the 74LS154 . All inputs are protected from damage due to static discharge by , routing applications. It possesses high noise immunity, and low power consumption of CMOS with speeds , If the device is enabled these inputs determine which one of the 16 normally HIGH outputs will go LOW. Two active LOW enables (G1 and G2) are provided to ease cascading of decoders with little or no , appending the suffix letter "X" to the ordering code. Connection Diagram Truth Table Inputs Pin


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PDF MM74HC154 4-to-16 MM74HC154 74LS1THOUT circuit diagram of 74ls154 decoder 74LS154 74LS154 74LS154 truth table 74ls154 data sheet DATA SHEET OF 74LS154 74ls154 fairchild pin diagram of 74ls154 74LS154 decoder datasheet 74LS154 decoder
Not Available

Abstract:
Text: ORDERING NUMBERS: M54HC154 F1 M74HC154M1 M74HC154 B1N M74HC154F1 ■PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS154 PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC154 is a high speed CMOS 4 TO , speed performance of LSTTL combined with true CMOS low power consumption. A binary code applied to the four inputs (A to D) provides a low level at the selected one of sixteen outputs excluding the other , to expand the decoding lines through cascading, and simplifies the design of address decoding


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PDF M54HC154 M74HC154 16-LINE M54HC154 M74HC154M1 M74HC154 M74HC154F1 54/74LS154
74LS154 truth table demultiplexer

Abstract:
Text: to 6V i PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS154 description The M54/74HC154 is a high speed , high speed performance of LSTTL combined with true CMOS low power consumption. A binary code applied to the four inputs (A to D) provides a low level at the selected one of sixteen outputs excluding the , easy to expand the decoding lines through cascading, and simplifies the design of address decoding , Package ORDERING NUMBERS: M54HC154 F1 M74HC154 M1 M74HC154 B1N M74HC154 F1 pin connections (top view


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PDF M54HC154 M74HC154 16-LINE 54/74LS154 M54/74HC154 74LS154 truth table demultiplexer 74LS154 truth table 74hc154 74LS154 1 of 16 Decoder 74HC154 74HC 54HC M74HC154 circuit diagram of 74ls154 decoder IC 74hc154
HD44102CH

Abstract:
Text: P30-P37 are used as the data bus. • The 74LS154 is a 4-to-16 decoder that decodes 4 bits of P10-P13 to , dot matrix liquid crystal driving signals. Each bit data of display RAM corresponds to on/off state of each dot of a liquid crystal display to provide more flexible than character display. The HD44102CH is produced by the CMOS process. Therefore, the combination of HD44102CH with a CMOS , dissipation. The combination of HD44102CH with the row (common) driver HD44103CH facilitates dot matrix


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PDF D44102- HD44102CH HD44102 A2-A15 HD6303 HD44103CH MSB808 HD44102CH* application HD44102D h06303 work of 74ls154 HD6800
74LS154P

Abstract:
Text: Operating Voltage Range-—Vcc (opr.) = 2V~6V • Pin and Function Compatible with 74LS154 _ P (DIP24-P-300-2.54) Weight: 1.50g (Typ.) PIN ASSIGNMENT Y0 IE -W- 1 24 Vcc Y1 2[ ] 23 A Y2 3[ 2 22 B Y3 4[ 1 21 C Y4 , D is decoded within the device. Depending on the binary code, causes one of sixteen outputs to go , decoding lines through cascading, and simplifies the design of address decoding circuits in a memory , working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in


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PDF TC74HC154AP TC74HC15 TC74HC154A 24PIN DIP24-P-300-2 93TYP 74LS154P 74ls154 303MAX 74LS154 truth table demultiplexer circuit diagram of 74ls154 TC74HC154 TC74HC154AP
74LS154

Abstract:
Text: Operating Voltage Range-—Vcc (opr.) = 2V~6V • Pin and Function Compatible with 74LS154 _ P (DIP24-P-300-2.54) Weight: 1.50g (Typ.) PIN ASSIGNMENT Y0 IE —w— 1 24 VCC Y1 2[ ] 23 A Y2 3[ ] 22 B Y3 4[ 1 21 C , D is decoded within the device. Depending on the binary code, causes one of sixteen outputs to go , decoding lines through cascading, and simplifies the design of address decoding circuits in a memory , improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general


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PDF TC74HC154AP TC74HC15 TC74HC154A 24PIN DIP24-P-300-2 93TYP 74LS154 74LS154 truth table demultiplexer 74LS154 truth table circuit diagram of 74ls154 TC74HC154AP
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