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Part Manufacturer Description Datasheet Download Buy Part
LTC2938HMS#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: -40°C to 125°C
LTC2939IMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C
LTC2938HDE#PBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: DFN; Pins: 12; Temperature Range: -40°C to 125°C
LTC2939HMS#PBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C
LTC2938HDE#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: DFN; Pins: 12; Temperature Range: -40°C to 125°C
LTC2939HMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C

pin configuration 74LS00 Datasheets Context Search

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74LS00 pin configuration

Abstract: gd74ls04 74LS00 function table 74LS00 pin configuration 74LS00 74LS00 Electrical and Switching characteristics 74LS04 NOT gate GD74LSOO 74LS00 clock frequency pin configuration 74LS04
Text: GD54/ 74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES Description This device contains four independent 2-input NAND gates, jt^ performs the Boolean functions Y = A B or Y=A+B in positive logic. Function Table (each gate) INPUTS OUTPUT A B Y H H L L X H X L H Pin Configuration Vcc 4B 4 A 4 Y 3B , to 150°C 4-3 This Material Copyrighted By Its Respective Manufacturer GD54/ 74LS00 Recommended , 4-4 This Material Copyrighted By Its Respective Manufacturer GD54/ 74LS00 Application Example


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PDF GD54/74LS00 GD74LSOO GD74LS04 74LS04 74LS00 pin configuration gd74ls04 74LS00 function table 74LS00 pin configuration 74LS00 74LS00 Electrical and Switching characteristics 74LS04 NOT gate GD74LSOO 74LS00 clock frequency pin configuration 74LS04
74LS00 clock frequency

Abstract: 74LS00 function table pin configuration 74LS00
Text: GD54/ 74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES Description This device contains four independent 2-input NAND gates. K performs the Boolean functions Y = A B or Y = A + B in positive logic. Pin Configuration V cc 4B 4A 4Y 3B 3A 14 13 12 11 10 9 3Y 8 , . - 6 5 ° C to 1 5 0 ° C 4-3 GD54/ 74LS00 Recommended Operating Conditions SYMBOL MIN , -1 1 . 4-4 GD54/ 74LS00 Application Example Crystal Clock Generator (1) G D74LS00 c


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PDF GD54/74LS00 D74LS00 D74LS04 74LS00 clock frequency 74LS00 function table pin configuration 74LS00
IC 74LS00

Abstract: 74LS00 74LS00 pin configuration 74LS00 function table pin configuration 74LS00 74LS00 clock frequency NAND 74LS00 74LS00 Electrical and Switching characteristics 74LS00 application 74ls00 NAND gate
Text: GD54/ 74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES Description This device contains four independent 2-input NAND gates. It performs the Boolean functions Y = A B or Y = A + B in positive logic. Pin Configuration V cc 14 4B 13 4A 12 4Y 11 3B 10 3A 9 3Y 8 Function Table (each gate) INPUTS A H , . - 6 5 CC to 1 5 0 ° C 2-45 40HÖ7S7 OOGHnO fib4 GD54/ 74LS00 Recommended Operating , GD54/ 74LS00 Application Example Crystal Clock Generator (1) G D 7 4 L S 0 0 c, Frequency (MHz) 1


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PDF GD54/74LS00 402B757 IC 74LS00 74LS00 74LS00 pin configuration 74LS00 function table pin configuration 74LS00 74LS00 clock frequency NAND 74LS00 74LS00 Electrical and Switching characteristics 74LS00 application 74ls00 NAND gate
1998 - pin diagram of 74ls00

Abstract: 74LS00 74ls00 datasheet 74HC74 motorola 74LS00 memory card circuit diagram 74HC74 decoder inverter wait 74LS00 impedance 74LS00 application
Text: B B Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0 9 10 74LS00 U1B C 74LS00 U1C 4 5 C 8 6 D1 D1 D0 3 11 12 3 2 , only one chip select used. TITLE AUTHOR COMPANY DATE REVISION PATTERN CHIP ; PIN ; PIN


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PDF 74HC04 0xfff44b 0xfff449 0xfff448 0xfff443 0xfff441 0xfff440 pin diagram of 74ls00 74LS00 74ls00 datasheet 74HC74 motorola 74LS00 memory card circuit diagram 74HC74 decoder inverter wait 74LS00 impedance 74LS00 application
ls 7400

Abstract: 7400 signetics TTL TTL LS 7400 7400 ls 7400 pin configuration TTL 7400 propagation delay 74LS00 signetics 74l500 74ls00 tr tf 74LS00 function table
Text: -0.4mA l|L. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) _1 2 & v. 3 _4 _S ^ 6 10 _9 , Signetìcs I 7400, LSOO, SOO Gates Logic Products Quad Two-Input NAND Gate Product Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7400 9ns 8mA 74LS00 9.5ns 1.6mA 74SOO 3ns 15mA ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = 5V ±5%; Ta = 0°C to + 70°C Plastic , .) PARAMETER TEST CONDITIONS1 7400 74LS00 74S00 UNIT Min Typ2 Max Min Typ2 Max Min Typ2 Max


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PDF 74LS00 74SOO N7400N, N74LS00N, N74S00N N74LS00D, N74S00D 10Sul 10LSul WF07570S ls 7400 7400 signetics TTL TTL LS 7400 7400 ls 7400 pin configuration TTL 7400 propagation delay 74LS00 signetics 74l500 74ls00 tr tf 74LS00 function table
7400 signetics

Abstract: 74LS00 7400 74S00 N7400N 7400 pin configuration 74LS00 function table 7400 signetics TTL 74LS00 DATA TTL 7400 TTL 7400 propagation delay 74LS00 pin configuration
Text: Signetics I 7400, LS00, SOO Gates Logic Products Quad Two-Input NAND Gate Product Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7400 9ns 8mA 74LS00 9.5ns 1.6mA , load (Sul) Is 50^A l|H and -2.0mA l|L, and 74LS unit load (LSul) is 20/iA l|H and -0.4mA l,L. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 1 2 & ^ 3 _« _5 10 IT 12 ^ 11 13 , CONDITIONS1 7400 74LS00 74S00 UNIT Min Typ2 Max Min Typ2 Max Min Typ2 Max HIGH-level OH output


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PDF 74LS00 74S00 N7400N, N74LS00N, N74S00N N74LS00D, N74S00D 10Sul 10LSul 7400 signetics 74LS00 7400 74S00 N7400N 7400 pin configuration 74LS00 function table 7400 signetics TTL 74LS00 DATA TTL 7400 TTL 7400 propagation delay 74LS00 pin configuration
74LS00 function table

Abstract: ls 7400 pin configuration logic symbol 74LS00 specification of 74ls00 74LS00 pin configuration TTL LS 7400 logic symbol 74LS00 TTL 74ls00 7400 ls pin configuration 74LS00
Text: 1Sul 10Sul 74LS 1LSul 10LSul PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC , Signelics | 7400, LS00, S00 Gates Quad Two-Input NAND Gate Product Specification Logic Products TYPE 7400 74LS00 74S00 TYPICAL PROPAGATION DELAY 9ns 9.5ns 3ns TYPICAL SUPPLY CURRENT (TOTAL) 8mA 1.6mA 15mA ORDERING CODE PACKAGES Plastic DIP Plastic SO COMMERCIAL RANGE VCC = 5 V ± 5 % , 74LS00 Max Min 2.7 0.4 Typ2 3.4 0.35 0.25 -1 .5 0.5 0.4 -1 .5 Max Min 2.7 74S00 UNIT Min Typ2 3.4 0.2


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PDF 74LS00 74S00 N7400N, N74LS00N, N74S00N N74LS00D, N74SOOD 74LS00 function table ls 7400 pin configuration logic symbol 74LS00 specification of 74ls00 74LS00 pin configuration TTL LS 7400 logic symbol 74LS00 TTL 74ls00 7400 ls pin configuration 74LS00
pin diagram of 74ls00

Abstract: 74HC04 74HC74 74LS00 74HC74 decoder motorola 74LS00 74LS00 application 74LS00 impedance 74ls00 circuit diagram inverter wait
Text: 74HC04 U2A 2 B Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0 9 10 74LS00 U1B C 74LS00 U1C 4 5 C 8 6 D1 D1 D0 3 11 , AUTHOR COMPANY DATE REVISION PATTERN CHIP ; PIN ; PIN PCMCIA VER 2.01 DECODER JACKY LI


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PDF Informatfff448 0xfff443 0xfff441 0xfff440 0xfff44b 0xfff449 0xfff448 pin diagram of 74ls00 74HC04 74HC74 74LS00 74HC74 decoder motorola 74LS00 74LS00 application 74LS00 impedance 74ls00 circuit diagram inverter wait
74LS00

Abstract: motorola 74LS00 datasheet of ic 74ls00 74LS00 impedance pin diagram of ic 74ls00 pin diagram of 74ls00 74ls00 circuit diagram 74HC74 decoder 74HC74 inverter wait
Text: Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0 9 10 74LS00 U1B C 74LS00 U1C 4 5 C 8 6 D1 D1 D0 3 11 12 3 2 Q , CHIP ; PIN ; PIN PCMCIA VER 2.01 DECODER JACKY LI MOTOROLA INC. 23/11/98 1 CLK U1


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PDF 0fff448 0xfff443 0xfff441 0xfff440 0xfff44b 0xfff449 0xfff448 74LS00 motorola 74LS00 datasheet of ic 74ls00 74LS00 impedance pin diagram of ic 74ls00 pin diagram of 74ls00 74ls00 circuit diagram 74HC74 decoder 74HC74 inverter wait
datasheet of ic 74ls00

Abstract: pin diagram of ic 74ls00 pin diagram of 74ls00 motorola 74LS00 74LS00 74HC74 74HC74 decoder 74LS00 impedance 74LS00 application 74HC74 application
Text: Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0 9 10 74LS00 U1B C 74LS00 U1C 4 5 C 8 6 D1 D1 D0 3 11 12 3 2 Q , COMPANY DATE REVISION PATTERN CHIP ; PIN ; PIN PCMCIA VER 2.01 DECODER JACKY LI MOTOROLA INC


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PDF 0xfff44b 0xfff449 0xfff448 0xfff443 0xfff441 0xfff440 datasheet of ic 74ls00 pin diagram of ic 74ls00 pin diagram of 74ls00 motorola 74LS00 74LS00 74HC74 74HC74 decoder 74LS00 impedance 74LS00 application 74HC74 application
1999 - schematic diagram brushless motor control

Abstract: schematic diagram Permanent Magnet brushless DC m permanent magnet synchronous machine ST52X301 schematic diagram Permanent Magnet brushless DC Speed Control Of DC Motor Using Fuzzy Logic code jps inverter stepping motor japan servo brushless motor control inverter schematic diagram speed control of dc motor using fuzzy logic controller
Text: 5 9 10 74LS00 74LS00 74LS00 IN2 IN3 8 3 6 8 IN1 IN2 IN3 , application. SOFTWARE DESCRIPTION Before to discuss about ST52x301 software configuration , it is important to note some HW connections in the schematic. Bit "0" ( pin 9) of the parallel port is used to enable , analog input AIN0 ( pin 43) is used to read the voltage reference. A voltage between 0 + 2.5 V present on this pin , is converted in the range 0 + 255. External INTerrupt pin (27) is used to read one Hall


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PDF AN1113 ST52x301 schematic diagram brushless motor control schematic diagram Permanent Magnet brushless DC m permanent magnet synchronous machine ST52X301 schematic diagram Permanent Magnet brushless DC Speed Control Of DC Motor Using Fuzzy Logic code jps inverter stepping motor japan servo brushless motor control inverter schematic diagram speed control of dc motor using fuzzy logic controller
TTL 74HC00

Abstract: 74LS00 TTL 5V 74HC00 logic symbol 74LS00 TTL 74ls00 74LS00 gate diagram 74LS00 function table 74ls00 74hc00 and gates 74HC00
Text: €¢ High noise immunity characteristic of CMOS • Diode protection on all inputs Pin Configuration 1A [T , GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/ 74LS00 . They contain four independent 2-input NAND gates. These devices are characterized for opération over Wide temperature ranges to meet in-dustry and military spécifications. Features • Low Power consumption characteristic of CMOS devices • Output drive capability: 10 LS TTL


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PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 D0Q457Q TTL 74HC00 74LS00 TTL 5V 74HC00 logic symbol 74LS00 TTL 74ls00 74LS00 gate diagram 74LS00 function table 74ls00 74hc00 and gates 74HC00
74LS00 pinout

Abstract: TTL 74HC00 74hc00 and gates 5V 74HC00 74HC00 logic symbol 74LS00 pin configuration logic symbol 74LS00 GD74HC00 74LS00 gate diagram GD54HC00
Text: €¢ High noise immunity characteristic of CMOS • Diode protection on all inputs Pin Configuration 1A , GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/ 74LS00 . They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet industry and military specifications. Features • Low Power consumption characteristic of CMOS devices • Output drive capability: 10 LS TTL


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PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 74LS00 pinout TTL 74HC00 74hc00 and gates 5V 74HC00 74HC00 logic symbol 74LS00 pin configuration logic symbol 74LS00 GD74HC00 74LS00 gate diagram GD54HC00
74HCoo

Abstract: TTL 74HC00 74LS00 pinout pin diagram of 74ls00 74LS00 gate diagram logic symbol 74LS00 74hc00 and gates 74HC00 pin configuration logic symbol 74LS00 GD74HC00
Text: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/ 74LS00 . They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet industry and military specifications. Features , . (74HC) • High noise immunity characteristic of CMOS • Diode protection on all inputs Pin Configuration 1A EE u 23 vcc 1B Dl 13 4B 1Y IZ HI 4 A 2 A Cl 00 4Y 2B (Z 3B 2 Y [I 3A GMD [I


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PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 74HCoo TTL 74HC00 74LS00 pinout pin diagram of 74ls00 74LS00 gate diagram logic symbol 74LS00 74hc00 and gates 74HC00 pin configuration logic symbol 74LS00 GD74HC00
CD4011 internal diagram

Abstract: of 74ls00 pin configuration cd4011 CD4011 equivalent CD4011 PIN DIAGRAM MUX-24 HI-509A CD4011 74LS00 cd40115
Text: /Hold Circuit 12-Bit A/D 3-State Output Buffer ■40 Pin DIP ■35 kHz Throughput ■Low Power , offered in 40- pin ceramic packages and are specified for operation from 0 °C to 70 °C for commercial , OUTLINE (53.74) 40 21 t 0.800 40 PIN MAX (20.32) 1 20 I • * i TOP VIEW PIN (1) INDEX , in plastic PIN ASSIGNMENTS PIN FUNCTION PIN FUNCTION 1 CH0/CH0 HI 40 LATCH 2 CH1/CH1 HI 39 MA2 , APPLICATIONS INFORMATION (continued) UNIPOLAR/BIPOLAR CONFIGURATION The HS 9404/HS 9408 - 2 are 20 volt range


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PDF 12-Bit HI-508A MUX-08 940X-J1 940X-J2 940X-K1 940X-K2 CD4011 internal diagram of 74ls00 pin configuration cd4011 CD4011 equivalent CD4011 PIN DIAGRAM MUX-24 HI-509A CD4011 74LS00 cd40115
TTL SN 54S00

Abstract: No abstract text available
Text: . J PACKAGE SN 54LS00, SN 54S00 . . . J OR W PACKAG E SN 7400 . . . N PACKAG E SN 74LS00 , SN , - 1 2 . locilC » d ia a r d m il Pin n u m b e rs s h o w n a re fo r D , J , a n d N p , , SN74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES recommended operating conditions SN 74LS00 SN 54LS00 , operating free-air temperature range (unless otherwise noted) SN 54LS00 PARAM ETER SN 74LS00 U N IT


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PDF SN5400, SN54LS00, SIU54S00, SN7400, SN74LS00, SN74S00 54LS00, 54S00 74LS00, 74S00 TTL SN 54S00
74ls163 function table

Abstract: 74LS163 pin diagram of 74ls00 pin configuration 74LS10 74LS00 clock frequency 1324NS 74LS00 function table 74LS04 LS163A SYNCHRONOUS LOAD CLEAR ENABLE COUNTER
Text: GD54/74LS163A SYNCHRONOUS 4-BIT COUNTER: BINARY, SYNCHRONOUS CLEAR Feature • Internal Look-Ahead for Fast Counting • Carry Output for n-Bit Cascading • Synchronous Counting • Synchronously Programmable • Load Control Line • Diode-Clamped Inputs Pin Configuration Ripple OUTP Carry -— vcc OUTPUT qa qb re RR R ENABLE T LOAD R Ripple Qa Carry Output CLEAR CK ENABLE T , . Inhibit CLEAR OUTPUTS ^ Application Example VARIABLE MODULO COUNTER 1/6 74LS04 or 1/4 74LS00 or1/3


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PDF GD54/74LS163A LS163A. 74ls163 function table 74LS163 pin diagram of 74ls00 pin configuration 74LS10 74LS00 clock frequency 1324NS 74LS00 function table 74LS04 LS163A SYNCHRONOUS LOAD CLEAR ENABLE COUNTER
2008 - pin diagram of ic 74ls00

Abstract: 74LS00 uv 709 pin diagram of 74ls00
Text: MODES q DOUBLE-BUFFERED INPUT REGISTER CONFIGURATION q VOUT AND IOUT MODELS q HIGH ACCURACY: Linearity , 24- pin hermetic DIPs. Input coding is Binary Two's Complement (bipolar) or Unipolar Straight Binary , PACKAGE 28- Pin Plastic DBL Wide DIP 28- Pin Plastic DBL Wide DIP 28LD Side Brazed Hermetic Dip 28LD Side , , DAC709) . Indefinite Short to COMMON External Voltage Applied to RF ( pin 13 or 14, DAC708) . ±18V External Voltage Applied to D/A Output ( pin 1, DAC707; pin 14


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PDF DAC707 DAC708 DAC709 16-BIT DAC707JP/KP) DAC709 16bit pin diagram of ic 74ls00 74LS00 uv 709 pin diagram of 74ls00
2007 - 74LS00

Abstract: specification of 74ls00 74HTC
Text: MODES q DOUBLE-BUFFERED INPUT REGISTER CONFIGURATION q VOUT AND IOUT MODELS q HIGH ACCURACY: Linearity , 24- pin hermetic DIPs. Input coding is Binary Two's Complement (bipolar) or Unipolar Straight Binary , PACKAGE 28- Pin Plastic DBL Wide DIP 28- Pin Plastic DBL Wide DIP 28LD Side Brazed Hermetic Dip 28LD Side , , DAC709) . Indefinite Short to COMMON External Voltage Applied to RF ( pin 13 or 14, DAC708) . ±18V External Voltage Applied to D/A Output ( pin 1, DAC707; pin 14


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PDF DAC707 DAC708 DAC709 16-BIT DAC707JP/KP) DAC709 16bit 74LS00 specification of 74ls00 74HTC
Not Available

Abstract: No abstract text available
Text: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/ 74LS00 . They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet in­ dustry and military specifications. Pin Configuration u 1 [T A m vcc [T 73] 4B 1Y [T Tj~| 4A 2A [T TT| 4Y 2B [F ~ 1 3B ÏÔ 2Y [T ~9~1 3 A GND [T ~8~] 3 Y 1B


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PDF GD54/74HC00, GD54/74HCT00 54/74LS00.
74ls163 function table

Abstract: No abstract text available
Text: GD54/74LS163A SYNCHRONOUS 4-BIT COUNTER: BINARY, SYNCHRONOUS CLEAR Feature • • • • • • Pin Configuration Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Load Control Line Diode-Clamped Inputs Ripple Carry Vcc OUTP U T O UTPUTS - — -ENABLE O. Qe Qc Qp T LOAD , to inputs of GATE 3 Qc 6 Qa Qc 7 Q b Qc 9 1/6 74LS04 or1/4 74LS00 or1


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PDF GD54/74LS163A 000424G 74ls163 function table
2006 - pin diagram of ic 74ls00

Abstract: IC TTL 74LS00 74HTC TTL 74ls00 lead side brazed hermetic analog devices ic 74LS00 74LS00 op amp 709 datasheet of ic 74ls00 pin diagram of 74ls00
Text: INPUT REGISTER CONFIGURATION q VOUT AND IOUT MODELS q LOW COST PLASTIC VERSIONS AVAILABLE , are in 24- pin hermetic DIPs. Input coding is Binary Two's Complement (bipolar) or Unipolar Straight , DRAWING NUMBER(1) DAC707JP DAC707KP 28- Pin Plastic DBL Wide DIP 28- Pin Plastic DBL Wide DIP , , DAC709) . Indefinite Short to COMMON External Voltage Applied to RF ( pin 13 or 14, DAC708) . ±18V External Voltage Applied to D/A Output ( pin 1, DAC707; pin 14


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PDF DAC707 DAC708 DAC709 16-BIT DAC707JP/KP) DAC708 DAC709 16bit pin diagram of ic 74ls00 IC TTL 74LS00 74HTC TTL 74ls00 lead side brazed hermetic analog devices ic 74LS00 74LS00 op amp 709 datasheet of ic 74ls00 pin diagram of 74ls00
2009 - pin diagram of ic 74ls00

Abstract: pin diagram of 74ls00 DAC707 74LS00 709b DAC708 DAC709 7407 connection diagram
Text: INPUT REGISTER CONFIGURATION q VOUT AND IOUT MODELS q LOW COST PLASTIC VERSIONS AVAILABLE , are in 24- pin hermetic DIPs. Input coding is Binary Two's Complement (bipolar) or Unipolar Straight , DRAWING NUMBER(1) DAC707JP DAC707KP 28- Pin Plastic DBL Wide DIP 28- Pin Plastic DBL Wide DIP , , DAC709) . Indefinite Short to COMMON External Voltage Applied to RF ( pin 13 or 14, DAC708) . ±18V External Voltage Applied to D/A Output ( pin 1, DAC707; pin 14


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PDF DAC707 DAC708 DAC709 16-BIT DAC707JP/KP) DAC708 DAC709 16bit pin diagram of ic 74ls00 pin diagram of 74ls00 DAC707 74LS00 709b 7407 connection diagram
2009 - Not Available

Abstract: No abstract text available
Text: DOUBLE-BUFFERED INPUT REGISTER CONFIGURATION q VOUT AND IOUT MODELS q LOW COST PLASTIC VERSIONS AVAILABLE , are in 24- pin hermetic DIPs. Input coding is Binary Two’s Complement (bipolar) or Unipolar Straight , ) DAC707JP DAC707KP 28- Pin Plastic DBL Wide DIP 28- Pin Plastic DBL Wide DIP 215 215 DAC707BH , ) . Indefinite Short to COMMON External Voltage Applied to RF ( pin 13 or 14, DAC708) . ±18V External Voltage Applied to D/A Output ( pin 1, DAC707; pin 14, DAC709


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PDF DAC707 DAC708 DAC709 16-BIT DAC707JP/KP) DAC708 DAC709 16bit
2003 - 74LS00

Abstract: DAC707 DAC708 DAC709
Text: INPUT REGISTER CONFIGURATION q VOUT AND IOUT MODELS q LOW COST PLASTIC VERSIONS AVAILABLE , are in 24- pin hermetic DIPs. Input coding is Binary Two's Complement (bipolar) or Unipolar Straight , DRAWING NUMBER(1) DAC707JP DAC707KP 28- Pin Plastic DBL Wide DIP 28- Pin Plastic DBL Wide DIP , , DAC709) . Indefinite Short to COMMON External Voltage Applied to RF ( pin 13 or 14, DAC708) . ±18V External Voltage Applied to D/A Output ( pin 1, DAC707; pin 14


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PDF DAC707 DAC708 DAC709 16-BIT DAC707JP/KP) DAC708 DAC709 16bit 74LS00 DAC707
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