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phy interface for the PCI Express Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2008 - MO-205

Abstract: PX1011B dc/tx/1/2/1257/PX1011B
Text: PXPIPE interface . Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE , between the MAC and PX1011B is a superset of the PHY Interface for the PCI Express (PIPE) specification , Loop PIPE PHY Interface for the PCI Express PVT Process Voltage Temperature S2P , ] PCI Express Base Specification - Rev. 1.0a - PCISIG [2] PHY Interface for the PCI Express , PCI Express PHY supports advanced power management functions. The PX1011BI is for the industrial


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PDF PX1011B PX1011B 8b/10b MO-205 dc/tx/1/2/1257/PX1011B
2012 - Not Available

Abstract: No abstract text available
Text: Product Overview GENERAL DESCRIPTION The GL9714 is a 4-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base Specification rev. 1.0a and Intel’s PHY Interface for the PCI Express , ‚·  Complies with PCI Express Base Specification rev. 1.1 Complies with Intel’s PHY Interface for PCI Express Architecture rev. 1.0 Integrates quad 2.5 gigabit per second (Gbps) Serializer , deserialization for each lane. The quad SerDes in the GL9714 supports an effective serial interface speed (2.5 Gb


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PDF GL9714 GL9714 16-bit
2012 - Not Available

Abstract: No abstract text available
Text: The GL9711 is a 1-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base Specification rev. 1.0a and Intel’s PHY Interface for the PCI Express Architecture rev. 1.0. It integrates one , with Intel’s PHY Interface for PCI Express Architecture rev. 1.0 Integrates 2.5 gigabit per second , Genesys Logic, Inc. GL9711 PCI ExpressTM PIPE x1 PHY Product Overview GL9711 Datasheet , effective serial interface speed (2.5 Gb/s) of data bandwidth, intended for use in ultrahigh-speed


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PDF GL9711 GL9711 16-bit
2008 - Not Available

Abstract: No abstract text available
Text: PXPIPE interface . Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE , between the MAC and PX1011B is a superset of the PHY Interface for the PCI Express (PIPE) specification , PLL Phase-Locked Loop PIPE PHY Interface for the PCI Express PVT Process Voltage , . References [1] PCI Express Base Specification — Rev. 1.0a - PCISIG [2] PHY Interface for the PCI , PCI Express PHY supports advanced power management functions. The PX1011BI is for the industrial


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PDF PX1011B PX1011B 8b/10b
2008 - smd marking g8

Abstract: smd marking e5 5Pin smd transistor marking j6 SMD 5pin code E2 marking code E5 SMD ic smd marking code g8 Diode smd f6 PHY Interface for the PCI Express marking code C3 SMD ic smd transistor s2p
Text: PXPIPE interface . Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE , is a superset of the PHY Interface for the PCI Express (PIPE) specification. The following feature , Loop PIPE PHY Interface for the PCI Express PVT Process Voltage Temperature S2P , ] PCI Express Base Specification - Rev. 1.0a - PCISIG [2] PHY Interface for the PCI Express , PCI Express PHY supports advanced power management functions. The PX1011BI is for the industrial


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PDF PX1011B PX1011B 8b/10b smd marking g8 smd marking e5 5Pin smd transistor marking j6 SMD 5pin code E2 marking code E5 SMD ic smd marking code g8 Diode smd f6 PHY Interface for the PCI Express marking code C3 SMD ic smd transistor s2p
2009 - marking code E5 SMD ic

Abstract: smd marking code g8 smd marking g8 phy interface for the PCI Express MO-205 PX1011B MARKING G3 5pin
Text: PXPIPE interface . Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE , is a superset of the PHY Interface for the PCI Express (PIPE) specification. The following feature , Sub-layer PHY PHYsical layer PLL Phase-Locked Loop PIPE PHY Interface for the PCI Express , PCI Express PHY supports advanced power management functions. The PX1011BI is for the industrial , (BER) 2.2 PHY /MAC interface I I I I Based on Intel PHY Interface for PCI Express architecture


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PDF PX1011B PX1011B 8b/10b marking code E5 SMD ic smd marking code g8 smd marking g8 phy interface for the PCI Express MO-205 MARKING G3 5pin
2006 - PHY Interface for the PCI Express

Abstract: ic smd 1012a PX1011A-EL1/G X0SM-57BRE.7.3728M PX1011A PX1011A-EL1 top RXZ smd marking e5 5Pin
Text: between the MAC and PX1011A/1012A is a superset of the PHY Interface for the PCI Express (PIPE , Based on Intel PHY Interface for PCI Express architecture v1.0 (PIPE) Adapted for off-chip with , electrical PHYsical layer ( PHY ) that handles the low level PCI Express protocol and signaling. The PX1011A/1012A PCI Express PHY is compliant to the PCI Express Base Specification, Rev. 1.0a, and Rev. 1.1. The , PHY with 8-bit data PXPIPE interface . Its PXPIPE interface is a superset of the PHY Interface for the


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PDF PX1011A/PX1012A PX1011A/PX1012A PX1011A/1012A 8b/10b PX1011A PX1012A PHY Interface for the PCI Express ic smd 1012a PX1011A-EL1/G X0SM-57BRE.7.3728M PX1011A-EL1 top RXZ smd marking e5 5Pin
2011 - history of rome

Abstract: PHY Interface for the PCI Express AEC-Q100 MO-205 PX1011B MARKING CODE E5 NXP
Text: PXPIPE interface . Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE , PCI Express PHY supports advanced power management functions. The PX1011BI is for the industrial , interface Based on Intel PHY Interface for PCI Express architecture v1.0 (PIPE) Adapted for off-chip with , detection. The PXPIPE interface between the MAC and PX1011B is a superset of the PHY Interface for the PCI , PHYsical layer ( PHY ) that handles the low level PCI Express protocol and signaling. The PX1011B PCI


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PDF PX1011B PX1011B 8b/10b history of rome PHY Interface for the PCI Express AEC-Q100 MO-205 MARKING CODE E5 NXP
2007 - PHY Interface for the PCI Express

Abstract: PX1041A MO-205 sot631 PX1041A-EL1
Text: -bit data PXPIPE interface . Its PXPIPE interface is a superset of the PHY Interface for the PCI Express , (optional) 2.2 PHY /MAC interface I Based on Intel PHY Interface for PCI Express architecture v2.0 (PIPE , detection. The PXPIPE interface between the MAC and PX1041A is a superset of the PHY Interface for the PCI , Semiconductors PCI Express stand-alone X4 PHY The JTAG interface is a 3.3 V CMOS signaling. JTAG TRST_N , PHYsical layer ( PHY ) that handles the low level PCI Express protocol and signaling. The PX1041A PCI


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PDF PX1041A PX1041A 8b/10b PHY Interface for the PCI Express MO-205 sot631 PX1041A-EL1
2006 - ic smd 1012a

Abstract: phy interface for the PCI Express
Text: PXPIPE interface . Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE , PX1011A/1012A is a superset of the PHY Interface for the PCI Express (PIPE) specification. The following , Phase-Locked Loop PHY Interface for the PCI Express Process Voltage Temperature Serial to Parallel Serializer , Express Base Specification - Rev. 1.0a - PCISIG PHY Interface for the PCI Express Architecture (PIPE , /1012A PCI Express PHY supports advanced power management functions. The PX1011AI/PX1012AI is for the


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PDF 807IRELESS PX1011A PX1012A ic smd 1012a phy interface for the PCI Express
2011 - Not Available

Abstract: No abstract text available
Text: Control (MAC) layer devices. The PX1011B is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface . Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE) specification , PX1011B is a superset of the PHY Interface for the PCI Express (PIPE) specification. The following feature , Loop PHY Interface for the PCI Express Process Voltage Temperature Serial to Parallel Serializer and , Specification - Rev. 1.0a - PCISIG PHY Interface for the PCI Express Architecture (PIPE) Specification Version


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PDF PX1011B PX1011B 8b/10b
2008 - XI02000A

Abstract: PCI express PCB footprint XIO3130 pci root complex XIO2000A XIO2000AGZZ XIO2000AZHH XIO2000AZZZ XIO2200A XIO2200AGGW
Text: Express serial link using a modified version of the PHY interface for the PCI Express (PIPE) architecture , ' PCI Express bridge chip, the XIO2000A, is an industry first. It is designed for seamless migration from the legacy PCI to the PCI Express interface . It bridges a x1 PCI Express bus to a 32-bit, 33-/66 , Express rates of 2.5 Gbps. Its architecture supports the PCI 2.3 interface . The chip's design enables PC , Gbps 2.5 Gbps x1 PCI Express upstream PHY interface Digital link layer Transaction layer


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PDF XIO2000A 100-MHz 125-MHz 66-MHz/32-bit XI02000A PCI express PCB footprint XIO3130 pci root complex XIO2000AGZZ XIO2000AZHH XIO2000AZZZ XIO2200A XIO2200AGGW
2007 - AN10373

Abstract: ddr phy interface TI-XIO1100 ddr phy PX1011A XIO1100 TIXIO1100 analog buffers Texas instruments 8-bit altera board
Text: Preliminary External PHY Support in PCI Express MegaCore Functions The Intel PIPE Interface PIPE stands for PHY Interface for the PCI Express Architecture. The PIPE specification was developed by Intel , PHY Interface Modes Clocking Figure 4 shows the clocking for PCI Express MegaCore functions when , provides an introduction to the PIPE interface and focuses on external PHY support in the PCI Express , between the PHY and the MAC layers (Figure 1). Figure 1. PIPE Interface PCI Express MegaCore


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PDF
2003 - PCI-EXP-T42G5-N1

Abstract: pci express dllp serdes tutorial pci express tlp ORT42G5 ORT82G5 parallel scrambler PCI dllp phy interface for the PCI Express
Text: Detection section in " PHY Interface for the PCI Express Architecture". 3. For usage of loc_lnk_cntl and , Packet Type Note2: 1. For all PCI Express Line Interface signals (both input and output) refer to the , Receive TLP interface to the transaction layer. 3 Lattice Semiconductor PCI Express Receive , platforms. The basic premise of PCI Express is that the host PCI software remains compatible with an , 4 ORT42G5 FPSC. The complete solution supports up to 2.5Gbps data rate as specified in PCI Express


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PDF 8b/10b ORT42G5-2BM484. PCI-EXP-T42G5-N1. PCI-EXP-T42G5-N1 pci express dllp serdes tutorial pci express tlp ORT42G5 ORT82G5 parallel scrambler PCI dllp phy interface for the PCI Express
dllp

Abstract: pci express dllp pci express serial parallel port circuit diagram PCI express switch pci express tlp ORT42G5 ORT82G5
Text: implemented to provide endpoint interface to an application running in the Transaction layer. The PCI Express , part of the training process. The core follows the steps as specified in the PCI Express spec 1.0a for , is transmitted from the core into the PCI Express Link. The Credit Available (CA) value for 8 , ACKD_SEQ) mod 4096 => 2048 Refer to Figures 3-17 in the PCI Express Specification 1.0a for more details , Interface . Register Description PCI Express configuration space is not implemented in this core. But the


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PDF ipug25 1-800-LATTICE dllp pci express dllp pci express serial parallel port circuit diagram PCI express switch pci express tlp ORT42G5 ORT82G5
2006 - Not Available

Abstract: No abstract text available
Text: PHY CHAPTER 1 GENERAL DESCRIPTION The GL9714 is a 4-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base Specification rev. 1.0a and Intel’s PHY Interface for the , Specification rev. 1.0a l Complies with Intel’s PHY Interface for PCI Express Architecture rev. 1.0 l , Page 16 GL9714 PCI ExpressTM PIPE x4 PHY for calibrating the on-chip termination resistors TXNA~D , configured into an x4 lane, 8-bit parallel bus and acts as a 4-lane PCI Express PHY . The parallel bus is


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PDF GL9714 GL9714 GL9714-TgGxx 233-pin
2006 - Not Available

Abstract: No abstract text available
Text: PHY CHAPTER 1 GENERAL DESCRIPTION The GL9711 is a 1-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base Specification rev. 1.0a and Intel’s PHY Interface for the PCI Express Architecture rev. 1.0. It integrates one SerDes and the Physical Coding Sublayer (PCS , ExpressTM PIPE x1 PHY CHAPTER 2 FEATURES l Complies with PCI Express Base Specification rev. 1.0a l Complies with Intel’s PHY Interface for PCI Express Architecture rev. 1.0 l


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PDF GL9711 GL9711 233-pin
2007 - gl9714

Abstract: trx 434 GL9714 GREEN gl9714-tggxx TXPA BCN11 PCI-Express 2.0 X8 connector Pinout TDB2 Genesys Logic
Text: x4 PHY CHAPTER 1 GENERAL DESCRIPTION The GL9714 is a 4-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base Specification rev. 1.0a and Intel's PHY Interface for the PCI , Complies with Intel's PHY Interface for PCI Express Architecture rev. 1.0 Integrates quad 2.5 gigabit per , . Description Page 16 GL9714 PCI ExpressTM PIPE x4 PHY for calibrating the on-chip termination resistors , deserialization for each lane. The quad SerDes in the GL9714 supports an effective serial interface speed (2.5 Gb


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PDF GL9714 GL9714 GL9714-TgGxx 233-pin trx 434 GL9714 GREEN gl9714-tggxx TXPA BCN11 PCI-Express 2.0 X8 connector Pinout TDB2 Genesys Logic
2005 - Not Available

Abstract: No abstract text available
Text: PHY CHAPTER 1 GENERAL DESCRIPTION The GL9714 is a 4-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base Specification rev. 1.0a and Intel’s PHY Interface for the PCI Express Architecture rev. 1.0. It integrates a quad SerDes and the Physical Coding Sublayer (PCS , Specification rev. 1.0a. l Complies with Intel’s PHY Interface for PCI Express Architecture rev. 1.0 , configured into an x4 lane, 8-bit parallel bus and acts as a 4-lane PCI Express PHY . The parallel bus is


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PDF GL9714 GL9714 233-pin
2006 - Not Available

Abstract: No abstract text available
Text: PHY CHAPTER 1 GENERAL DESCRIPTION The GL9714 is a 4-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base Specification rev. 1.0a and Intel’s PHY Interface for the , Specification rev. 1.0a l Complies with Intel’s PHY Interface for PCI Express Architecture rev. 1.0 l , Page 16 GL9714 PCI ExpressTM PIPE x4 PHY for calibrating the on-chip termination resistors TXNA~D , configured into an x4 lane, 8-bit parallel bus and acts as a 4-lane PCI Express PHY . The parallel bus is


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PDF GL9714 GL9714 233-pin
2006 - LFBGA-233

Abstract: GL9711 BCN18 CH-610 101 R15 N 101 JT genesys PCI-Express 2.0 X8 connector Pinout smd diode code T9 smd diode K10 BCN158
Text: CHAPTER 1 GENERAL DESCRIPTION The GL9711 is a 1-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base Specification rev. 1.0a and Intel's PHY Interface for the PCI Express , Intel's PHY Interface for PCI Express Architecture rev. 1.0 l Integrates 2.5 gigabit per second , PCI ExpressTM PIPE x1 PHY VSSGR C15 P Ground for the guard ring of the SerDes block , GL9711 PCI ExpressTM PIPE x1 PHY SMBus uses fixed voltage levels to define the logic "ZERO" and logic


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PDF GL9711 GL9711 GL9711-TgGXX 233-pin LFBGA-233 BCN18 CH-610 101 R15 N 101 JT genesys PCI-Express 2.0 X8 connector Pinout smd diode code T9 smd diode K10 BCN158
2006 - et1310

Abstract: pci express mini card electromechanical specification L-ET1310R1B1-M agere et2008 ET1011 Analog devices TOP marking Information D 8H X3-230-1994 woke on lan 5A02 Gigabit Ethernet PHY
Text: lowering cost for both LOM and NIC applications. Designed specifically for PCI Express , the ET1310 , the PCI Express link provide native support for QoS transmission for real-time and multimedia , the PCI Express link. The PCI Express receive and transmit blocks are responsible for transactions , Gbits/s. The PCI Express PHY also implements the beacon function, which is active during low-power , , these blocks perform the parallel-to-serial and serial-to-parallel conversion for the PCI Express


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PDF ET1310 DS06-153GPHY DS06-012GPHY) pci express mini card electromechanical specification L-ET1310R1B1-M agere et2008 ET1011 Analog devices TOP marking Information D 8H X3-230-1994 woke on lan 5A02 Gigabit Ethernet PHY
2006 - ET1310

Abstract: LinkUp Systems Corporation AT24CXX et412
Text: management for PCI Express Physical: - Pin compatible with the ET1310 PCI Express Gigabit Ethernet , technology and a high-performance, standards-compliant PCI Express 1.0a host system interface . The ET1301 is , PCI Express as the industry-standard host interface . The ET1301 is targeted at power-conscious mobile , and NIC applications. Designed specifically for PCI Express , the ET1301 architecture leverages the , ) Multiple traffic classes per virtual channel on the PCI Express link provide native support for QoS


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PDF ET1301 M-553-2448, DS06-129GPHY DS05-137GPHY) ET1310 LinkUp Systems Corporation AT24CXX et412
2005 - et1310

Abstract: AT24CXX Gigabit Ethernet MAC phy
Text: transition to PCI Express as the industry-standard host interface . The ET1310-M is targeted at , traffic classes per virtual channel on the PCI Express link provide native support for QoS transmission , the gigabit Ethernet PHY . They are discussed separately in this document Q Q Q PCI Express , are responsible for transactions between the Host Controller subsystem and the PCI Express core logic , operates at a raw signaling rate of 2.5 Gbits/s. The PCI Express PHY also implements the beacon function


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PDF ET1310 DS05-041GPHY DS04-229GPHY) AT24CXX Gigabit Ethernet MAC phy
2007 - Not Available

Abstract: No abstract text available
Text: PIPE x4 PHY CHAPTER 1 GENERAL DESCRIPTION The GL9714 is a 4-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base Specification rev. 1.0a and Intel’s PHY Interface for the PCI Express Architecture rev. 1.0. It integrates a quad SerDes and the Physical Coding Sublayer (PCS , . 1.0a Complies with Intel’s PHY Interface for PCI Express Architecture rev. 1.0 Integrates quad 2.5 , . Description Page 16 GL9714 PCI ExpressTM PIPE x4 PHY for calibrating the on-chip termination resistors


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PDF GL9714 GL9714 GL9714-TgGxx 233-pin
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