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LT1528CQ Linear Technology LT1528 - 3A Low Dropout Regulator for Microprocessor Applications; Package: DD PAK; Pins: 5; Temperature Range: 0°C to 70°C
LT1528CQ#TR Linear Technology LT1528 - 3A Low Dropout Regulator for Microprocessor Applications; Package: DD PAK; Pins: 5; Temperature Range: 0°C to 70°C
LT1528CT#PBF Linear Technology LT1528 - 3A Low Dropout Regulator for Microprocessor Applications; Package: TO-220; Pins: 5; Temperature Range: 0°C to 70°C
LT1528CQ#PBF Linear Technology LT1528 - 3A Low Dropout Regulator for Microprocessor Applications; Package: DD PAK; Pins: 5; Temperature Range: 0°C to 70°C
LT1528CT Linear Technology LT1528 - 3A Low Dropout Regulator for Microprocessor Applications; Package: TO-220; Pins: 5; Temperature Range: 0°C to 70°C
LT1528CQ#TRPBF Linear Technology LT1528 - 3A Low Dropout Regulator for Microprocessor Applications; Package: DD PAK; Pins: 5; Temperature Range: 0°C to 70°C

philips application manchester verilog Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1998 - AN070

Abstract: philips application manchester manchester code verilog manchester verilog decoder manchester encoder an070
Text: Semiconductors Application note Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs , Application note Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs AN070 Table , Philips Semiconductors Application note Verilog implementation of a Manchester Encoder/Decoder in , Semiconductors Application note Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs , Application note Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs 1. The pattern


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PDF AN070 AN070 philips application manchester manchester code verilog manchester verilog decoder manchester encoder an070
1998 - manchester verilog decoder

Abstract: manchester encoder an070 manchester code verilog Verilog implementation of a Manchester Encoder/Decoder philips application manchester philips application manchester verilog AN070 manchester encoder verilog code for uart communication manchester code
Text: Semiconductors Application note Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs , Application note Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs AN070 Table , Philips Semiconductors Application note Verilog implementation of a Manchester Encoder/Decoder in , Semiconductors Application note Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs , Application note Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs 1. The pattern


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PDF AN070 manchester verilog decoder manchester encoder an070 manchester code verilog Verilog implementation of a Manchester Encoder/Decoder philips application manchester philips application manchester verilog AN070 manchester encoder verilog code for uart communication manchester code
manchester verilog decoder

Abstract: DK20-9.5/110/124 manchester code verilog MD1010
Text: Philips Semiconductors Application note Verilog implementation of a Manchester Encoder , Semiconductors Application note Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs , Semiconductors Application note Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs , Philips Semiconductors Application note Verilog implementation of a Manchester Encoder/Decoder in , . Manchester Encoder 1997 May 14 414 Philips Semiconductors Application note Verilog


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PDF mda0101010101 4400lrst manchester verilog decoder DK20-9.5/110/124 manchester code verilog MD1010
1999 - philips application manchester verilog

Abstract: vhdl code manchester encoder philips application manchester XAPP324 PZ3032CS10BC manchester code verilog vhdl manchester encoder XPLA1
Text: APPLICATION NOTE Xilinx has acquired the entire Philips CoolRunner Low Power CPLD Product Family , Designer-XL Design Flow for Philips CPLDs 1999 Jan 29 Philips Semiconductors Application note , Philips tool dino can be used to translate the gate-level Verilog to edif. Then XPLA Designer-XL accepts , ., including BuildGates. 1999 Jan 29 2 Simulator Philips Semiconductors Application note , no_buffer_at_integraton_level true 1999 Jan 29 3 Philips Semiconductors Application note Ambit - XPLA Designer-XL


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PDF XAPP324 philips application manchester verilog vhdl code manchester encoder philips application manchester XAPP324 PZ3032CS10BC manchester code verilog vhdl manchester encoder XPLA1
1998 - vhdl code for manchester decoder

Abstract: easy examples of vhdl program vhdl code manchester encoder vhdl manchester AN078 vhdl manchester encoder manchester code verilog manchester verilog decoder vhdl code for D Flipflop synchronous Verilog implementation of a Manchester Encoder/Decoder
Text: PZ3032 complex programmable logic device.This design is a manchester decoder. See Philips application , APPLICATION NOTE AN078 VHDL EASY Design Flow for Philips CPLDs 1998 Jul 02 Philips Semiconductors Application note VHDL Easy Design Flow for Philips CPLDs AN078 INTRODUCTION This , support for the design flow described in this application note is provided by: Philips Technical , for the source code for the Manchester decoder. (1) Philips acknowledges the trademarks of the


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PDF AN078 vhdl code for manchester decoder easy examples of vhdl program vhdl code manchester encoder vhdl manchester AN078 vhdl manchester encoder manchester code verilog manchester verilog decoder vhdl code for D Flipflop synchronous Verilog implementation of a Manchester Encoder/Decoder
vhdl code for manchester decoder

Abstract: easy examples of vhdl program vhdl code manchester encoder vhdl manchester vhdl code for accumulator Verilog implementation of a Manchester Encoder/Decoder
Text: logic device.This design is a manchester decoder. See Philips application note, VHDL Implementation of a , Philips Semiconductors Application note VHDL Easy Design Flow for Philips AN078 CPLDs , . Technical support for the design flow described in this application note is provided by: Philips Technical , 02 568 Philips Semiconductors Application note VHDL Easy Design Flow for Philips CPLDs , Philips Semiconductors Application note VHDL Easy Design Flow for Philips AND7A CPLDs


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PDF AN078 vhdl code for manchester decoder easy examples of vhdl program vhdl code manchester encoder vhdl manchester vhdl code for accumulator Verilog implementation of a Manchester Encoder/Decoder
2008 - Bluetooth Jammer

Abstract: slot jammer rf verilog manchester coding jammer samsung bluetooth manchester code verilog TDA523x microtec user guide TDA5230 FCC15
Text: SmartLEWISTM Receiver TDA5230 Preliminary Application Note V1.0 Wireless Control Edition , herein, any typical values stated herein and/or any information regarding the application of the device , , SolarisTM of Sun Microsystems, Inc. Philips ®, I2C-Bus® of Koninklijke Philips Electronics N.V. Epson® of , . Zetex® of Zetex Semiconductors. RohmTM of Rohm Co., Ltd. Microtec® of Microtec Research, Inc. Verilog , .10 Preliminary Application Note 4 V1.0, 2008-11-01 Protocol Examples Protocol Examples


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PDF TDA5230 10kBit 10kBit 50kHz 104Bit TDA523x: Bluetooth Jammer slot jammer rf verilog manchester coding jammer samsung bluetooth manchester code verilog TDA523x microtec user guide TDA5230 FCC15
1998 - decoder in verilog with waveforms and report

Abstract: philips designer guide verilog code for correlate Philips applications pic 16 f 888 AN058 TQFP-44-P32 16HF80
Text: APPLICATION NOTE AN058 Cadence/Synopsys Design Flows for targeting Philips CPLDs 1997 May 22 Philips Semiconductors Preliminary Application note Cadence/Synopsys Design Flows for targeting , User's Guide. 1997 May22 2 Philips Semiconductors Preliminary Application note Cadence , delay-annotated verilog model from the jedec file. To use Synopsys for Philips CPLDs, the .synopsys_dc.setup , Philips Semiconductors Preliminary Application note Cadence/Synopsys Design Flows for targeting


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PDF AN058 PZ5000 PZ3000 decoder in verilog with waveforms and report philips designer guide verilog code for correlate Philips applications pic 16 f 888 AN058 TQFP-44-P32 16HF80
5 to 32 decoder using 3 to 8 decoder verilog

Abstract: verilog code for correlate philips designer guide decoder in verilog with waveforms and report pic 16 f 888 16HF80
Text: /data/ verilog / 1997 May 22 322 Philips Semiconductors Application note Cadence/Synopsys , Philips Semiconductors Application note Cadence/Synopsys Design Flows for targeting Philips , May 22 319 Philips Semiconductors Application note Cadence/Synopsys Design Flows for , "POWER_1"; edifout_ground_name = "POWER_0"; 1997 May 22 320 Philips Semiconductors Application note , Semiconductors Application note Cadence/Synopsys Design Flows for targeting Philips CPLDs plfit $1 plfuse


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PDF AN058 PZ5000 PZ3000 PZ5128/PZ3128 5 to 32 decoder using 3 to 8 decoder verilog verilog code for correlate philips designer guide decoder in verilog with waveforms and report pic 16 f 888 16HF80
1999 - Philips DATA Handbook system

Abstract: 12NC ordering code philips semiconductors 12NC philips
Text: capture ­ Philips Hardware Description Language (PHDL) ­ Verilog HDL ­ VHDL · Fitter support for , methods include schematic capture, Philips Hardware Description Language (PHDL), Verilog HDL, and VHDL , for any damages resulting from such application . Right to make changes - Philips Semiconductors , INTEGRATED CIRCUITS PZXPLAPRO Design tools for Philips Semiconductors CoolRunnert CPLDs Product specification IC27 Data Handbook Philips Semiconductors 1999 Jan 26 Philips


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PDF 22V10 100MHz Philips DATA Handbook system 12NC ordering code philips semiconductors 12NC philips
1998 - vhdl code program for 4-bit magnitude comparator

Abstract: vhdl code for 4 bit ripple COUNTER IEC wiring schematic symbols vhdl code for 8-bit serial adder vhdl code for BCD to binary adder vhdl code for asynchronous decade counter vhdl code for 8-bit BCD adder vhdl code for demultiplexer vhdl code manchester encoder data flow vhdl code for ripple counter
Text: a UART. See Philips application note "VHDL Implementation of a Manchester Encoder Decoder" for the , APPLICATION NOTE AN071 OrCAD Express Design Flow for Philips CPLDs 1998 Jul 21 Philips Semiconductors Application note OrCAD Express Design Flow for Philips CPLDs AN071 INTRODUCTION This , this application note is provided by: Philips Technical Assistance Telephone no. 888-coolpld web , Philips Semiconductors Application note OrCAD Express Design Flow for Philips CPLDs AN071


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PDF AN071 vhdl code program for 4-bit magnitude comparator vhdl code for 4 bit ripple COUNTER IEC wiring schematic symbols vhdl code for 8-bit serial adder vhdl code for BCD to binary adder vhdl code for asynchronous decade counter vhdl code for 8-bit BCD adder vhdl code for demultiplexer vhdl code manchester encoder data flow vhdl code for ripple counter
1990 - vhdl code for multiplexer 64 to 1 using 4 to 1

Abstract: vhdl code for multiplexer vhdl code for multiplexer 4 to 1 using 2 to 1 vhdl code for multiplexer 64 to 1 using 8 to 1
Text: APPLICATION NOTE AN059 Mentor Graphics Design Flow for targeting Philips CPLDs 1996 Sep 27 Philips Semiconductors Preliminary Application note Mentor Graphics Design Flow for targeting , can be used with minor edits for Verilog synthesis. For additional information, telephone Philips , Application note Mentor Graphics Design Flow for targeting Philips CPLDs AN059 Synthesis using the , Preliminary Application note Mentor Graphics Design Flow for targeting Philips CPLDs AN059 qvcom


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PDF AN059 PZ5000 PZ3000 vhdl code for multiplexer 64 to 1 using 4 to 1 vhdl code for multiplexer vhdl code for multiplexer 4 to 1 using 2 to 1 vhdl code for multiplexer 64 to 1 using 8 to 1
1997 - verilog code for johnson counter

Abstract: 2100 1BZ Q0011 Q1100 16HF80 1650 LD B1111 ps138 4bit verilog code for johnson counter Q1111
Text: APPLICATION NOTE CPLDs Verilog models of commonly used digital functions for targeting Philips , Verilog models of commonly used digital functions CPLDs INTRODUCTION This application note , =8'd5; b=8'd4 ; end 1997 May 22 3 CPLDs Philips Semiconductors Preliminary Verilog , 4 CPLDs Philips Semiconductors Preliminary Verilog models of commonly used digital , 'h0000 ; 1997 May 22 7 Philips Semiconductors Preliminary Verilog models of commonly used digital


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PDF 888-coreg verilog code for johnson counter 2100 1BZ Q0011 Q1100 16HF80 1650 LD B1111 ps138 4bit verilog code for johnson counter Q1111
an059

Abstract: No abstract text available
Text: Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips , edits for Verilog synthesis. For additional information, telephone Philips Applications Support at 888 , given. 1996 Sep 27 331 Philips Semiconductors Application note Mentor Graphics Design Flow for , Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips CPLDs , 27 333 Philips Semiconductors Application note Mentor Graphics Design Flow for targeting


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PDF AN059 PZ5000 P23000 32-macrocell PZ3032 PZ5032, PZ3064/PZ5064 an059
1998 - T 3055

Abstract: T-2135 transistor B1010 T1255 T1735 uart 2651 T4655
Text: Applicatins Engineer Philips Semiconductors 1997 May 21 Philips Semiconductors Application note , . This application note implements a UART in Philips CPLDs. UARTs are available as inexpensive standard , Semiconductors Application note Implementing a UART in Philips CPLDs AN072 DIRECTION SIGNAL , 'b0 ; #160 rxd = 1'b1 ; 1997 May 21 3 Philips Semiconductors Application note Implementing a , Semiconductors Application note Implementing a UART in Philips CPLDs AN072 rsr = 8'b0 ; rbr = 8


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PDF AN072 RS232. T 3055 T-2135 transistor B1010 T1255 T1735 uart 2651 T4655
2009 - verilog code for i2c

Abstract: ahb to i2c verilog code verilog code for I2C MASTER verilog code for I2C MASTER slave i2c master verilog code atmel 8051 i2c sample code ahb to i2c design implementation 8051 I2C PROTOCOL verilog code for amba ahb master 89C51IC2
Text: the Philips I2C Bus® specification version 2.1. It is compliant with the PVCI (Peripheral Virtual , of devices, therefore minimizing interconnections and usage of IC pins in the user application and , system configuration support Multimaster Mode Sophisticated self-checking Testbench ( Verilog versions use Verilog 2001) January 2009 Functional description Configurability The I2C-HS core is , Testbench ( Verilog versions use Verilog 2001) that instantiates the core, clock generator, bus/behavioral


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2009 - 89C51IC2

Abstract: 8051 THROUGH I2C PROTOCOL EP3SE50 ahb to i2c design implementation
Text: interface that meets the Philips I2C Bus® specification version 2.1. It is compliant with the PVCI , number of devices, therefore minimizing interconnections and usage of IC pins in the user application , ( Verilog versions use Verilog 2001) January 2009 Verification Functional description The I2C-HS , Post-synthesis EDIF netlist · Sophisticated self-checking Testbench ( Verilog versions use Verilog 2001) that , Bus Controller which provides a serial interface that meets the Philips I2C bus specification and


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2007 - verilog code for 16 bit ram

Abstract: ISP1501 communication control verilog code CUSB2 verilog hdl code for programmable peripheral interface Evatronix
Text: , support for the Philips ISP1501 transceiver, and a UTMI Low Pin Interface (ULPI). Designed for easy , microprocessors and bus architectures o Interrupt request signals for application microprocessor o Interrupt , Optional support for Philips ISP1501 USB2.0 Transceiver can be added before delivery Sophisticated self-checking Testbench ( Verilog versions use Verilog 2001) September 2007 Customization , from servicing USB control transfers. Support for the Philips ISP1501 transceiver is also available


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PDF ISP1501 verilog code for 16 bit ram communication control verilog code CUSB2 verilog hdl code for programmable peripheral interface Evatronix
2002 - RC500

Abstract: MF RC171 MF RC500 Mifare reader antenna design RC500 Mifare reader antenna design RC531 RC171 MF RC500 command MF CM200 MIFARE MAX490 schematic MF RC530
Text: INTEGRATED CIRCUITS MF RC500 Active Antenna Concept Revision 1.0 PUBLIC Philips Semiconductors March 2002 Philips Semiconductors Revision 1.0 March 2002 Active Antenna Concept , .14 PUBLIC 2 Philips Semiconductors Revision 1.0 March2002 Active Antenna Concept , configuration of the various blocks. The active antenna concept is applicable on all Philips contactless reader IC (MF RC530, MF RC531 & CL RC632). All the descriptions of MF RC500's application in this document


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PDF RC500 RC500 SCA74 MF RC171 MF RC500 Mifare reader antenna design RC500 Mifare reader antenna design RC531 RC171 MF RC500 command MF CM200 MIFARE MAX490 schematic MF RC530
1997 - Z80 usb interface

Abstract: generation of control signals in 89c51 micro Atmel 89C51 microcontroller micro controller 89c51 pin diagram of micro controller 89c51 FEATURES OF microcontroller 89C51 mc 89c51 89c51 atmel specification Z80 usb 89c51 controller
Text: error · External interface to Philips IPDIUSBP11 USB transceiver XC4000E CLBs Used 600 IOBs , XC4000E/CX5215 Datasheets Core documentation Sample files for top level module in Verilog HDL Design File Formats XNF Netlist Verilog Source RTL Available Verification Tool Verilog Schematic Symbols , implement Function controller, with micro controller interface. Reference designs & None application , Requirements Xilinx Core Tools XACTstep 5.2.1/6.0.1 Entry/Verification Tools Verilog RTL Additional


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PDF IPDIUSBP11 Z80 usb interface generation of control signals in 89c51 micro Atmel 89C51 microcontroller micro controller 89c51 pin diagram of micro controller 89c51 FEATURES OF microcontroller 89C51 mc 89c51 89c51 atmel specification Z80 usb 89c51 controller
1998 - schematic diagram of usb hub

Abstract: "USB Hub Controller" schematic diagram usb to video out HQ240 XC4000E usb-if
Text: Xilinx-based hub evaluation board is available from Inventra External interfaces to Philips IPDIUSBP11 USB , documentation Sample files for top level module in Verilog HDL Design File Formats XNF Netlist Verilog Source RTL Available Constraint Files Timespec, .cst, .tnm files Verification Tool Verilog Schematic , designs & None application notes Additional Items Firmware for microcontroller available for nominal cost Design Tool Requirements Xilinx Core Tools XACTstep 5.2.1/6.0.1 Entry/Verification Verilog


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2006 - NXP NFC antenna automatic impedance matching

Abstract: nfc indicator and target block diagram NFC antenna automatic impedance matching PN532 pn532 Protocol is mifare antenna soft pcb philips RC5 protocol PN532 SFR registers NxP PN532 nfc pcb antenna
Text: 2011 19 of 25 PN532/C1 Philips Semiconductors NFC controller 14. Application , Philips Electronics N.V. This specification can be ordered using the code 9398 393 40011. Application , resulting from such application . Right to make changes - Philips Semiconductors reserves the right to , FeliCaTM Higher Baudrates up to 424 kbaud in both directions. PN532/C1 Philips Semiconductors , data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 1.2 - 31 March


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PDF PN532/C1 PN532. PN532 80C51 4443A NXP NFC antenna automatic impedance matching nfc indicator and target block diagram NFC antenna automatic impedance matching pn532 Protocol is mifare antenna soft pcb philips RC5 protocol PN532 SFR registers NxP PN532 nfc pcb antenna
2009 - 3S100E-5

Abstract: 8051 THROUGH I2C PROTOCOL ahb to i2c design implementation 89C51IC2 "programmable clock" i2c texas ahb to i2c testbench of a transmitter in verilog
Text: the Philips I2C Bus® specification version 2.1. It is compliant with the PVCI (Peripheral Virtual , devices, therefore minimizing interconnections and usage of IC pins in the user application · I2C , support Multimaster Mode Sophisticated self-checking Testbench ( Verilog versions use Verilog 2001 , Sophisticated self-checking Testbench ( Verilog versions use Verilog 2001) that instantiates the core, clock , which provides a serial interface that meets the Philips I2C bus specification and supports all


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T 3055

Abstract: B1011 T1495 T2145
Text: Philips Semiconductors Application note Implementing a UART in Philips CPLDs Author Lester , communication over serial communication links as RS232. This application note implements a UART in Philips CPLDs , Application note Implementing a UART in Philips CPLDs AN072 SIGNAL rst dk16x rdn data[7:0] fe oe pe , ,"Verify resetAn"); Philips Semiconductors Application note Implementing a UART in Philips CPLDs , ) begin 1997 May 21 483 Philips Semiconductors Application note Implementing a UART in


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PDF RS232. b0001) b0010) b0011) b1010) b1011) b1100) b0000; T 3055 B1011 T1495 T2145
2006 - pn532

Abstract: TAS-3225A PN532 SFR registers pn532 Protocol is PN5321a3hn nfc antenna nfc indicator and target block diagram nfc antenna design 27.12Mhz PN5320A3HN
Text: January 2006 19 of 25 PN532/C1 Philips Semiconductors NFC controller 14. Application , for any damages resulting from such application . Purchase of Philips RC5 components Purchase of , FeliCaTM Higher Baudrates up to 424 kbaud in both directions. PN532/C1 Philips Semiconductors , data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 1.2 - 12 January 2006 2 of 25 PN532/C1 Philips Semiconductors NFC controller s Supported host


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PDF PN532/C1 PN532. PN532 80C51 4443A TAS-3225A PN532 SFR registers pn532 Protocol is PN5321a3hn nfc antenna nfc indicator and target block diagram nfc antenna design 27.12Mhz PN5320A3HN
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