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Part Manufacturer Description Datasheet Download Buy Part
LF398S8#TR Linear Technology LF398S - Precision Sample and Hold Amplifier in SO8 Package; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LF398S8#15 Linear Technology LF398S - Precision Sample and Hold Amplifier in SO8 Package; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LF398S8#TRPBF Linear Technology LF398S - Precision Sample and Hold Amplifier in SO8 Package; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LF398S8#PBF Linear Technology LF398S - Precision Sample and Hold Amplifier in SO8 Package; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LTC1064-1ACJ Linear Technology 50KHZ CLOCK SWEEPABLE CAUER FILT
LTC1068-200IG#TRPBF Linear Technology LTC1068 - Clock-Tunable, Quad Second Order, Filter Building Blocks; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C

pecl clock so8 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2004 - LCD 09151

Abstract: SCC2691AC1A28 SC28L198 PCF8591 APPLICATION CSOT109 PCK2002 PCA9552 HVQFN-56 PC133 registered reference design tSSOP10 Package
Text: Intended application LQFP-32 HVQFN-32 high-performance PECL clock distribution synchronous output enable SO-20 TSSOP-20 high-performance PECL clock distribution synchronous output enable; LVDS input compatible SO-20 TSSOP-20 high-performance PECL clock distribution LQFP-32 HVQFN-32 high-performance PECL clock distribution individual output enable; LVPECL input , -52 300 -40~+85 LQFP-52 high-performance PECL clock distribution 300 300 -40~+85


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2003 - SOP8 8002 Amplifier

Abstract: SCR s838 TRANSISTOR s838 4606 MOSFET INVERTER transistor SMD DK QB Marking Code SMD CM sot-23-5 4606 inverter reg SMD MOSFET DRIVE DATASHEET 4606 voltage regulator SOT-223-4 C5 87 EL34
Text: manufacturer of advanced, high performance communications, clock management, mixed signal, analog and power , product family includes precision frequency synthesizers, clock distribution and translation, multiplexers , low-data-rate RF communications to a system. The tiny SO-8 receivers require just three external components to , Adj. 3.0, 3.3, 5.0 3.3, 4.85, 5.0, 5.0 (0.5%) 3.0, 3.3, 4.85, 5.0 SO-8 Package, JA = 160 , 16V SO-8 Package, JA = 160°C/W 2.5V to 16V 48µA 48µA 48µA 48µA 48µA 100µA


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PDF TinyFE81090 M-0009 SOP8 8002 Amplifier SCR s838 TRANSISTOR s838 4606 MOSFET INVERTER transistor SMD DK QB Marking Code SMD CM sot-23-5 4606 inverter reg SMD MOSFET DRIVE DATASHEET 4606 voltage regulator SOT-223-4 C5 87 EL34
LQFP48

Abstract: 9952 OQ2541 LQFP-32 bicmos CGY2100 pecl clock so8 SO16 package OQ2545 TZA3001
Text: SO16 SO16 SO16 SO16 LQFP48 LQFP 32 LQFP 32 LQFP 32 LQFP48 SO8 LQFP 32 SO8 LQFP 32 SO8 LQFP 32 SO8 2488 OQ2541 LQFP48 LQFP48 2488 2488 , X X X X X X X X X Bare Die X Clock conversion 2.5 2.5 , AND CLOCK RECOVERY 155 NE/SA5224 LIMITING AMPLIFIER 622 TZA3031 LASERDRIVERS 622 , Level detect X X X E.R. control X X LP Filter CML/GTL CML/TTL PECL /TTL


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PDF TZA3031 TZA3001 TZA3041 OQ2545 CGY2111 OQ2535 OQ2536 TZA3004 OQ2541 TZA3034 LQFP48 9952 OQ2541 LQFP-32 bicmos CGY2100 pecl clock so8 SO16 package OQ2545 TZA3001
2003 - HLT22

Abstract: klt22
Text: Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPS I/O SPICE , MC10ELT22, MC100ELT22 5V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground , it ideal for applications which require the translation of a clock and a data signal. http://onsemi.com MARKING DIAGRAMS* 8 1 SO-8 D SUFFIX CASE 751 8 HLT22 ALYW 1 1 8 KLT22 ALYW · · · · · · 1.2


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PDF MC10ELT22, MC100ELT22 MC10ELT/100ELT22 ELT22 HLT22 KLT22 AND8020 AN1404 AN1405 AN1406
2005 - Not Available

Abstract: No abstract text available
Text: Supports DC to 625 MHz operation HSTL compatible differential clock outputs PECL compatible differential , -lead Pb-free package available MC100ES8011P 1:2 DIFFERENTIAL PECL TO HSTL CLOCK FANOUT DRIVER D SUFFIX , ]) Figure 3. MC100ES8011P AC Reference Measurement Waveform ( PECL Input) MC100ES8011P 4 Advanced Clock , Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer The MC100ES8011P is a low voltage 1:2 Differential PECL-to-HSTL clock fanout buffer. Designed for the most demanding clock distribution systems, the


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PDF MC100ES8011P
2006 - Integrated Device Technology CROSS

Abstract: No abstract text available
Text: SHEET Product Preview Low Voltage 1:2 Differential PECL Clock Fanout Buffer MC100ES7011P MC100ES7011P The MC100ES7011P is a low voltage 1:2 Differential PECL to LVDS clock fanout buffer. Designed , clock outputs PECL compatible differential clock inputs 3.3V power supply Supports industrial temperature range Standard 8 lead SOIC package 1:2 DIFFERENTIAL PECL TO LVDS CLOCK FANOUT DRIVER D , PECL Clock Fanout Buffer MC100ES7011P 746 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA


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PDF MC100ES7011P MC100ES7011P 199707558G Integrated Device Technology CROSS
2005 - KLT22

Abstract: HLT22 MC100ELT22 ELT22 HT22 MC100 MC10ELT22
Text: MC10ELT22, MC100ELT22 5.0 V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and , makes it ideal for applications which require the translation of a clock and a data signal. http , Loading SO-8 D SUFFIX CASE 751 Flow Through Pinouts 1 KLT22 ALYW G 1 Operating Range , . PIN DESCRIPTION Q0 1 8 VCC Pin Function Qn, Qn 2 PECL D0 TTL TTL Inputs


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PDF MC10ELT22, MC100ELT22 MC10ELT/100ELT22 ELT22 HLT22 KLT22 MC10ELT22/D KLT22 HLT22 MC100ELT22 HT22 MC100 MC10ELT22
2004 - Not Available

Abstract: No abstract text available
Text: Product Preview Low Voltage 1:2 Differential PECL Clock Fanout Buffer The MC100ES7011P is a low voltage 1:2 Differential PECL to LVDS clock fanout buffer. Designed for the most demanding clock distribution , Supports DC to 1000 MHz operation LVDS compatible differential clock outputs PECL compatible differential , MC100ES7011P 1:2 DIFFERENTIAL PECL TO LVDS CLOCK FANOUT DRIVER D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 , differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very


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PDF MC100ES7011P MC100ES7011P
2007 - Not Available

Abstract: No abstract text available
Text: Product Preview Low Voltage 1:2 Differential PECL Clock Fanout Buffer The MC100ES7011P is a low voltage 1:2 Differential PECL to LVDS clock fanout buffer. Designed for the most demanding clock distribution , Supports DC to 1000 MHz operation LVDS compatible differential clock outputs PECL compatible differential , MC100ES7011P 1:2 DIFFERENTIAL PECL TO LVDS CLOCK FANOUT DRIVER D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 , differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very


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PDF MC100ES7011P MC100ES7011P
2006 - HLT22

Abstract: KLT22 ic so8 socket ELT22 HT22 MC100 MC100ELT22 MC10ELT22
Text: MC10ELT22, MC100ELT22 5.0 V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and , makes it ideal for applications which require the translation of a clock and a data signal. MARKING , Through Pinouts Operating Range: VCC = 4.75 V to 5.25 V with GND = 0 V SO-8 D SUFFIX CASE 751 No , Pin Function Qn, Qn Q0 2 PECL Dn VCC D0 TTL Q1 3 6 4 5 Positive


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PDF MC10ELT22, MC100ELT22 MC10ELT/100ELT22 ELT22 HLT22 HLT22 KLT22 ic so8 socket HT22 MC100 MC100ELT22 MC10ELT22
2000 - HLT22

Abstract: KLT22 HT22 MC100ELT22 MC10ELT22 ELT22
Text: MC10ELT22, MC100ELT22 5VDual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and , makes it ideal for applications which require the translation of a clock and a data signal. · · · , Pinouts ESD Protection: >2 KV HBM, >200 V MM Operating Range: VCC= 4.75 V to 5.25 V with GND= 0 V SO­8 , Assembly Location KT22 ALYW 1 L = Wafer Lot Y = Year W = Work Week D0 2 PECL *For


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PDF MC10ELT22, MC100ELT22 MC10ELT/100ELT22 ELT22 HLT22 r14525 MC10ELT22/D HLT22 KLT22 HT22 MC100ELT22 MC10ELT22
2003 - KLT23

Abstract: No abstract text available
Text: which require the translation of a clock and a data signal. The PECL inputs are differential; therefore, the MC100ELT23 can accept any standard differential PECL input referenced from a VCC of 5.0 V. · 3.5 , Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPS I/O SPICE , MC100ELT23 5V Dual Differential PECL to TTL Translator The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL (Positive ECL) levels are used, only +5 V and ground are required


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PDF MC100ELT23 ELT23 MC100ELT23/D KLT23
2006 - HLT22

Abstract: klt22 ELT22 HT22 MC100 MC100ELT22 MC10ELT22
Text: AN1405/D - ECL Clock Distribution Techniques AN1406/D - Designing with PECL (ECL at +5.0 V , MC10ELT22, MC100ELT22 5.0 V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and , makes it ideal for applications which require the translation of a clock and a data signal. http , Loading Flow Through Pinouts Operating Range: VCC = 4.75 V to 5.25 V with GND = 0 V SO-8 D SUFFIX


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PDF MC10ELT22, MC100ELT22 MC10ELT/100ELT22 ELT22 HLT22 MC10ELT22/D HLT22 klt22 HT22 MC100 MC100ELT22 MC10ELT22
2002 - HEL35

Abstract: KEL35 KL35 MC100EL35
Text: data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock . The reset pin is asynchronous and is , DIAGRAMS* 8 1 SO-8 D SUFFIX CASE 751 8 1 TSSOP-8 DT SUFFIX CASE 948R 1 8 HEL35 ALYW 1 8 KEL35 ALYW · · , , > 100 V MM PECL Mode Operating Range: VCC = 4.2 V to 5.7 with VEE = 0 V NECL Mode Operating Range: VCC = , DESCRIPTION PIN J K R CLK Q, Q VCC VEE FUNCTION ECL Input ECL Input ECL Reset ECL Clock Input ECL Data


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PDF MC10EL35, MC100EL35 MC10EL/100EL35 HEL35 KEL35 AND8020 AN1404 AN1405 AN1406 AN1503 KL35
2003 - KLT23

Abstract: MC100ELT23 MC100ELT23D MC100ELT23DR2 MC100ELT23DT MC100ELT23DTR2
Text: applications which require the translation of a clock and a data signal. The PECL inputs are differential; therefore, the MC100ELT23 can accept any standard differential PECL input referenced from a VCC of 5.0 V , MC100ELT23 5V Dual Differential PECL to TTL Translator The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL (Positive ECL) levels are used, only +5 V and ground are , 2 7 Q0 6 MARKING DIAGRAMS* 8 KLT23 ALYW SO-8 D SUFFIX CASE 751 8 1 1 8


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PDF MC100ELT23 MC100ELT23 ELT23 MC100ELT23/D KLT23 MC100ELT23D MC100ELT23DR2 MC100ELT23DT MC100ELT23DTR2
2007 - Not Available

Abstract: No abstract text available
Text: SiGe Technology Supports DC to 400 MHz operation HSTL compatible differential clock outputs PECL , SOIC package MC100ES8011P 1:2 DIFFERENTIAL PECL TO HSTL CLOCK FANOUT DRIVER D SUFFIX 8 , Measurement Waveform ( PECL Input) 768 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA , Product Preview Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer The MC100ES8011P is a low voltage 1:2 Differential PECL-to-HSTL clock fanout buffer. Designed for the most demanding clock


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PDF MC100ES8011P MC100ES8011P
2003 - KLT23

Abstract: No abstract text available
Text: which require the translation of a clock and a data signal. The PECL inputs are differential; therefore, the MC100ELT23 can accept any standard differential PECL input referenced from a VCC of 5.0 V. · 3.5 , MC100ELT23 5V Dual Differential PECL to TTL Translator The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL (Positive ECL) levels are used, only +5 V and ground are required , * 8 SO-8 D SUFFIX CASE 751 1 8 8 1 A L Y W TSSOP-8 DT SUFFIX CASE 948R 1 = Assembly Location = Wafer


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PDF MC100ELT23 ELT23 MC100ELT23/D KLT23
2004 - KVT20

Abstract: AN1642
Text: AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at , is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used , . The 100 Series contains temperature compensation. http://onsemi.com MARKING DIAGRAM 8 1 SO-8 D SUFFIX CASE 751 8 KVT20 ALYW 1 · 390 ps Typical Propagation Delay · Maximum Input Clock Frequency , Differential PECL Outputs LVTTL Input Positive Supply Ground No Connect NC 4 5 GND (Top View


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PDF MC100LVELT20 KVT20 BRD8011/D. AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642
2004 - receiver ka20

Abstract: HA20 MC10EPT20 HPT20 EPT20 KPT20 MC100 MC100EPT20 KA20 TSSOP8
Text: 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only , Clock Frequency > 1 GHz Typical · Operating Range VCC = 3.0 V to 3.6 V · · · http://onsemi.com MARKING DIAGRAMS* 8 8 1 SO-8 D SUFFIX CASE 751 with GND = 0 V PNP TTL Input for Minimal Loading , Positive Supply Ground No Connect NC 5 LVTTL Input NC Q 7 Differential PECL Outputs , individually under normal operating conditions and not valid simultaneously. Table 5. 10EPT PECL OUTPUT DC


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PDF MC10EPT20, MC100EPT20 MC10EPT20 EPT20 MC10EPT20/D receiver ka20 HA20 HPT20 KPT20 MC100 MC100EPT20 KA20 TSSOP8
2003 - KPT-20

Abstract: HA20 MC10EPT20
Text: Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and , TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and , contains temperature compensation. http://onsemi.com MARKING DIAGRAMS* 8 1 SO-8 D SUFFIX CASE 751 8 HPT20 ALYW 1 1 8 KPT20 ALYW · 390 ps Typical Propagation Delay · Maximum Input Clock Frequency > 1 GHz , Package SO-8 SO-8 SO-8 SO-8 TSSOP-8 Shipping 98 Units/Rail 2500 Tape & Reel 98 Units/Rail 2500 Tape & Reel


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PDF MC10EPT20, MC100EPT20 MC10EPT20 EPT20 HPT20 KPT20 MC10EPT20/D KPT-20 HA20
2002 - HLT22

Abstract: MC100-A KLT22 AN1400
Text: Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPS I/O SPICE Modeling , MC10ELT22, MC100ELT22 5V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground , it ideal for applications which require the translation of a clock and a data signal. http://onsemi.com MARKING DIAGRAMS* 8 1 SO-8 D SUFFIX CASE 751 8 HLT22 ALYW 1 1 8 KLT22 ALYW · · · · · · · · · ·


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PDF MC10ELT22, MC100ELT22 MC10ELT/100ELT22 ELT22 HLT22 KLT22 r14525 MC10ELT22/D MC100-A AN1400
2004 - PMEG2020EA

Abstract: smps repair circuit 40V NPN embedded package TEA1620P TEA1622 smps repair TEA1623P pecl clock so8 30v 3a schottky barrier type rectifiers smd transistor bq
Text: Quarterly highlights. P 1 PCK12429 25 - 400 MHz differential PECL clock generator products, you will , low VCEsat (BISS) transistor P 4 PCK111/PCK210/PCKEL14/PCKEP14 High-speed differential PECL clock , 20 V, 2 A very low VF MEGA Schottky barrier rectifier 25 - 400 MHz differential PECL clock , PECL output clock from an external quartz crystal reference with an input range of 10 - 20 MHz. It , One 25 - 400 MHz differential PECL clock output · +/- 25 ps peak-to-peak output jitter · Fully


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PDF PCK12429 PBSS5540X PCK111/PCK210/PCKEL14/PCKEP14 TDA9965A PMEG2020EA smps repair circuit 40V NPN embedded package TEA1620P TEA1622 smps repair TEA1623P pecl clock so8 30v 3a schottky barrier type rectifiers smd transistor bq
2005 - clock generator differential output

Abstract: MC100ES8011P
Text: . 1:2 DIFFERENTIAL PECL TO HSTL CLOCK FANOUT DRIVER Features · · · · · · · · · 1:2 , HSTL compatible differential clock outputs PECL compatible differential clock inputs 3.3V power , Low Voltage 1:2 Differential PECL-to Low Voltage 1:2 Differential -HSTL Clock Fanout Buffer MC100ES8011P PECL-to-HSTL Clock Fanout Buffer The MC100ES8011P is a low voltage 1:2 Differential PECL-to-HSTL clock fanout buffer. Designed for the most demanding clock distribution systems, the


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PDF MC100ES8011P MC100ES8011P 199707558G clock generator differential output
2006 - Integrated Device Technology CROSS

Abstract: tPD50
Text: SiGe Technology Supports DC to 400 MHz operation HSTL compatible differential clock outputs PECL , SOIC package MC100ES8011P MC100ES8011P 1:2 DIFFERENTIAL PECL TO HSTL CLOCK FANOUT DRIVER D , Measurement Waveform ( PECL Input) IDTTM Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer , SHEET Product Preview Low Voltage 1:2 Differential PECL-to -HSTL Clock Fanout Buffer The MC100ES8011P is a low voltage 1:2 Differential PECL-to-HSTL clock fanout buffer. Designed for the most


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PDF MC100ES8011P 199707558G Integrated Device Technology CROSS tPD50
2002 - Not Available

Abstract: No abstract text available
Text: which require the translation of a clock and a data signal. The PECL inputs are differential; therefore, the MC100ELT23 can accept any standard differential PECL input referenced from a VCC of 5.0 V. · 3.5 , MC100ELT23 5V Dual Differential PECL to TTL Translator The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL (Positive ECL) levels are used, only +5 V and ground are required , Index: 28 to 34 · Transistor Count = 91 devices D0 1 D0 2 PECL D1 3 TTL 6 Q1 8 VCC 7 Q0 http


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PDF MC100ELT23 ELT23 r14525 MC100ELT23/D
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