The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC1643AHCGN#TR Linear Technology LTC1643A - PCI-Bus Hot Swap Controller; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C
LTC4242CG Linear Technology LTC4242 - Dual Slot Hot Swap Controller for PCI Express; Package: SSOP; Pins: 36; Temperature Range: 0°C to 70°C
LTC1643AL-1CGN#TRPBF Linear Technology LTC1643A - PCI-Bus Hot Swap Controller; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C
LTC4242CUHF#PBF Linear Technology LTC4242 - Dual Slot Hot Swap Controller for PCI Express; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C
LTC4242CG#TR Linear Technology LTC4242 - Dual Slot Hot Swap Controller for PCI Express; Package: SSOP; Pins: 36; Temperature Range: 0°C to 70°C
LTC1643AL-1IGN#PBF Linear Technology LTC1643A - PCI-Bus Hot Swap Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C

pci target Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1995 - XC4400

Abstract: XC4000 XC4000E XC4013E-3PQ208C Xilinx XC4013E-3PQ208C
Text: ® PCI Target System Module for XILINX XC4000E FPGA September 27, 1995 Design Description , fully-implemented 33 MHz PCI Target interface in 40% of an XC4013E-3PQ208C FPGA. n Verified electrical and , PCI Target inte rface, configuration registers, burst FIFOs, and a custom back-end interface. n , cost. Application Procedure The Xilinx PCI Target System Module ensures fast time-to-volume by , required to obtain the PCI Target System Module. To apply for the PCI Target System Module design


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PDF XC4000E XC4013E-3PQ208C 16-deep 32-wide XC4400 XC4000 XC4013E-3PQ208C Xilinx XC4013E-3PQ208C
2010 - NOR Flash

Abstract: NOR flash controller vhdl code pci initiator in verilog NOR Flash read cycle flash read verilog RD1008 wishbone verilog code for pci to pci bridge vhdl code for 32bit parity generator vhdl code for 4 bit even parity generator
Text: design. Features · Supports 33-MHz,32-bit PCI target functions with PCI Local Bus Specification Rev , Flash data sheet The reference design does not support the following features: · PCI target interface , register space ­ Cache line register ­ Interrupt signal from PCI target to PCI initiator · NOR Flash , of the PCI target that completes the current configuration cycle on the PCI bus. pci_frame_l , Output Low The PCI target drives this signal low prior to the positive edge of a clock when it can


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PDF RD1050 LFXP2-5E-5FT256C, RD1008, 33MHz, 32-Bit 1-800-LATTICE NOR Flash NOR flash controller vhdl code pci initiator in verilog NOR Flash read cycle flash read verilog RD1008 wishbone verilog code for pci to pci bridge vhdl code for 32bit parity generator vhdl code for 4 bit even parity generator
2010 - wishbone rev. b

Abstract: wishbone verilog code for pci to pci bridge verilog hdl code for parity generator RD1008
Text: the PCI and WISHBONE sides of the bridge · Supports 33 MHz,32-bit PCI target functions with PCI Local , Parity generation for all read cycles · Two FIFOs between PCI target module and WISHBONE master module , design does not support the following features: · PCI target interface ­ PERR and SERR ­ Expansion ROM , register ­ Interrupt signal from PCI target to PCI initiator · WISHBONE master interface ­ Respond to , design is used to interface a PCI initiator, or master, and a WISHBONE slave device. It acts as a target


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PDF RD1045 32-bit RD1008 33MHz, 1-800-LATTICE wishbone rev. b wishbone verilog code for pci to pci bridge verilog hdl code for parity generator RD1008
2001 - 176-PQFP

Abstract: 9030RDK-LITE pci9030 plx 9030
Text: .2 compliant 32-bit 33MHz Target Interface Chip enabling PCI Burst Transfers up to 132Mbytes/second. s Up to 60MHz Local Bus operation enabling burst transfers up to 240Mbytes/second s PCI Target Read Ahead Mode s PCI Target Programmable Burst s PCI Target Delayed Write s Posted Memory , to do a PCI target design. Many PCI chip and core designs only attempt to implement the minimum PCI , your current PCI target design, the PCI 9030 with SMARTarget technology provides the fastest and


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PDF 32-bit 33MHz 132Mbytes/second. 60MHz 240Mbytes/second 32-bit 60MHz 9030-SIL-PB-P1-03 176-PQFP 9030RDK-LITE pci9030 plx 9030
2001 - plx 9030

Abstract: 9030-AA60BI PCI 9030 BGA 180 176-PQFP 176PQFP
Text: .2 compliant 32-bit 33MHz Target Interface Chip enabling PCI Burst Transfers up to 132Mbytes/second. s Up to 60MHz Local Bus operation enabling burst transfers up to 240Mbytes/second s PCI Target Read Ahead Mode s PCI Target Programmable Burst s PCI Target Delayed Write s Posted Memory , to do a PCI target design. Many PCI chip and core designs only attempt to implement the minimum PCI , your current PCI target design, the PCI 9030 with SMARTarget technology provides the fastest and


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PDF 32-bit 33MHz 132Mbytes/second. 60MHz 240Mbytes/second 32-bit 60MHz 9030-SIL-PB-P1-03 plx 9030 9030-AA60BI PCI 9030 BGA 180 176-PQFP 176PQFP
Verification Using a Self-checking Test Bench

Abstract: signal path designer ispMACH M4A3
Text: Designing a 33MHz, 32-Bit PCI Target Using ispMACH Devices July 2001 Reference Design RD1008 , a 33MHz, 32-bit PCI target for ispMACHTM devices. It is designed to provide users with a starting point for designing a PCI target into a Lattice CPLD. The reference design source code is available from Lattice upon the signing of a simple non-disclosure agreement. The 33MHz, 32-bit PCI target , modifications · A fully automated and self-checking HDL test bench for ease of verification The PCI Target


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PDF 33MHz, 32-Bit RD1008 1-800-LATTICE Verification Using a Self-checking Test Bench signal path designer ispMACH M4A3
2010 - CODE VHDL TO ISA BUS INTERFACE

Abstract: ispMACH M4A3 verilog hdl code for multiplexer 4 to 1 vhdl code for 32bit parity generator verilog hdl code for parity generator ispMACH 4A3 PCI33 LCMXO2280 LCMXO1200 Signal path designer
Text: Designing a 33MHz, 32-Bit PCI Target Using Lattice Devices January 2010 Reference Design , design solution for a 33MHz, 32-bit PCI target for LatticeXP2TM, MachXOTM and ispMACH® devices. It is designed to provide users with a starting point for designing a PCI target into Lattice devices. The , . The 33MHz, 32-bit PCI target reference design comes with a fully-automated HDL test environment and , self-checking HDL test bench for ease of verification The PCI Target does not support the following features


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PDF 33MHz, 32-Bit RD1008 1-800-LATTICE CODE VHDL TO ISA BUS INTERFACE ispMACH M4A3 verilog hdl code for multiplexer 4 to 1 vhdl code for 32bit parity generator verilog hdl code for parity generator ispMACH 4A3 PCI33 LCMXO2280 LCMXO1200 Signal path designer
1999 - vhdl code for a 9 bit parity generator

Abstract: pci target verilog hdl code for parity generator vhdl code for 4 bit even parity generator vhdl code for 9 bit parity generator pci initiator in verilog pci verilog code Signal Path DESIGNER
Text: Designing a 33MHz, 32-Bit PCI Target Using MACH Devices Reference Design Application Note Table of Contents DESIGNING A 33MHZ, 32-BIT PCI TARGET USING MACH DEVICES , . 5 REGISTER TRANSFER LEVEL (RTL) IMPLEMENTATION OF THE PCI TARGET REFERENCE DESIGN. 6 PCI TARGET TOP , . 13 THE DEVICE-UNDER-TEST (THE PCI TARGET


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PDF 33MHz, 32-Bit vhdl code for a 9 bit parity generator pci target verilog hdl code for parity generator vhdl code for 4 bit even parity generator vhdl code for 9 bit parity generator pci initiator in verilog pci verilog code Signal Path DESIGNER
1998 - 430VX

Abstract: No abstract text available
Text: ® pcit1 PCI Target MegaCore Function Data Sheet July 1998, ver. 1.01 Features s s s s , -bit, 33-MHz peripheral component interconnect ( PCI ) target interface Fully compliant with the PCI Special , Corporation A-DS-PCIT1-01.01 1 pcit1 PCI Target MegaCore Function Data Sheet General Description , target interface (ordering code: PLSM-PCIT1). Because the pcit1 function handles the complex PCI protocol , and implements the logic. 2 Altera Corporation pcit1 PCI Target MegaCore Function Data Sheet


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PDF 32-bit, 33-MHz E2925A 430VX
1997 - AGP Host to PCI Bridge

Abstract: commands pci controller pci target gart
Text: ) will be described. Processor 1 2 4 PCI Target PCI Master (Optional) AGP Master AGP , Controller 8 6 System Memory 3 PCI Controller AGP Compliant Corelogic PCI PCI Target /Master PCI Target /Master Target /Master 6-1 Figure 0-1 Configuration View of an A.G.P. Target , Controller also provides a means for PCI masters to access the PCI target that resides on the A.G.P. port , Bridge Architecture Specification. The P2P bridge makes it possible to configure the PCI target


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PDF ECR-16. AGP Host to PCI Bridge commands pci controller pci target gart
2008 - PLX PCI9030 bridge

Abstract: pci target plx 9030 PCI9030 cpldbased 64-BIT SOUND CARD Altera N ROHS EPM2210 EPM1270 MAX PLUS II Programmable Logic Development System & Software
Text: PCI target interfaces can be implemented at lower costs using CPLDs, resulting in cost savings and , function as a 32-bit, 66-MHz PCI target interface by integrating Altera's PCI target interface , implements a local bus interface similar to common ASSP-based PCI interfaces. The Altera PCI target interface , block diagram of Altera's MAX II CPLD-based PCI target interface solution. WP-AAB090305-1.3 March , Corporation Figure 2. Altera's MAX II CPLD-Based PCI Target Interface Solution Block Diagram 32-bit PCI I


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1999 - vhdl code for 8 bit ODD parity generator rom

Abstract: PAR64 REQ64 vhdl code for 8 bit odd parity checker
Text: PCI Target Designs Using Ultra37000 CPLDs Introduction The Peripheral Component Interconnect ( PCI , associated transactions, and to present example designs for a PCI target device that has been implemented in , target designs and the associated test bench to confirm functionality. PCI Architecture The PCI bus , devices are accessible from the PCI bus and transact in an initiator/ target relationship. The initiator , this note the terms initiator and target are used instead of master and slave. CPU SRAM PCI


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PDF Ultra37000 vhdl code for 8 bit ODD parity generator rom PAR64 REQ64 vhdl code for 8 bit odd parity checker
1999 - PPC401

Abstract: Nippon capacitors radial book
Text: ).3 PCI Target (Direct Slave , .15 2.1.1 2.1.2 2.1.2.1 2.1.2.2 PCI Target Command Codes , .16 PCI Target , . 18 PCI Target Accesses to 8- or 16-Bit Local Bus , .36 PCI Initiator/ Target Abort


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PDF 1030-54000-DTB USA/0499 PPC401 Nippon capacitors radial book
1999 - A42 B331

Abstract: CA91C860B-40IQ CA91C860B-40CQ CA91C860B-50CQ tea 1601 t CA91C860B a44 b331 CA91C860 T337A CA91L860B-50CE
Text: . 2-1 The QBus Slave Channel: From Processor to PCI Bus . 2-2 The PCI Target , and PCI Transaction Ordering. 2-19 PCI Target Channel Reads , The PCI Target Channel . 2-24 PCI Target Channel Architecture Overview . 2-25 PCI , 2-33 Write Cycle Mapping for PCI Target Channel. 2-34 32-Bit QBus Port


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PDF CA91C860B, CA91L860B) A42 B331 CA91C860B-40IQ CA91C860B-40CQ CA91C860B-50CQ tea 1601 t CA91C860B a44 b331 CA91C860 T337A CA91L860B-50CE
68k cpu

Abstract: Motorola 68040 F020 XX10 spanner
Text: function as 68K target and PCI target . The figure also illustrates its role in translating during , : "Spanner as 68K Target ( PCI Initiator)" on page 2-4 "Spanner as PCI Target (68K Initiator)" on page 2-8 , Functional Overview The Spanner bridges a PCI bus to a 68040 compatible bus, with initiator and target , acknowledgment from the 68K side will meet PCI latency requirements, the Spanner chip performs a target , ^ SflT ive Manufacturer — * ' Spanner as PCI Target (68K Initiator) Spanner User Manual 2.2 Spanner


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PDF 225-Pin DD03HSÃ CA91C068-X U5SB101 68k cpu Motorola 68040 F020 XX10 spanner
1998 - E2925A

Abstract: 803-4 BUS BAR specification 21052-AB 430HX 430TX 430VX FF000000
Text: pcit1 PCI Target MegaCore Function Data Sheet ® 1998 6 ver.1 Data Sheet s s s , I/O MRM MRL MWI Page 1 pcit1 PCI Target MegaCore Function , Corporation pcit1 PCI Target MegaCore Function Data Sheet MAX+PLUS II.gdf pcit1 pcit1 , TABORT_SIG SERR_SIG PERR_DET Page 3 pcit1 PCI Target MegaCore Function Data Sheet PCI pcit1 PCI , pcit1pcit1PCI pcit1PCI pcit1 Page 4 Altera Corporation pcit1 PCI Target MegaCore Function Data


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PDF -DS-PCIT1-01/J 3233MHzPCIPeripheral 10KFLEX E2925A BARFLEX550790 132M/sec 803-4 BUS BAR specification 21052-AB 430HX 430TX 430VX FF000000
2002 - 1AM5

Abstract: No abstract text available
Text: . . . . . . 68 Universe II as PCI Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . 90 PCI Bus Target Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Special PCI Target Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 PCI Bus Target Channel , . . 89 Memory Mapping in the Special PCI Target Image . . . . . . . . . . . . . . . . . 92 Figure


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PDF 80A3010 LD64EN 1AM5
2000 - plx 9030

Abstract: plx 9030 data sheet mini pci pcb layout plx 9030 176-pin pqfp PCI9030
Text: . . . 2.1.1.1. PCI Target Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 2.1.1.3. PCI Target Accesses to an 8- or 16-Bit Local Bus Device . . . . . . . . . . . . . . . . . . . . . , 3-1 3-1 3-1 3-1 3-1 3-1 3-3 3-6 3-6 3-7 3-7 3-8 4. PCI Target (Direct Slave) Operation . , . . . . . . . 4.2.1. PCI Target Operation ( PCI Master-to-Local Bus Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1.1. PCI Target Lock . . . . . . . . . . . . .


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PDF 9030-SIL-DB-P1-1 plx 9030 plx 9030 data sheet mini pci pcb layout plx 9030 176-pin pqfp PCI9030
2002 - EJTAG PROBE

Abstract: 20A4 AN-350 RC32332
Text: target reads and writes as well as PCI master reads and writes. There are separate eight-word-deep FIFOs , majority of PCI devices and nearly all of the customer systems IDT has seen utilize target reads and , increasing the target access buffer sizes, numerous other architectural changes were made. General PCI , system controller registers. PCI Target Write Changes In the Z-revision, target PCI writes are , PCI target write never performs burst transactions across the local bus, the 1-1-1 is not taken


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PDF RC32334/RC32332 AN-350 RC32334/RC32332 32-bit RC32334 RC32332 EJTAG PROBE 20A4 AN-350
2002 - plx 9030

Abstract: plx 9030 176-pin pqfp PCI9030 93cs66l 9030-AA60BI TMS320C6202 PPC401 93CS56L plx 9052 marking ld25
Text: . . . . . . . . . . . . . . 1.1.3.1. High-Performance PCI Target Interface . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1.1. PCI Target Command , . . . . . . . . . . . . . . . . . . . . . . . 2.1.1.5. PCI Target Accesses to an 8-or 16-Bit Local , 3-6 3-7 3-7 3-8 4. PCI Target (Direct Slave) Operation . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1. PCI Target


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PDF 9030-ms Index-11 plx 9030 plx 9030 176-pin pqfp PCI9030 93cs66l 9030-AA60BI TMS320C6202 PPC401 93CS56L plx 9052 marking ld25
2009 - CA91C142D-33IE

Abstract: CA91C142D-33CE CA91C142D-33iev CA91C142D-33CEV tundra universe TUNDRA CA91C142D-33CE tundra scv64 LM015 universe II IDT Tundra Semiconductor ca91c142d
Text: . Universe II as PCI Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . PCI Bus Target Images . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special PCI Target Image . . . , PCI Bus Target Channel Dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , Special PCI Target Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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2000 - plx 9030 176-pin pqfp

Abstract: plx 9052
Text: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3.1. High-Performance PCI Target , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1.3. PCI Target Accesses , 3-1 3-1 3-1 3-1 3-1 3-3 3-6 3-6 3-7 3-7 3-8 4. PCI Target (Direct Slave) Operation . . . . . . . . , . . . 4.2.1. PCI Target Operation ( PCI Master-to-Local Bus Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1.1. PCI Target Lock . . . . . . . . . . . . . . . . . . .


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PDF 9030-SIL-DB-P1-1 Index-19 plx 9030 176-pin pqfp plx 9052
2004 - MCF5470

Abstract: MCF5471 MCF5472 MCF5473 MCF5474 MCF5475 pci controller
Text: Disconnected PCI read bursts when MCF547x is master can cause corruption when followed by target access 4 , /2004 All PCI target interface prefetch from slow memory 6 PCI 08/17/2004 All , /17/2004 All PCI target interface does not expect false writes on the first data beat 12 , /write results in data loss 16 PCI 08/17/2004 All PCI target read prefetch data , target interface of the PCI controller and a read to PCI across the XL bus collide. The condition occurs


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PDF MCF5475 MCF5470, MCF5471, MCF5472, MCF5473, MCF5474, MCF547x MCF5275DE MCF5470 MCF5471 MCF5472 MCF5473 MCF5474 pci controller
2001 - Not Available

Abstract: No abstract text available
Text: 1.2.3.1. High-Performance PCI Target Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . 2.1.1.1. PCI Target Command Codes . . . . . . . . . . . . . . , . . . . . . . . . . . . 2.1.1.3. PCI Target Accesses to an 8- or 16-Bit Local Bus Device . . . . . , 3-1 3-3 3-6 3-6 3-7 3-7 3-8 4. PCI Target (Direct Slave) Operation . . . . . . . . . . . . . , 4.2.1. PCI Target Operation ( PCI Master-to-Local Bus Access) . . . . . . . . . . . . . . . . . . . . . .


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PDF 9030-SIL-DB-Pam Index-19
1998 - DS-FND-BAS-PC

Abstract: DS-FND-EXP-PC
Text: Foundation Series: the PCI target and initiator, and the PCI target only. See our web site for more information on our PCI cores. PCI Target & Initiator PCI Target only For the most recent pricing


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