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Part Manufacturer Description Datasheet Download Buy Part
DC392A-A Linear Technology LTC1628 or LTC3728 Evaluation Kit
DC392A-C Linear Technology LTC1628 or LTC3728 Evaluation Kit
DC392A-B Linear Technology LTC1628 or LTC3728 Evaluation Kit
LF198S Linear Technology IC SAMPLE AND HOLD AMPLIFIER, PDSO, Sample and Hold Circuit
LF198AJ8 Linear Technology IC SAMPLE AND HOLD AMPLIFIER, CDIP8, Sample and Hold Circuit
LF198AS Linear Technology IC SAMPLE AND HOLD AMPLIFIER, PDSO, Sample and Hold Circuit

pMOS NAND GATE Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
nmos pmos array

Abstract: mf10 A300 list of n channel fet Acumos n channel fet array
Text: device. Since it takes two pairs to make a two input - NAND gate , this area has the potential of making , il A300 Analog/Digital Gate Array DESCRIPTION The Acumos A300 is a high performance analog/digital gate array. The gate array can perform analog and/or digital functions. The gate array is silicon gate construction using a double-poly p-well process. The minimum gate channel length is 4 microns , €” 12V V Internal gate prop delay - less than 5ns V Output sink current per transistor 6 mA V Op amps


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acumos

Abstract: list of n channel fet A300 MF10 nmos pmos array n channel fet array
Text: input - NAND gate , this area has the potential of making 200 two input NAND gates. Due to interconnect , il A300 Analog/Digital Gate Array DESCRIPTION The Acumos A300 is a high performance analog/digital gate array. The gate array can perform analog and/or digital functions. The gate array is silicon gate construction using a double-poly p-well process. The minimum gate channel length is 4 microns , €” 12V V Internal gate prop delay - less than 5ns V Output sink current per transistor 6 mA V Op amps


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mc 4011

Abstract: Mc 4049 MM4601 CD4017 CD4024 4049 schmitt trigger MC14584 "cross reference" CD4013 CD4018 CD4021 serial input parallel output
Text: Input NOR Gate + Inverter HD-4000 CD4000 Quad 2 Input NOR HD-4001 CD4001 MM4601 Dual 4 Input NOR HD , HD-4007 CD4007 4-Bit Full Adder HD-4008 CD4008 Quad 2 Input NAND HD-4011 CD4011 MM4611 Dual 4 Input NAND HD-4012 CD4012 MM4612 Dual D Flip-Flop HD-4013 CD4013 MM4613 8 Stage Static Shift Register , Divide by 8 Counter HD-4022 CD4022 MM4622 Triple 3 Input NAND HD-4023 CD4023 MM4623 7 Stage Binary , -4043 CD4043 Quad Three State NAND R/S Latch HD-4044 CD4044 Hex Buffer, Inverting HD-4049 CD4049 MM4649 Hex


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PDF HD-4000 CD4000 HD-4001 CD4001 MM4601 HD-4002 CD4002 MM4602 HD-4006 mc 4011 Mc 4049 MM4601 CD4017 CD4024 4049 schmitt trigger MC14584 "cross reference" CD4013 CD4018 CD4021 serial input parallel output
74C901

Abstract: 74C902 74C221 74C904 80C97 Multivibrator 4001 74C903 74C17 80c95 CD40106 PIN OUT
Text: /BUFFERS/INVERTERS Dual 3 Input NOR Gate + Inverter Quad 2 Input NOR Dual 4 Input NOR Quad 2 Input NAND Dual 4 Input NAND Triple 3 Input NAND Triple3 Input NOR Hex Inverter Quad 2 Input AND 8 Inputs NAND Quad 2 Input OR Quad 2 Input Exclusive OR Quad AND-OR Select Dual Complementary Pair + Inverter Hex Buffer/Converter, Inverting Hex Buffer/Converter, Non-Inverting Hex Inverting PMOS Buffer Hex , Non-Inverting TTL Buffer HD-74C902 Hex Inverting PMOS Buffer HD-74C903 Hex Non-Inverting PMOS Buffer HD


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PDF HD-74C173 HD-74C174 HD-74C175 HD-74C192 HD-74C193 HD-74C195 256-Bit HD-74C200 HD-74C221 HD-74C901 74C901 74C902 74C221 74C904 80C97 Multivibrator 4001 74C903 74C17 80c95 CD40106 PIN OUT
74C10

Abstract: CD40106 PIN OUT HID-4025 74C20 cd40106 74C32 74C14 74c164 MC14584 HD-74C30
Text: GATES/BUFFERS/INVERTERS Dual 3 Input NOR Gate + Inverter Quad 2 Input NOR Dual 4 Input NOR Quad 2 Input NAND Dual 4 Input NAND Triple 3 Input NAND Triple3 Input NOR Hex Inverter Quad 2 Input AND 8 Inputs NAND Quad 2 Input OR Quad 2 Input Exclusive OR Quad AND-OR Select Dual Complementary Pair + Inverter Hex Buffer/Converter, Inverting Hex Buffer/Converter, Non-Inverting Hex Inverting PMOS Buffer Hex Non-Inverting PMOS Buffer Three State Hex Buffer Three State Hex Buffer HD-4000 HD


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PDF HD-4000 HD-4001 HID-4002 hlD-4011 HID-4012 HID-4023 HID-4025 CD4069 HD-4030 HD-4019 74C10 CD40106 PIN OUT HID-4025 74C20 cd40106 74C32 74C14 74c164 MC14584 HD-74C30
74C32

Abstract: 74C02 74C20 74C164 74C89 MC14584 HD-74C20 74C165 74C30 74C04
Text: HD-54C/74* SERIES MANUFACTURER CROSS REFERENCE FUNCTION Quad 2 Input NAND Quad 2 Input NOR Hex Inverter Quad 2 Input AND Triple 3 Input NAND Hex Schmitt Trigger Dual 4 Input NAND 8 Input NAND Quad 2 Input OR BCD to Decimal Decoder BCD to 7 Segment Decoder Dual J-K Flip-Flops with Clear , MM74C160 MM74C161 MM74C162 MM74C163 MM74C164 Di - 2 GATES/BUFFERS/INVERTERS Dual 3 Input NOR Gate + Inverter Quad 2 Input NOR Dual 4 Input NOR Quad 2 Input NAND Dual 4 Input NAND Triple 3 Input NAND


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PDF HD-54C/74* 64-Bit HD-4006 HD-4015 HD-4014 HD-4021 HD-4035 HD-74C165 HD-74C95 HD-74C164 74C32 74C02 74C20 74C164 74C89 MC14584 HD-74C20 74C165 74C30 74C04
1998 - TTL 7400

Abstract: 4000 series CMOS Logic levels 18 - 24v 7400 series CMOS Logic ICs 7400 TTL CMOS TTL Logic Family Specifications CV2f z1012 TTL 7400 fairchild 5 input nand gate dtl 15V 5A Power Supply Schematic
Text: the circuit in question. Take, for example, a four input NAND gate being used as a two input gate , current load such as a lamp or a relay. So, tying unused NAND gate inputs to VCC (Ground for NOR , . MM74C20 Four Input NAND gate age required will be determined by the maximum frequency of operation of , . Typically, the static power dissipation is 10 nW per gate which is due to the flow of leakage currents. The , , gate dissipation at 1 MHz with a 50 pF load is less than 10 mW. Second, the propagation delays


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1995 - TTL 7400 national semiconductor

Abstract: TRANSISTOR 6019 CV2f AN-77 MM74C20 MM74C02 MM74C00 CD4016C CD4000A C1995
Text: Take for example a four input NAND gate being used as a two input gate The internal structure is , transistors would be on So tying unused NAND gate inputs to VCC (Ground for NOR gates) will enable them but , ) a TL F 6019 ­ 11 FIGURE 3-1 MM74C20 Four Input NAND gate 4 supply voltage AC and DC , dissipates low power Typically the static power dissipation is 10 nW per gate which is due to the flow of , time but typically gate dissipation at 1 MHz with a 50 pF load is less than 10 mW Second the


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1998 - ATL35

Abstract: nand gate layout ATL60
Text: defined as a two input NAND or, in Atmel's library, a NAN2. A NAN2 uses four transistors. For each gate , , each gate array routing site contains four transistors, two NMOS and two PMOS . Transistors are , accurate equivalent two input NAND gate count, the netlist from Synopsys can be analyzed using v3h (a , yields a precise equivalent two input NAND gate count. ATL35 Cell Library-1.0-12/97 To determine , . 7-2 Gate Count Estimation


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PDF ATL35 nand gate layout ATL60
2001 - OPA03

Abstract: DMILL SUN SENSOR 65260 npn nv SRAM cross reference hep silicon diode Bias "One Year Repeatability" SMALL ELECTRONICS PROJECTS digital SUN SENSOR cmos detector digital SUN SENSOR cmos detector space radiation
Text: possibility to use 4 different active devices, i.e. NMOS, PMOS , NPN Bipolar and PJFET. With regards to , (4.0x0.8) and PMOS (8.0/0.8) Rev. B ­ 24-Aug-01 1 DMILL Table 1. DMILL basic parameters , 17.5 nm Gate oxide thickness EField 470 nm Gate oxide thickness Ecapa 42.0 nm Gate oxide thickness RP+ 118 /square P+ resistivity RP- 3550 /square P , gate resistivity R M1 0.050 /square Metal 1 resistivity R M2 0.040 /square


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2002 - OPA02

Abstract: OPA03 128 x 1 multiplexer hep silicon diode BGP02 DMILL calorimeter sensor CIRCUIT SUN SENSOR digital SUN SENSOR cmos detector space radiation BGP01
Text: Grounded gate NMOS transistors / Specific Poly-contact spacing / > 4000V Output Buffer NMOS & PMOS , use 4 different active devices, i.e. NMOS, PMOS , NPN Bipolar and PJFET. With regards to advanced , (4.0x0.8) and PMOS (8.0/0.8) Rev. 4169B­AERO­08/01 1 Table 1. DMILL basic parameters Parameter , 17.5 nm Gate oxide thickness EField 470 nm Gate oxide thickness Ecapa 42.0 nm Gate oxide thickness RP+ 118 /square P+ resistivity RP- 3550 /square P


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PDF 4169B OPA02 OPA03 128 x 1 multiplexer hep silicon diode BGP02 DMILL calorimeter sensor CIRCUIT SUN SENSOR digital SUN SENSOR cmos detector space radiation BGP01
2011 - 4000 series CMOS Logic ICs

Abstract: TTL 74ALS CMOS 4000 Series family TTL nand gate 74 Series Logic ICs TTL SERIES 74AS cmos logic 4000 series 74ls series logic family IC AND GATE TTL family 4000 series CMOS IC
Text: 9/7/2011 ©2011, CE Department 12 dce 2011 TTL NAND Gate · LOW State 9/7/2011 ©2011, CE Department 13 dce 2011 TTL NAND Gate · HIGH State 9/7/2011 ©2011, CE Department 14 dce 2011 TTL NAND Gate · Current-Sinking and Current Sourcing 9/7/2011 ©2011, CE Department 15 dce 2011 TTL NAND Gate · Totem-Pole Output ­ Advantage · Low , Department 33 dce 2011 Complementary MOS Logic · CMOS NAND Gate 9/7/2011 ©2011, CE


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PDF 4000B 74HC/74HCT 4000 series CMOS Logic ICs TTL 74ALS CMOS 4000 Series family TTL nand gate 74 Series Logic ICs TTL SERIES 74AS cmos logic 4000 series 74ls series logic family IC AND GATE TTL family 4000 series CMOS IC
1998 - 3 input or gates TTL

Abstract: cmos XOR Gates 4-input nand gates ttl "resistor set oscillator" dip XOR GATES Nand gate Crystal Oscillator TTL XOR Gates 5D208 cmos XOR schmitt trigger toggle nand
Text: HT3A CMOS Low Cost Gate Array General Features · · · · · · · · 5µm LOVAG CMOS , low power 32kHz Cell Libraries · · · · Basic gates ­ Inverting x1, x2, x3 ­ NAND 2 , and reset Special cells ­ Power on reset ­ RC oscillator ­ Schmitt trigger ­ High impedance PMOS ­ High impedance NMOS HT5D 0.8µm CMOS High Speed Gate Array General Features · · · · · · · · 0.8µm single poly, double metal CMOS technology Sea of gate architecture Operating


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PDF HTA3000 HT3A000 HT3A100 HT3A200 HT3A300 HT3A400 3 input or gates TTL cmos XOR Gates 4-input nand gates ttl "resistor set oscillator" dip XOR GATES Nand gate Crystal Oscillator TTL XOR Gates 5D208 cmos XOR schmitt trigger toggle nand
HX2000

Abstract: HMX2000 nmos pmos array IC AND GATE TTL family honeywell SOI CMOS
Text: Characteristics Maximum gate count and I/O Typical delay ­ 2 input NAND I/O interface levels Typical power consumption, W/MHz/ gate Operating temperature range Minimum Geometry Analog supply level NMOS/ PMOS Vt , MIXED SIGNAL SOI GATE ARRAYS HMX2000 FAMILY Features Fabricated on Honeywell's RICMOSTM IV , digital gate arrays - Sea-Of-Gates flow around embedded cells - Memory, A/D, D/A and other cores available Up to 275,000 gates useable Typical gate toggle power 0.6 W/MHz/ gate Analog on SOI provides


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PDF HMX2000 HMX2000 HX2000 100ppm/Volt, nmos pmos array IC AND GATE TTL family honeywell SOI CMOS
0.5 MIETEC CMOS

Abstract: No abstract text available
Text: on-chip gate delay • Speed: Up to 25 M H z operation (Commercial Temp. Range) • Pow er , custom LSI circuits. Due to smaller die sizes, standard cell parts can be more economical than gate , , speed, and electrical characteristics, resulting in a reduction in unit costs over gate arrays while , entire circuit is automatically interconnected. Unlike gate arrays, only those cells and interconnects , ). .1 . 8 . . 8 . . 40 x 84.8 2-Input nand


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PDF 1204x744 DA081 600x816 MTC-2010 0.5 MIETEC CMOS
N03E

Abstract: HBC2500 CMP006 op-amp- 356 AMP016 transistor 2955 Analog Devices Opamp 3-input xnor opamp 555 AMP017
Text: 5ns NAND Gates, 22ns D-flipflops, 1MHz - 20MHz UGBW Op Amps with 1mV - 5mV Offsets, 250ns Comparator , 7/3 7/3 3/10 3/10 3/20 3/20 10/3 10« 3/30 3/30 40/3 40/3 DIGITAL PRIMITIVES: 2-INPUT NAND GATES , /3 3/3 7/3 7/3 16/3 16« 16/3 16/3 im 28/3 16/3 16/3 DIGITAL PRIMITIVES: 3-INPUT NAND GATES , 21/3 7/3 7/3 16/3 16/3 DIGITAL PRIMITIVES: 4-INPUT NAND GATES NA4E01 NA4E11 50)1 50)1 87)1 87 n 5V , ANALOG CELL: OP-AMP; PMOS INPUT; CLASS AB OUTPUT AMP017 328.5(1 200(1 VDDA COMPARATORS ANALOG CELL


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PDF HBC2500 HBC2500 N03E CMP006 op-amp- 356 AMP016 transistor 2955 Analog Devices Opamp 3-input xnor opamp 555 AMP017
8pin dual gate driver

Abstract: quad nand A-9788 udn5713m A-9798 UDS-5707H UDS-5733H dtl quad nand UDN5712M UDN5711M
Text: interface devices • Inputs compatible with DTL/TTL, PMOS , and CMOS • 300 mA output sink current capability per gate • High sustaining voltage: 80 volts • Hermetically-sealed packages to MIL-M , -pin Dual In-Line H QUAD NAND DRIVER QUAD NOR DRIVER Veci 1 lj \2_ J4l n" n* cC jT"] |~6_ Vl [~7 , DUAL AND DRIVER UDN-5711M/H UDS-5711H UDS-5711H MIL DUAL NAND DRIVER DWG. NO. 4-9790 UDN-5712M/H


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PDF MIL-M-38510 MIL-STD-883, 16-PIN UDN-5703A/H UDS-5703H UDN-5706A/H UDS-5706H 8pin dual gate driver quad nand A-9788 udn5713m A-9798 UDS-5707H UDS-5733H dtl quad nand UDN5712M UDN5711M
C04-013

Abstract: 74ls10 IC CMOS 4000B series rca 74 HC Series ICs C04013
Text: HCT10, a triple 3-input NAND Gate , are being driven by a TTL device with a 50% duty cycle. Given the , technologies is shown in Fig. 7, In the o r« < Û . oc < z 90 30 · figure, a 2-input NAND gate is used to , . Application Notes QUAD 3 INPUT NAND GATE D U A L FLIP F LO P FREQUENCY (H i , illustrate this discussion. In the quiescent state, either the PMOS or NMOS transistor is fully off, and , the PMOS and NMOS transistors of the input stage, Fig. 1(a), being on, at least to some degree, at the


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PDF SSD-290. C04-013 74ls10 IC CMOS 4000B series rca 74 HC Series ICs C04013
1997 - cmos XOR schmitt trigger

Abstract: 5D208 D flip flop 8 bit XOR Gates AOI gate d flip flop 0.8um cmos CMOS OR Gates XOR schmitt trigger delay reset flip flop 5D048
Text: impedance PMOS ­ High impedance NMOS 14th Aug '97 HT5D 0.8µm CMOS High Speed Gate Array HT-5D Series · · · · · · · · 0.8µm single poly, double metal CMOS technology Sea of gate architecture Operating voltage 5V Propagation delay 0.3ns for 2-input NAND with fanout=2 Output driving , HT3A COMS Low Cost Gate Array General Features · · · · · · · · 5µm LOVAG CMOS , x1, x2, x3 ­ NAND 2inputs, 3inputs, 4inputs, 5inputs ­ NOR 2inputs, 3inputs, 4inputs, 5inputs


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PDF HTA3000 HT3A000 HT3A100 HT3A200 HT3A300 HT3A400 32DIP 40DIP 48DIP 24Skinny cmos XOR schmitt trigger 5D208 D flip flop 8 bit XOR Gates AOI gate d flip flop 0.8um cmos CMOS OR Gates XOR schmitt trigger delay reset flip flop 5D048
ad654 spice

Abstract: DARLINGTON TRANSISTOR ARRAY AD75019
Text: P OP O O S H S MWU M LA T P M NM OS (ENHANCEM ENT) v ./ ' IM L N PA T NMOS PMOS , V Process MOSFETs NMOS Bvdss V to BJTs B V Ce o Beta PMOS > 10V +0.75 V > 10V , with 2to 3-|a design rules and 500-A gate ox­ ide for ±5-volt supplies, and one with 5-^. design rules and 1000-A gate oxide for ± 15-volt supply circuits. distortion levels below - 7 5 dB. Gate , SOURCE GATE DRAIN SILÖX PNP BIPOLAR TRANSISTOR \\ r pou T5ZTC EJ DRAIN CATE


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Not Available

Abstract: No abstract text available
Text: . FIGURE 4. 2-INPUT NAND GATE VDD O OUT FIGURE 5. 2-INPUT NOR GATE VDD A OUT B O , 3-Input NOR 4-Input NAND The underpasses used throughout the gate arrays are highly doped poly , buffer array b u ffer GATE CAPACITANCE .16 2.50 .16 2.50 Inverter 2-Input NAND 2 , High Reliability Fast CMOS Gate Arrays UNIVERSAL SEMICONDUCTOR INC. ranging from 100 to 6000 , supply voltage Ease of Breadboarding Ease of Interface The ISO series of gate arrays are


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NPN Transistor PT7

Abstract: ITT K12 series switch T flip flop IC UTM RESISTOR 214 24 volt 6 amp power supply chips kaa x5 amd k10 resistor 10 kohm P144 Toggle flip flop IC
Text: 2 16 * K1 Dual Transmission Gate 2 16 * K2 Two Input NAND 2 16 * K3 Two Input NOR 2 16 * K4 Four , CHARACTERISTICS The PGA Family consists of six metal gate CMOS arrays with chip area increasing progressively , Micron Split Gate Analog/Digital Transistors Each 10 micron split gate analog/digital transistor has , current variation of less than 1 percent per volt for NMOS transistors and 2 percent per volt for PMOS , channel lengths in both NMOS and PMOS (fig 3). The high impedance transistors (N channel at 1 megohm and P


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PDF 0G00113 T-42-1? NPN Transistor PT7 ITT K12 series switch T flip flop IC UTM RESISTOR 214 24 volt 6 amp power supply chips kaa x5 amd k10 resistor 10 kohm P144 Toggle flip flop IC
ultrasound transducer circuit driver

Abstract: ultrasound driver design ultrasound transducer high power driver Piezoelectric ultrasound Transducer 3.3V 0.22F MD1813K6-G pMOS NAND GATE TC6320 TC2320 3.3v to 5v logic level shifter
Text: pre-charging the coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS. A built-in level shifter is for PMOS gate negative bias driving. It enables the , a high-speed quad MOSFET driver. It is designed to drive two Nand two P-channel, high voltage, DMOS


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PDF MD1813 -100V TC6320 TC2320 QFN-16 MD1813 MD1813K6-G 16-Lead ultrasound transducer circuit driver ultrasound driver design ultrasound transducer high power driver Piezoelectric ultrasound Transducer 3.3V 0.22F MD1813K6-G pMOS NAND GATE TC6320 TC2320 3.3v to 5v logic level shifter
2010 - IL311ANM

Abstract: tda8362b ILa1519B1Q iff4n60 IN1307N tda8890 IL311AN IL91214AN MC74HC123AN IL258D
Text: No file text available


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pMOS NAND GATE

Abstract: A540B ISO-5
Text: PMOS transistors together with a poly underpass as shown in Figure 2. Note that each gate is common to , -lnput NAND 4.2 5.2 4.7 TABLE 6. ISO-3 FAMILY OF ARRAYS Typical Gate Delays (ns) F.O . = 2 GATE , Typical Gate Delays (ns) F.O, = 2 GATE TYPE Tr T, Tpd Inverter .8 .7 .7 2-lnput NAND .9 .9 .9 2 , UNIVERSAL SEMICONDUCTORS HE □ | 13ba311 000D0M5 3 | _T- High Reliability Fast CMOS Gate , €”45% of supply voltage • Ease of Breadboarding • Ease of Interface ISO-5/ISO-3/ISO-2 GATE ARRAY


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PDF 13ba311 000D0M5 410x410 390x390 pMOS NAND GATE A540B ISO-5
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