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UPD17P103GS UPD17P103GS ECAD Model Renesas Electronics Corporation UPD17P103GS

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2005 - LCV14

Abstract: LCV11 dmos6 XRT83SL216 XRT83SL216IB
Text: REV. P1.0.3 GENERAL DESCRIPTION APPLICATIONS The XRT83SL216 is a fully integrated 16 , XRT83SL216 PRELIMINARY 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.3 FEATURES · Fully , INTERFACE UNIT REV. P1.0.3 FIGURE 2. PIN OUT FOR THE XRT83SL216 (BOTTOM VIEW) (See pin list for pin , PRELIMINARY 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT xr REV. P1.0.3 TABLE OF CONTENTS GENERAL , ) . 24 I xr REV. P1.0.3 PRELIMINARY XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE


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PDF XRT83SL216 16-CHANNEL XRT83SL216 LCV14 LCV11 dmos6 XRT83SL216IB
p103 t020

Abstract: 5A/p103 t020 upd78p356gc 16T MARKING D78356GD MSAB d27c1001 uPD78P356 RA78K3 marking 1AAA
Text: -O -O -O -O -O -O RESET P27/ T020 P26/TCLR2/T021 P25/INTP4 P24/INTP3 P23/INTP2 P22/INTP1/T005 , /ANI2 NC P73/ANI3 P74/ANI4 O O O O O' O O O O O O O O O P105/SCK11 P104/SI11 NC P103 /SQ11 , excluded.) NMI INTPO/T004 INTP1/T005 INTP2 INTP3 INTP4 TCLR2/T021 T020 I/O Port 3. 8-bit I/O port , pins (2/2) Pin P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P100 P101 P102 P103 P104 P105 P106 P107 , P32/SB0 P100 P103 P32/SOOO P33/SI00 o o I/O PWM signal output P86 P87 Output for the


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PDF uPD78P356 uPD78356 /xPD78P356. iPD78356 IEU-1361 p103 t020 5A/p103 t020 upd78p356gc 16T MARKING D78356GD MSAB d27c1001 RA78K3 marking 1AAA
2007 - XRK32308

Abstract: XRK32308-1 XRK32308-1H XRK32308-2 XRK32308CD-1 XRK32308CDTR-1 P103
Text: XRK32308 PRELIMINARY 3.3V ZERO DELAY BUFFER FEBRUARY 2007 REV. P1.0.3 GENERAL , BUFFER REV. P1.0.3 TABLE 1: PIN D ESCRIPTION PIN SIGNAL DESCRIPTION SOIC/TSSOP QFN 1 , XRK32308 3.3V ZERO DELAY BUFFER REV. P1.0.3 TABLE 3: AVAILABLE XRK32308 CONFIGURATIONS DEVICE , . P1.0.3 TABLE 4: ABSOLUTE MAXIMUM RATINGS Supply Voltage to Ground Potential -0.5V to +7.0V , ) IOH= -12mA (-1H, -5H) 4 PRELIMINARY XRK32308 3.3V ZERO DELAY BUFFER REV. P1.0.3 TABLE


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PDF XRK32308 XRK32308 XRK32308-1 XRK32308-1H XRK32308-2 XRK32308CD-1 XRK32308CDTR-1 P103
2003 - MAX9111ESA

Abstract: No abstract text available
Text: áç JANUARY 2003 XRT8020 650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS REV. P1.0.3 , ) 668-7017 · www.exar.com XRT8020 650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS REV. P1.0.3 áç , áç XRT8020 650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS REV. P1.0.3 ABSOLUTE MAXIMUM , 650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS REV. P1.0.3 áç ELECTRICAL SPECIFICATIONS , % TR TF 4 áç XRT8020 650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS REV. P1.0.3


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PDF XRT8020 XRT8020 MAX9111ESA
2004 - 32176 Group PWM CODE

Abstract: M32176FnVFP sfr32176 P103 P104 P105 P106 P153
Text: TO 11 ( P103 ) S F/F12 TO 12 (P104) S F/F13 TO 13 (P105) S F/F14 TO 14 (P106 , : FP11) · Set the F/F11 output initial value to "0". (FFD0: FD11) · Set P103 operation mode bit of P10 , enable bit. (TIOPRO: TIO0PRO) · Stop TIO0 count. (TIOCEN: TIO0CEN) · Set P103 data bit in P10 Data Register to "0". (P10DATA: P103DT) · Set P103 direction bit in P10 Direction Register to output mode. (P10DIR: P103 DIR) · Set P103 operation mode bit in P10 Operation Mode Register to input/output port


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PDF REJ05B0678-0100/Rev M32176FnVFP, M32176FnTFP) 40MHz 32176 Group PWM CODE M32176FnVFP sfr32176 P103 P104 P105 P106 P153
2007 - dmo 365 r

Abstract: dmo 365 isolation transformer TX15 xn03 xn06 850C XRT83VSH316 XRT83VSH316IB
Text: . P1.0.3 GENERAL DESCRIPTION for external timing (8kHz, 1.544Mhz, 2.048Mhz, nxT1/J1, nxE1). , SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.3 FEATURES · Fully integrated 16-Channel short haul , ) -400C to +850C 2 PRELIMINARY REV. P1.0.3 XRT83VSH316 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE , SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.3 TABLE OF CONTENTS FIGURE 1. BLOCK DIAGRAM OF THE , ) . 36 I PRELIMINARY REV. P1.0.3 XRT83VSH316 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE


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PDF XRT83VSH316 16-CHANNEL 544Mhz, 048Mhz, XRT83VSH316 16-channel dmo 365 r dmo 365 isolation transformer TX15 xn03 xn06 850C XRT83VSH316IB
2010 - rvdt sensor

Abstract: LVDT
Text: LIPS® P103 SHORT STROKE LINEAR POSITION SENSOR Position feedback for industrial and , applications. Our P103 LIPS® (Linear Inductive Position Sensor) is an affordable, durable, accurate position , , or spring-loaded with a ball end. The P103 also offers a wide range of mechanical and electrical , . SPECIFICATION DIMENSIONS For full mechanical details see drawing P103 -11 Independent linearity < ± 0.25% @ 20 , 68-2-29: 40 g MTBF 350,000 hrs 40°C Gf Drawing List P103 -11 Sensor Outline Drawings, in AutoCAD® dwg or


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PDF IP65/IP67 rvdt sensor LVDT
2004 - p103

Abstract: No abstract text available
Text: áç AUGUST 2004 PRELIMINARY XRT83SL28 REV. P1.0.3 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE , UNIT REV. P1.0.3 áç PRELIMINARY FIGURE 2. HARDWARE MODE BLOCK DIAGRAM OF THE XRT83SL28 1 of , SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.3 · Fully integrated 8-Channel short haul transceivers for E1 , -40°C to +85°C 3 XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.3 áç , 34 35 36 4 áç PRELIMINARY XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.3


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PDF XRT83SL28 XRT83SL28 p103
2003 - DMO11

Abstract: DMO10 0X00 GR-253 GR-499-CORE XRT73R12 XRT73R12IB em7 120 cc11r
Text: XRT73R12 PRELIMINARY TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT OCTOBER 2003 REV. P1.0.3 , ) 668-7017 · www.exar.com XRT73R12 PRELIMINARY REV. P1.0.3 TWELVE CHANNEL E3/DS3/STS-1 LINE , PRELIMINARY REV. P1.0.3 TABLE OF CONTENTS GENERAL DESCRIPTION , . 29 I XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.0.3 , ) . 63 II XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.0.3


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PDF XRT73R12 XRT73R12 DMO11 DMO10 0X00 GR-253 GR-499-CORE XRT73R12IB em7 120 cc11r
2008 - inductive displacement sensors

Abstract: No abstract text available
Text: LIPS® P103 SHORT STROKE LINEAR POSITION SENSOR Position feedback for industrial and , applications. Our P103 LIPS® (Linear Inductive Position Sensor) is an affordable, durable, accurate position , , or spring-loaded with a ball end. The P103 also offers a wide range of mechanical and electrical , . SPECIFICATION DIMENSIONS For full mechanical details see drawing P103 -11 Independent linearity < ± 0.25% @ 20 , Vibration IEC 68-2-6: 10g Shock IEC 68-2-29: 40 g MTBF 350,000 hrs 40°C Gf Drawing List P103 -11 Sensor


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PDF IP65/IP67 inductive displacement sensors
2002 - G703

Abstract: No abstract text available
Text: áç DECEMBER 2002 PRELIMINARY XRT85L61 REV. P1.0.3 BITS (BUILDING INTEGRATED TIMING , www.exar.com áç PRELIMINARY XRT85L61 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR REV. P1.0.3 , BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR REV. P1.0.3 áç PRELIMINARY TABLE OF , INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR REV. P1.0.3 TYPE I DESCRIPTION Reference T1 Clock input , INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR REV. P1.0.3 áç PRELIMINARY PIN DESCRIPTIONS PIN # 11


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PDF XRT85L61 XRT85L61 64KHz 544Mbps) 048Mbps) 2048kHz 32-bit G703
2001 - Not Available

Abstract: No abstract text available
Text: áç MARCH 2002 PRELIMINARY XRT83SL38 REV. P1.0.3 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK , www.exar.com XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.0.3 , XRT83SL38 REV. P1.0.3 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR , . 76 III áç XRT83SL38 REV. P1.0.3 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY , TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.0.3 áç PRELIMINARY PIN # 1 TYPE O


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PDF XRT83SL38 XRT83SL38 544Mbps) 048Mbps)
2005 - chn 542

Abstract: No abstract text available
Text: xr FEBRUARY 2005 PRELIMINARY XRT86VL32 DUAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.3 , · FAX (510) 668-7017 · www.exar.com xr REV. P1.0.3 PRELIMINARY XRT86VL32 DUAL T1/E1/J1 , data link information 2 XRT86VL32 DUAL T1/E1/J1 FRAMER/LIU COMBO PRELIMINARY xr REV. P1.0.3 , /E1/J1 FRAMER/LIU COMBO PRELIMINARY LIST OF PARAGRAPHS XRT86VL32 REV. P1.0.3 1.0 , . 188 I XRT86VL32 REV. P1.0.3 PRELIMINARY xr DUAL T1/E1/J1 FRAMER/LIU COMBO 4.7.6


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PDF XRT86VL32 XRT86VL32 chn 542
2005 - Not Available

Abstract: No abstract text available
Text: xr JANUARY 2005 PRELIMINARY XRT91L80 REV. P1.0.3 2.488/2.666GBPS OC-48/STM-16 SONET/SDH , OC-48/STM-16 SONET/SDH TRANSCEIVER FEATURES xr REV. P1.0.3 · 2.488 / 2.666 Gbps Transceiver · , 2 REV. P1.0.3 xr FIGURE 2. 196 BGA PINOUT OF THE XRT91L80 (TOP VIEW) A AGND_RX , . P1.0.3 4 xr REV. P1.0.3 PRELIMINARY XRT91L80 2.488/2.666GBPS OC-48/STM-16 SONET/SDH , . 25 I XRT91L80 PRELIMINARY 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER xr REV. P1.0.3


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PDF XRT91L80 666GBPS OC-48/STM-16 XRT91L80 OC-48
2003 - dmo 365 r

Abstract: RUR 117-5 E1 HDB3 GR-499-CORE GR-253 17X17 XRT79L71IB XRT79L71 PC403 0X1157
Text: áç PRELIMINARY XRT79L71 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC JUNE 2003 REV. P1.0.3 , . P1.0.3 · 8/16 bit UTOPIA Level I and II and PPP Multi-PHY RECEIVE CELL PROCESSING · , CHANNEL DS3/E3 ATM UNI/PPP COMBO IC áç XRT79L71 REV. P1.0.3 TABLE 1: PIN OUT OF THE XRT79L71 (TOP VIEW) XRT79L71 PRELIMINARY áç 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC REV. P1.0.3 , PRELIMINARY 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC XRT79L71 REV. P1.0.3 E3 LINE SIDE PARAMETERS


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PDF XRT79L71 XRT79L71 dmo 365 r RUR 117-5 E1 HDB3 GR-499-CORE GR-253 17X17 XRT79L71IB PC403 0X1157
2000 - ict TRANSFORMER

Abstract: No abstract text available
Text: áç SEPTEMBER 2000 PRELIMINARY XRT73L00 E3/DS3/STS-1 LINE INTERFACE UNIT REV. P1.0.3 , REV. P1.0.3 áç PRELIMINARY ORDERING INFORMATION PART NUMBER XRT73L00IV PACKAGE TYPE 44 Pin , /(ENDECDIS) 22 CS/(DR/SR) 2 áç E3/DS3/STS-1 LINE INTERFACE UNIT XRT73L00 REV. P1.0.3 , . 25 I XRT73L00 REV. P1.0.3 E3/DS3/STS-1 LINE INTERFACE UNIT áç 25 25 25 25 25 25 26 , Receive Section II áç E3/DS3/STS-1 LINE INTERFACE UNIT XRT73L00 REV. P1.0.3 of the


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PDF XRT73L00 XRT73L00 ict TRANSFORMER
2002 - STM-16

Abstract: XRT91L81 XRT91L81IB STM-16 LIU B30 ferrite
Text: . P1.0.3 GENERAL DESCRIPTION an overflow condition. The operation of the device can be monitored , /2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER PRELIMINARY REV. P1.0.3 · Selectable full duplex , /2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER PRELIMINARY REV. P1.0.3 TABLE 1: 196 BGA PINOUT OF THE XRT91L81 (TOP VIEW) XRT91L81 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER REV. P1.0.3 , . 23 I PRELIMINARY XRT91L81 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER REV. P1.0.3


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PDF XRT91L81 666GBPS OC-48/STM-16 XRT91L81 OC-48 STM-16 XRT91L81IB STM-16 LIU B30 ferrite
2003 - rneg2

Abstract: XRT83L314 XRT83L314IB
Text: 2003 REV. P1.0.3 GENERAL DESCRIPTION Additional features include RLOS, a 16-bit LCV counter , INTERFACE UNIT PRELIMINARY REV. P1.0.3 · Receive monitor mode handles 0 to 29dB resistive , /J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.3 PIN OUT OF THE XRT83L314 XRT83L314 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY REV. P1.0.3 TABLE , REV. P1.0.3 FIGURE 17. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN


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PDF XRT83L314 14-CHANNEL 16-bit XRT83L314 rneg2 XRT83L314IB
2003 - Not Available

Abstract: No abstract text available
Text: PRELIMINARY JUNE 2003 XR16L2550 REV. P1.0.3 LOW VOLTAGE DUART WITH 16-BYTE FIFO GENERAL , -BYTE FIFO REV. P1.0.3 VCC CTSA# 38 RIA# CDA# 47 46 45 44 43 42 41 40 , IOW# NC XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO REV. P1.0.3 PRELIMINARY PIN , . P1.0.3 DESCRIPTION UART channel A Receiver Ready (active low). This output provides the RX FIFO , 14 8 O 4 XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO REV. P1.0.3 PRELIMINARY


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PDF XR16L2550 16-BYTE XR16L25501 L2550) XR16L2550 ST16C2550 L2550
2000 - uart 16c854

Abstract: No abstract text available
Text: xr FEBRUARY 2001 PRELIMINARY XR16L788 REV. P1.0.3 HIGH PERFORMANCE OCTAL UART GENERAL , ) 668-7017 · www.exar.com xr REV. P1.0.3 PRELIMINARY XR16L788 OCTAL UART FIGURE 2. PIN OUT OF , INT# VCC GND IOR# A7 A6 A5 A4 A3 A2 A1 A0 VCC GND CS# 2 XR16L788 OCTAL UART REV. P1.0.3 , . P1.0.3 PRELIMINARY XR16L788 OCTAL UART NAME RI0# TX1 RX1 PIN # 96 85 92 TYPE I O I , I O I I I O I 4 XR16L788 OCTAL UART REV. P1.0.3 PRELIMINARY xr NAME RTS4# CTS4


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PDF XR16L788 XR16L7881 XR16L758, uart 16c854
2003 - ST16C2550

Abstract: XR16L2550 XR16L2551 XR16L2551IL XR16L2551IM XR16L2751CM
Text: XR16L2551 PRELIMINARY LOW VOLTAGE DUART WITH POWERSAVE JUNE 2003 REV. P1.0.3 FEATURES , ) 668-7017 · www.exar.com XR16L2551 LOW VOLTAGE DUART WITH POWERSAVE PRELIMINARY REV. P1.0.3 , XR16L2551 LOW VOLTAGE DUART WITH POWERSAVE PRELIMINARY REV. P1.0.3 PIN DESCRIPTIONS Pin , PRELIMINARY REV. P1.0.3 Pin Description 32-QFN PIN # 48-TQFP PIN # TYPE DESCRIPTION , XR16L2551 LOW VOLTAGE DUART WITH POWERSAVE PRELIMINARY REV. P1.0.3 Pin Description NAME 32


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PDF XR16L2551 L2551) ST16C2550: L2551 ST16C2550 XR16L2550. XR16L2550 XR16L2551 XR16L2551IL XR16L2551IM XR16L2751CM
2001 - FIFO memory

Abstract: ST16C650A
Text: áç MAY 2001 PRELIMINARY XR16L651 REV. P1.0.3 2.5V, 3.3V AND 5V LOW POWER UART WITH 32 , ) 668-7017 · www.exar.com XR16L651 P1.0.3 2.5V, 3.3V AND 5V LOW POWER UART WITH 32-BYTE FIFO áç , 2.5V, 3.3 AND 5V LOW POWER UART WITH 32-BYTE FIFO REV. P1.0.3 NOTE: Pin type: I=Input, O=Output, IO , 9 CS1 10 CS2# 11 INT (INT#) 30 3 XR16L651 P1.0.3 2.5V, 3.3V AND 5V LOW , PRELIMINARY NAME CTS# PIN # 39 TYPE I XR16L651 2.5V, 3.3 AND 5V LOW POWER UART WITH 32-BYTE FIFO REV. P1.0.3


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PDF XR16L651 32-BYTE XR16L6511 16C450, 16C550, ST16C580 ST16C650A 16C550 FIFO memory
2001 - TU12

Abstract: XRT81L27 XRT81L27IV rdat
Text: 2001 REV. P1.0.3 GENERAL DESCRIPTION The XRT81L27 is an optimized seven-channel, analog, 3.3V , E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY PRELIMINARY REV. P1.0.3 ORDERING INFORMATION , CLOCK RECOVERY REV. P1.0.3 TABLE OF CONTENTS GENERAL DESCRIPTION , REV. P1.0.3 PIN DESCRIPTIONS PIN # NAME TYPE DESCRIPTION 1 RClk1 O Receiver 1 , PRELIMINARY REV. P1.0.3 PIN # NAME TYPE DESCRIPTION 21 RRing5 I Receiver 5 Bipolar


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PDF XRT81L27 XRT81L27 21-channel TU12 XRT81L27IV rdat
2003 - Not Available

Abstract: No abstract text available
Text: PRELIMINARY JUNE 2003 XR16L2552 REV. P1.0.3 2.25V TO 5.5V DUART WITH 16-BYTE FIFO , XR16L2552 2.25V TO 5.5V DUART WITH 16-BYTE FIFO REV. P1.0.3 48-TQFP PACKAGE TXRDYA# DSRA# RIA# CTSA# 38 , WITH 16-BYTE FIFO REV. P1.0.3 PRELIMINARY xr PIN DESCRIPTIONS Pin Description NAME 48 , 5.5V DUART WITH 16-BYTE FIFO REV. P1.0.3 DESCRIPTION UART channel B Receiver Ready (active low). , CDB# 26 30 I 4 XR16L2552 2.25V TO 5.5V DUART WITH 16-BYTE FIFO REV. P1.0.3


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PDF XR16L2552 16-BYTE L2552) XR16L2552 ST16C2552 L2552
Not Available

Abstract: No abstract text available
Text: strobe WAIT Wait CLKOUT Clock output T020 , T021 T CLR0-T CLR2 T C LR U D J j- Timer , T020 P31 Port 3. TxD 8-bit I/O port I/O RxD Can be specified a s input or output , . S010 8-bit I/O port. suo Can be specified a s input or output bit by bit. SC K 1 0 P103 , /T005 Output state : Open P23/INTP2 P24/INTP3 P25/INTP4 P26/TCLR2/T021 P27/ T020 P30/TxD 5 , separate resistor. Output state : Open P102/SCK10 P103 /S011 5-A P104/SI11 8-A P105/SCK11


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PDF PD78P356 /iPD78P356 pPD78356 PD78356 U10669E IEU-1395 /JPD78P356 iPD7835
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