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Part ECAD Model Manufacturer Description Datasheet Download Buy Part
HMC729LC3C HMC729LC3C ECAD Model Analog Devices Inc 26 GHz, T Flip-Flop w/Reset
123576-HMC729LC3C 123576-HMC729LC3C ECAD Model Analog Devices Inc 26 GHz, T Flip-Flop w/Reset

of D-flip flop Datasheets Context Search

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siemens master drive circuit diagram

Abstract: SR flip flop IC toshiba tc110g TC110G jk flip flop to d flip flop conversion SC11C1 JK flip flop IC siemens Nand gate scxc1 SR flip flop IC pin diagram
Text: source of Toshiba TC110G family Densities up to 129,000 raw gates Channelless " sea of gates , DESCRIPTION The SCxC1 Series Gate Arrays is a product family of 1.5 micron (drawn) CMOS devices featuring internal gate speeds which are equivalent to those of 10K ECL. True system integration is achievable with , and 256 signal I/O pads. The channelless " sea of gates" architecture of the base arrays allows for efficient place ment and routing of complex design functions, including compiled RAM and ROM blocks. This


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PDF TC110G M33S004 siemens master drive circuit diagram SR flip flop IC toshiba tc110g jk flip flop to d flip flop conversion SC11C1 JK flip flop IC siemens Nand gate scxc1 SR flip flop IC pin diagram
2000 - KGL4205

Abstract: D flip flop IC
Text: -Gbps D-Flip Flop IC 0.2µm Gate Length GaAs MESFET Technology February 2000 s s ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ Oki Semiconductor KGL4205 10-Gbps GaAs D-Flip Flop IC INTRODUCTION Oki Semiconductor's KGL4205 is a 10-Gbps D-Flip Flop IC designed for ultra high-speed digital communications systems. The KGL4205 uses 0.2-µm gate length GaAs MESFETs and Oki's unique MCFF ( Memory Cell type Flip Flop ) technology to achieve operations of 10-GHz or more. The KGL4205 is available as a 24-pin ceramic packaged


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PDF KGL4205 10-Gbps KGL4205 10-GHz 24-pin D flip flop IC
A138G2

Abstract: t166h TTL catalog binary counters with D-flip flop 2-bit adder layout ON48 nand gate layout Q6600C T175 AN14
Text: . not including metal) Maximum flip/ flop toggle frequency Typical TTL input delay (includes a fanout of , hard-wired macros consisting of powerful MSI, I/O, logic and storage macros, characterized for immediate use , Q6000 series logic arrays offer a wide selection of I/O macros which are compatible with CMOS and TTL systems using a single +5V power supply. DESCRIPTION The AMCC Q6000 2jjl CMOS array series consists of the Q1400C, Q1750C, Q2700C, Q3300C, Q4300C and Q6600C arrays. This series of arrays provides gate


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PDF Q6000 Q1400C Q6600C. A138G2 t166h TTL catalog binary counters with D-flip flop 2-bit adder layout ON48 nand gate layout Q6600C T175 AN14
of D-flip flop

Abstract: MTC55
Text: MIXED SIGNAL INTEGRATED CIRCUIT PRODUCTS 12 Gb/s D-Flip/ Flop with Slice Amplifier MTC5505 Preliminary Data Sheet Applications · Retiming of transmit data · Decision of received data Features , D-Flip/ Flop with Slice Amplifier MTC5505 Preliminary Data Sheet Absolute Maximum Ratings Caution , SIGNAL INTEGRATED CIRCUIT PRODUCTS 12 Gb/s D-Flip/ Flop with Slice Amplifier MTC5505 Preliminary , D-Flip/ Flop with Slice Amplifier MTC5505 Preliminary Data Sheet Typical Output Response (VEE =


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PDF MTC5505 MTC5505 07-99L of D-flip flop MTC55
2007 - DS-406

Abstract: 124u DS406 Processor System Reset Module v2.00a
Text: flop . In general each unique bus should receive a different copy of this signal. To help equalize , registered through a D-flip flop . In general each peripheral should receive a different copy of this signal , . The parameterizable features of designs are discussed in the Design Parameters section. Core , ® 11.4 or later · Sequencing of reset signals coming out of reset: Verification ModelSim PE , - Peripheral(s) come out of reset 16 clocks later - N/A Verification Design Tool


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PDF DS406 DS-406 124u Processor System Reset Module v2.00a
X328 transistor

Abstract: scx6206 transistor x328 SCX6218 SCX6225 MEA 2901 x328 SCX6244 scx6232 SM8250A
Text: WjWM National /¡/m Semiconductor mUm Corporation Description of Gate Arrays and Standard Cells , channel length. The 2 micron family of gate arrays offers complexities from 600 to 8700 gates with utilization factors of >95% typically. 2 micron standard cells are available up to about 15000 gate equivalents. They offer a wide range of fixed height cells (SSI/MSI functions) and a number of LSIs, called Functional Blocks. The basic building block of National's Gate Arrays, a 16transistor cell, is described


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PDF 128x8 SM8250A SM8250B 250A/16450 8250-B/8250J-B SM2901 SM2909 SM2911 0Q72122 X328 transistor scx6206 transistor x328 SCX6218 SCX6225 MEA 2901 x328 SCX6244 scx6232
2008 - ic CD4040 application

Abstract: PLL CD4046 application CD4046 pll application note Hsync Vsync RGB HC4046 pll application note HSYNC, VSYNC counter SoG to hsync vsync PLL cd4046 DATASHEET OF IC CD4040 CD4046 application note
Text: rising edge, the flip/ flop Q output will go high on the rising edge of the PLL's HSYNC, thus indicating , compensate for the setup and hold of the D flip/ flop . Delaying the PLL Q4 (PLL HSYNC) by 120ns and delaying , . ISL59885 CSYNC OUTPUT Problem ISL59885 VSYNC OUTPUT It is not uncommon to experience corruption of , the HSYNC to be missing or be out of sync with the source. Also, not all monitors have adequate , the corrupted HSYNC will generate distortion at the top of the LCD displays or not sync at all


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PDF TB476 ISL59885 ic CD4040 application PLL CD4046 application CD4046 pll application note Hsync Vsync RGB HC4046 pll application note HSYNC, VSYNC counter SoG to hsync vsync PLL cd4046 DATASHEET OF IC CD4040 CD4046 application note
gaas D flip flop

Abstract: No abstract text available
Text: O K I electronic components_ KGL6060_ Ultra high-speed logic 1C D-Flip Flop G ENERAL DESCRIPTIO N The KGL6000 family are the ultra high-speed GaAs devices. W ith our unique M CFF (memory cell type flip-flop) technology, ultra high-speed operation of 5 GHz or more has been realized , com ponents KGL6060 28 20 PRO DUCTIO N NA M E C O M P A N Y LOGO COUNTRY OF M ANUFACTU RE , EST DIGIT) B LO C K DIAGRAM KGL 6060 D Flip Flop 153 KGL6060 OKI electronic com


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PDF KGL6060_ KGL6000 gaas D flip flop
1996 - 10E431

Abstract: 10E131 10H131 AN1504 10E101 DL140 ECL 100151 DL140-D Rennie
Text: . Dover Todd Pearson ECLinPS Applications Engineering This application note examines the concept of metastability and provides a theoretical discussion of how it occurs, including examples of the metastable , presented. Metastability results are then applied to the ECLinPS family. ECLinPS is a trademark of , ECLinPS Family Introduction state. Case 3 represents a violation of the set-up and hold times whereby , state is indeterminate. Further, the final settling state of the flip-flop having been in this


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PDF AN1504 DL140 AN1504/D* AN1504/D 10E431 10E131 10H131 AN1504 10E101 ECL 100151 DL140-D Rennie
74hc273

Abstract: 74HC273 Toshiba
Text: ) = CpD · Vcc · f]N + lc0/8 (per F/F) And the total CPD when n pcs. of Flip Flop operate can be gained , TOSHIBA TC74LVQ273F/FW/FS Octal D - type flip Flop With Clear The TC74LVQ273 is a high speed CMOS OCTAL D-FLIP FLOP fabricated with silicon gate and double-layer metal wir ing C2MOS technology , going edge of the clock pulse. When the CLR input is held low, the Q outputs are in the low logic level independent of the other inputs. All inputs are equipped with protection circuits against static discharge or


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PDF TC74LVQ273F/FW/FS TC74LVQ273 S0120--P--300) 74hc273 74HC273 Toshiba
3h91

Abstract: No abstract text available
Text: TOSHIBA TC74LVQ174F/EN/FS Hex D - Type Flip Flop With Clear The TC74LVQ174 is a high speed C M O S HEX D-FLIP FLOP fabricated with silicon gate and double-layer metal wiring C 2M O S technology , positive going edge of the clock pulse. When the CLR input is held low, the Q output are in the low logic level independent of the other inputs. All inputs are equipped with protection circuits against static , ) Parameter guaranteed by design. Note (3) C PD is defined as the value of the internal equivalent capacitance


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PDF TC74LVQ174F/EN/FS TC74LVQ174 3h91
74hc273

Abstract: tc741
Text: TC74LVQ273F/FW/FS OCTAL D-TYPE FLIP FLOP WITH CLEAR The TC74LVQ273 is a high speed CMOS OCTAL D-FLIP FLOP fabricated w ith silicon gate and double-layer metal w iring C2M OS technology. Designed for , edge of the clock pulse. W h e n the CLR input is held low, the Q outputs are in the low logic level independent of the other inputs. All inputs are equipped with protection circuits against static discharge or , 'C C 18 (P er F ' F) A nd th e to tal C po w h e n n pcs. o f Flip Flop o p era te can be gain ed by


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PDF TC74LVQ273F/FW/FS TC74LVQ273 160MHz TC741VQ273F/FW/FS 74hc273 tc741
HA 1370 schematics

Abstract: CMOS XNOR XOR NAND2 NAND3 ic ttl and not xor nor xnor or MICRON POWER RESISTOR 2W ECL IC NAND
Text: family of mixed ECL and BiCMOS gale arrays based on National's revolutionary 0.8 micron drawn ABiC BiCMOS process. The NGM Series is the first commercially available gate array to feature a mixture of ECL and BiCMOS internal cells for applications requiring the high performance of ECL and low power of CMOS , . The internal CMOS macros have the option of being used with or without bipolar output drive , BiCMOS Industry first mixture of ECL and BiCMOS internal gates High performance ECL: typical delay =


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PDF TL/U/10861-4 HA 1370 schematics CMOS XNOR XOR NAND2 NAND3 ic ttl and not xor nor xnor or MICRON POWER RESISTOR 2W ECL IC NAND
TC7WH74FU

Abstract: No abstract text available
Text: D-TYPE FLIP FLOP WITH PRESET AND CLEAR The TC7WH74FU is an advanced high speed CMOS D-FLIP FLOP , INPUT is transferred to Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input low. An input protection circuit , (TOP VIEW) 961001EBA2 0 TOSHIBA is continually working to improve the quality and the reliability of , inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer


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PDF TC7WH74FU TC7WH74FU
Not Available

Abstract: No abstract text available
Text: S IL IC O N T O S H IB A M O N O L IT H IC CM O S D IG IT A L IN T E G R A T E D C IR C U IT TC7WH74FU D-TYPE FLIP FLOP WITH PRESET AND CLEAR The TC7WH74FU is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate CMOS technology. It achieves the high speed , transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the , ) : Cpo is defined as the value of the internal equivalent capacitance which is calculated from the


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PDF TC7WH74FU TC7WH74FU
2005 - TC7WT74FU

Abstract: No abstract text available
Text: Flop with Preset and Clear The TC7WT74FU is high speed CMOS D-FLIP FLOP fabricated with silicon gate , the positive going trasition of the CK pulse. CLEAR and PRESET are independent of the CK and are , MHz Note: CPD is defined as the value of the internal equivalent capacitance which is calculated , presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No


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PDF TC7WT74FU TC7WT74FU
Not Available

Abstract: No abstract text available
Text: /8 (Per F /F ) And the total Cpp when n pcs. of Flip Flop operate can be gained by the follow ing , TC74LVX374F/FW/FS OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUT The TC74LVX374 is a high speed CMOS O CTAL D-FLIP FLOP fabricated with silicon gate C2MOS technology. Designed for use in 3.3 Volt systems, it achieves high speed operation w hile m aintaining the CMOS low power dissipation. This device , defined as the value of the internal equivalent capacitance which is calculated from the operating current


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PDF TC74LVX374F/FW/FS TC74LVX374
74HC374

Abstract: TC74LVX374F TC74LVX374FT TC74LVX374FW
Text: ) And the total Cpp when n pes. of Flip Flop operate can be gained by the following equation : CpD , TC74LVX374F, TC74LVX374FW, TC74LVX374FT OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUT The TC74LVX374 is a high speed CMOS OCTAL D-FLIP FLOP fabricated with silicon gate C2MOS technology. Designed for use in 3.3 Volt , quality and the reliability of its products. Nevertheless, semiconductor devices in general can , the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and


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PDF TC74LVX374F/FW/FT TC74LVX374F, TC74LVX374FW, TC74LVX374FT TC74LVX374 OP20-P-300-1 685typ SOL20-P-300-1 74HC374 TC74LVX374F TC74LVX374FT TC74LVX374FW
Not Available

Abstract: No abstract text available
Text: when n pcs. of Flip Flop operate can be gained by the following equation : CpQ (total) = 20 + 12 ·n , TC74LVX374F, TC74LVX374FW, TC74LVX374FT OCTAL D-TYPE FLIP FLOP W IT H 3-STATE OUTPUT The TC74LVX374 is a high speed CMOS OCTAL D-FLIP FLOP fabricated with silicon gate C2MOS technology. Designed for use in , orking to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in , could cause loss of human life, bodily injury or dam age to property. In developing your designs, please


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PDF TC74LVX374F/FW/FT TC74LVX374F, TC74LVX374FW, TC74LVX374FT TC74LVX374 OP20-P-300-1 50L20-P-300-1
3055 la

Abstract: TC7WH74
Text: , TC7WH74FK D-TYPE FLIP FLOP WITH PRESET AND CLEAR The TC7WH74 is an advanced high speed CMOS D-FLIP FLOP , INPUT is transferred to 0 OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input low. An input protection circuit , 0 TOSHIBA is continually working to improve the quality and the reliability of its products , sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing


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PDF TC7WH74FU/FK TC7WH74FU, TC7WH74FK TC7WH74 3055 la
Not Available

Abstract: No abstract text available
Text: T T7 W T7 JFII M m m m (UNDER DEVELOPMENT) D-TYPE FLIP FLOP WITH PRESET AND CLEAR The TC7WT74FU is a high speed CMOS D-FLIP FLOP fabricated with silicon gate CMOS technology. It achieves the , the D-INPUT is tranceferred to Q-OUTPUT during the positive going transition of the CK pulse. CLEAR and PRESET are independent of the CK and are accomplished by setting the appropriate input low. All , # TOSHIBA is continually working to improve the quality and the reliability of its products


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PDF TC7WT74FU TC7WT74FU
GHz Ripple Counter

Abstract: MSI IC Dual 4-1 MUX TQ1112 tektronix custom synchronous counter using 4 flip flip TQ1121 TQ1122 TQ1131 TQ1132
Text: * TQ1112 The Q-LOGIC GaAs IC component series provides a new level of ultra high speed performance and system flexibility for applications in high-speed systems. Based upon the use of standard and custom , ranges and a wide range of power supply voltages. The series is built in the TriQuint ID MSI , , 2.5 GHz * TQ1134 1:4 DEMUX, 2.5 GHz * TQ1151 DUAL D-Flip/ Flop , 2 GHz TriQuint m This document


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PDF TQ1112 GHz Ripple Counter MSI IC Dual 4-1 MUX TQ1112 tektronix custom synchronous counter using 4 flip flip TQ1121 TQ1122 TQ1131 TQ1132
pin DIAGRAM OF IC 74HC74

Abstract: No abstract text available
Text: TOSHIBA T C 74L V Q 74 F / F N / F S QUAD D - Type Flip Flop With Preset and Clear The TC74LVQ74 is a high speed CMOS D-FLIP FLOP fabri cated with silicon gate and double-layer metal wiring C2MOS , positive going transition of the CK pulse._ CLR and PR are independent of the CK and are accom plished by , value of the internal equivalent capacitance which is calculated from the operating current consumption , U.S. Export Administration Regulators and may be subject to the approval of the U.S. Department of


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PDF TC74LVQ74 147MHz pin DIAGRAM OF IC 74HC74
TC7WT74FU

Abstract: No abstract text available
Text: TC7WT74FU (UNDER DEVELOPMENT) D-TYPE FLIP FLOP WITH PRESET AND CLEAR The TC7WT74FU is a high speed CMOS D-FLIP FLOP fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to , Q-OUTPUT during the positive going transition of the CK pulse. CLEAR and PRESET are independent of the CK , continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor , to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to


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PDF TC7WT74FU TC7WT74FU
Not Available

Abstract: No abstract text available
Text: TC74LVQ273F, TC74LVQ273FW TC74LVQ273FS DATA SILICON MONOLITHIC OCTAL D-TYPE FLIP FLOP W ITH CLEAR The TC74LVQ273 is a high speed CMOS OCTAL D-FLIP FLOP fabricated w ith silicon gate and double-layer , -225-0.65A : 0.09g (Typ.) The information contained herein 1$ presented only i t « guide for the applications of , CORPORATION or others. TOSHIBA Is continually working to improve th e quality and th e reliability of its , electrical sensitivity and vulnerability to physical stress, tt Is th e responsibility of th e buyer, when


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PDF TC74LVQ273F, TC74LVQ273FW TC74LVQ273FS TC74LVQ273 LVQ273FW SOL20-P-300-1 TC74LVQ273F
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