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LT1111CJ8 Linear Technology SWITCHING REG ADJ. OUT
LT1111CJ8-12 Linear Technology SWITCHING REG +12V OUT
LT3009ESC8-5.0#TRPBF Linear Technology IC REG LDO 5V 20MA SC70-8
LT1129CF-3.3#TR Linear Technology IC REG LDO 3.3V SHUTDOWN 20TSSOP
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nmos shift register Datasheets Context Search

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2007 - surface mounted transistor 1BW 17

Abstract: 74VHCT244AFT Hamamatsu Color sensor address MSTAR S390X
Text: shift register that addresses these switches. Figure 2-1 NMOS linear image sensor equivalent circuit , of NMOS linear image sensors 2-3. Signal readout by shift register As stated above, NMOS linear , . 4 2-3. Signal readout by shift register , ) . 23 4-9. Shift register frequency characteristics , INTEGRATION TIME START PULSE TO SHIFT REGISTER ADDRESS PULSE


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PDF SD-26 SE-171 KMPD9001E05 surface mounted transistor 1BW 17 74VHCT244AFT Hamamatsu Color sensor address MSTAR S390X
MB88307

Abstract: MB88306 DI 8306 nmos shift register
Text: supply ground pin. • Procastor Interface SI 14 1 Serial data input to the internal shift register : A data bit on the Si pin is shifted Into the MSB of the shift register at the rising edge (MB88306/7 , the internal shift register : The rising edge of SC (MB88306/7) or falling edge of SC (MB88308/9) shifts a data bit on the SI pin into the MSB of the shift register , each bit of the shift register Is shifted right, and the LSB of the shift register appears directly on the SO pin. A high level and low


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PDF 374T7LE 0004bELi T-S2-33 MB88306 MB88307 MB88308 MB88309 MBS8307 DI 8306 nmos shift register
KNC 201 15

Abstract: knc 201 knc 201 11 knc 201 interfacing m8830 MB88307 KNC 201 6
Text: -State NMOS Open Drain Shift Clock Trlggar Rising Edge Rising Edge Falling Edge Falling Edge MB88306/7/8/9 , Interface SI 14 I Serial data input to the internal shift register : A data bit on the SI pin is shifted into the MSB of the shift register at the rising edge (MB88306/7) of the shift clock SC or the falling , the SO pin of the cascaded devices. SC (SC) 4 I Shift clock input for the internal shift register , into the MSB of the shift register , each bit of the shift register is shifted right, and the LSB of the


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PDF MB88306 MB88307 MB88308 MB88309 DrainB88308 HB8830S KNC 201 15 knc 201 knc 201 11 knc 201 interfacing m8830 KNC 201 6
MB88307

Abstract: MB88306 DI 8306 lt 9306 lt 9306 diode nmos shift register
Text: that follows. Kxpandsr Output Shift Clock Trigger MB88306 CMOS 3-State Rising Edge MBB8307 NMOS Open , internal shift register : A data bit on the SI pin is shifted into the MSB of the shift register at the , ) 4 I Shift clock input for the internal shift register : The rising edge of SC (MB88306/7) or falling edge of SC (MB88308/9) shifts a data bit on the SI pin into the MSB of the shift register , each bit of the shift register is shifted right, and the LSB of the shift register appears directly on the SO pin


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PDF MB88306 MB88307 MB88308 MB88309 MBB8307 DI 8306 lt 9306 lt 9306 diode nmos shift register
MB88307

Abstract: MD-883 MB88300 mb89300
Text: -State NMOS Open Drain Shift Clock Trigger Rising Edge Rising Edge Falling Edge Falling Edge MB88306/7/6/9 , Interface SI 14 1 Serial data input to the internal shift register : A data bit on the Si pin is shifted into the MSB of the shift register at the rising edge (MB88306/7) of the shift clock SC or the falling , the SO pin of the cascaded devices. SC m 4 1 Shift clock input for the internal shift register : The , MSB of the shift register , each bit of the shift register Is shifted right, and the LSB of the shift


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PDF MB88306 MB88307 MB88308 MB88309 DIP-16P-M02) 10-LEAD MD-883 MB88300 mb89300
1996 - 11.059mHz crystal oscillator

Abstract: 80C51 80C51 family hardware
Text: 1 0 1 Mode 0 1 2 3 Description shift register 8-bit UART 9-bit UART 9-bit UART , position of the shift register , then the 1 that was initially loaded into the 9th position, is just to the , the 9th position of the transmit shift register and tells the TX Control block to commence a , machine cycle, the RX Control unit writes the bits 11111110 to the receive shift register , and in the , machine cycle in which RECEIVE is active, the contents of the receive shift register are shifted to the


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PDF 80C51 80C51 SU00559 SU00560 11.059mHz crystal oscillator 80C51 family hardware
1998 - HD44780U

Abstract: HD61830B HD66002 HD66002FS HD66710 HD66712 HD66720 HD66730
Text: CL1 80-bit latch circuit DIOL DIOR DR DL 80-bit bi-directional shift register (also used , signal. 80-bit latch circuit Latches data of the 80-bit bi-directional shift register (also used as a , . 80-bit bi-directional shift register (also used as a latch circuit) When FCS is low, this register functions as an 80-bit shift register . At this time, DIOL and DIOR are used as data input/output pins. When , the latch circuit is maintained. Operating mode switching circuit Switches shift register operation


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PDF HD66002 80-Channel HD66002 HD44780U HD61830B HD66002FS HD66710 HD66712 HD66720 HD66730
2014 - Not Available

Abstract: No abstract text available
Text: circuit st 1 Clock 2 s Active area structure Digital shift register (MOS shift register , ) Description Pulses for operating the MOS shift register . The video data rate is equal to the clock pulse , starting the MOS shift register operation. The time interval between start pulses is equal to the signal , -phase clock pulses φ1, φ2 are needed to drive the shift register . These start and clock pulses are , ) st The amplitude of start pulse φst is the same as the φ1 and φ2 pulses. The shift register


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PDF S5930/S5931 B1201, KMPD1018E05
1998 - hd66002

Abstract: HD61830B 200dot Hitachi DSA00164 Nippon capacitors
Text: -bit bi-directional shift register (also used as a latch circuit) S/P Selector FCS E TEST1 TEST2 Operating , display drive circuit. 80-bit bi-directional shift register (also used as a latch circuit) When FCS is low, this register functions as an 80-bit shift register . At this time, DIOL and DIOR are used as , Switches shift register operation (when FCS is low) and serial-latch operation (when FCS is high). 6 , pin is set low. 2. Operating mode: Shift register operation When serial data is input in order from


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PDF HD66002 80-Channel ADE-207-277 HD66002 HD61830B 200dot Hitachi DSA00164 Nippon capacitors
8051 mx philips

Abstract: 7mP1 11.059mHz crystal oscillator 80C51 family hardware
Text: port mode, as follows: SMO 0 0 SMI 0 1 Mode 0 1 Description shift register 8-bit UART ie the 9th data , elapse between "write to SBUF" and activation of SEND. SEND enables the output of the shift register to , , the RX Control unit writes the bits 11111110 to the receive shift register , and in the next dock phase , RECEIVE is active, the contents of the receive shift register are shifted to the left one position. The , initially loaded into the rightmost position arrives at the leftmost position in the shift register , it


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PDF 80C51 80C51 8051 mx philips 7mP1 11.059mHz crystal oscillator 80C51 family hardware
1981 - 6522 rockwell

Abstract: R6522
Text: . 20 Shift Register Operation . 20 2.12 Shift Register Input Modes . 21 2.12.1 Shift Register Disabled (000 , ) . 23 2.13 Shift Register Output Modes , ) . 19 TABLE 2-10 SHIFT REGISTER AND AUXILIARY CONTROL REGISTER CONTROL ($0A) . 21


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PDF W65C22 W65C22N W65C22S) 6522 rockwell R6522
1981 - W65C22S

Abstract: W65C22S Versatile Interface Adapter (VIA) w65c22s core rockwell 6522 65C22 R6522 mos 6522 r65nc22 6522 rockwell 6522 mos
Text: . . 20 2.11 Shift Register Operation . 20 2.12 Shift Register Input Modes. . 21 2.12.1 Shift Register Disabled (000 , ) . 23 2.13 Shift Register Output Modes , ) . 19 TABLE 2-10 SHIFT REGISTER AND AUXILIARY CONTROL REGISTER CONTROL ($0A) . 21


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PDF W65C22S W65C22S W65C22S Versatile Interface Adapter (VIA) w65c22s core rockwell 6522 65C22 R6522 mos 6522 r65nc22 6522 rockwell 6522 mos
1999 - 80C51

Abstract: transistor s6p
Text: the data byte is at the output position of the shift register , then the 1 that was initially loaded , " signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX , the receive shift register , and in the next clock phase activates RECEIVE. RECEIVE enable SHIFT , receive shift register are shifted to the left one position. The value that comes in from the right is , output of the shift register to the alternate output function line of P3.0 and also enable SHIFT CLOCK


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PDF 80C51 80C51 SU00559 SU00560 transistor s6p
2014 - Not Available

Abstract: No abstract text available
Text: circuit st 2 Digital shift register (MOS shift register ) Address switch Active photodiode , for operating the MOS shift register . The video data rate is equal to the clock pulse frequency since , MOS shift register operation. The time interval between start pulses is equal to the signal , start pulse φst and 2-phase clock pulses φ1, φ2 are needed to drive the shift register . These start , †1 and φ2 pulses. The shift register starts the scanning at the “High” level of φst, so the start


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PDF S3922/S3923 KMPD1037E03
2014 - Not Available

Abstract: No abstract text available
Text: circuit st 2 Digital shift register (MOS shift register ) End of scan Source follower circuit , †2 Input (CMOS logic compatible) φst Description Pulses for operating the MOS shift register . The , synchronously with the rise of φ2 pulse. Pulse for starting the MOS shift register operation. The time , †2 are needed to drive the shift register . These start and clock pulses are positive going pulses and , the same as the φ1 and φ2 pulses. The shift register starts the scanning at the “High” level


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PDF S3921/S3924 KMPD1044E03
1981 - W65C22

Abstract: R65NC22
Text: . 20Â 2.11Â Shift Register Operation . 20Â 2.12Â Shift Register Input Modes . 21Â 2.12.1Â Shift Register Disabled (000 , ) . 23Â 2.13Â Shift Register Output Modes , ) . 19Â TABLE 2-10 SHIFT REGISTER AND AUXILIARY CONTROL REGISTER CONTROL ($0A) . 21Â


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PDF W65C22 W65C22N W65C22S) W65C22 R65NC22
1981 - 65C22

Abstract: R6522 6522 rockwell rockwell 6522 rockwell 6522 VIA
Text: . . 20 Shift Register Operation . 20 2.12 Shift Register Input Modes. . 21 2.12.1 Shift Register Disabled (000 , ) . 23 2.13 Shift Register Output Modes , ) . 19 TABLE 2-10 SHIFT REGISTER AND AUXILIARY CONTROL REGISTER CONTROL ($0A) . 21


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PDF W65C22S 65C22 R6522 6522 rockwell rockwell 6522 rockwell 6522 VIA
1998 - FET pair n-channel p-channel

Abstract: crystal 11.059MHZ datasheet of tcon register of 8051 TI 8048 CPU ET10 transistor depletion mode fet 8048 microcontroller APPLICATION HD7417P interfacing 8051 with eprom and ram P-Channel Depletion Mode Field Effect Transistor
Text: the data byte is at the output position of the shift register , then the 1 that was initially loaded , " signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX , the receive shift register , and in the next clock phase activates RECEIVE. RECEIVE enable SHIFT , receive shift register are shifted to the left one position. The value that comes in from the right is , output of the shift register to the alternate output function line of P3.0 and also enable SHIFT CLOCK


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PDF 80C51 80C51 SU00559 SU00560 FET pair n-channel p-channel crystal 11.059MHZ datasheet of tcon register of 8051 TI 8048 CPU ET10 transistor depletion mode fet 8048 microcontroller APPLICATION HD7417P interfacing 8051 with eprom and ram P-Channel Depletion Mode Field Effect Transistor
Not Available

Abstract: No abstract text available
Text: port mode, as foilows: SMO 0 0 1 SMI 0 1 0 Mode 0 1 2 Description shift register 8 , the 9th bit position of the transmit shift register and tells the TX Control block to commence a , activation of SEND. SEND enables the output of the shift register to the alternate output function line of P3 , in which SEND is active, the contents of the transmit shift register are shifted to the right one , is at the output position of the shift register , then the 1 that was initially loaded into the 9th


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PDF 16-bit 8751H Am9761H 80C51 80C31 8051AH LS001422
2014 - Not Available

Abstract: No abstract text available
Text: – Active area structure Degital shift register (MOS shift register ) End of scan 2.5 mm Start , - Description Pulses for operating the MOS shift register . The video data rate is equal to the , †2 pulse. Pulse for starting the MOS shift register operation. The time interval between start pulses is , and 2-phase clock pulses φ1, φ2 are needed to drive the shift register . These start and clock , of start pulse φst is the same as the φ1 and φ2 pulses. The shift register starts the scanning at


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PDF S3901/S3904 S3901 S3904 KMPD1036E04
2005 - S3923-256Q

Abstract: No abstract text available
Text: REGISTER (MOS SHIFT REGISTER ) END OF SCAN SOURCE FOLLOWER CIRCUIT Vdd ACTIVE VIDEO l Built-in , operating the MOS shift register . The video data rate is equal to the clock pulse frequency since the video , 2-phase clock pulses 1, 2 are needed to drive the shift register . These start and clock pulses are , shift register starts the scanning at the "High" level of st, so the start pulse interval is equal to , for 200 ns. To operate the shift register correctly, 2 must change from the "High" level to the "Low"


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PDF S3922/S3923 SE-171 KMPD1037E01 S3923-256Q
2010 - S3903

Abstract: S3903-512Q S3903-256Q S3903-1024Q S3902-512Q S3902-256Q S3902-128Q S3902 silicon photodiode array high frequency linear cmos IMAGE SENSOR
Text: 1 Clock 2 Degital shift register (MOS shift register ) Active photodiode End of scan , - Description Pulses for operating the MOS shift register . The video data rate is equal to the , . Pulse for starting the MOS shift register operation. The time interval between start pulses is equal to , , 2 are needed to drive the shift register . These start and clock pulses are positive going pulses , pulses. The shift register starts the scanning at the "High" level of st, so the start pulse interval


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PDF S3902/S3903 S3902 S3903 SE-171 KMPD1043E02 S3903-512Q S3903-256Q S3903-1024Q S3902-512Q S3902-256Q S3902-128Q silicon photodiode array high frequency linear cmos IMAGE SENSOR
2005 - Not Available

Abstract: No abstract text available
Text: Figure 2 Active area structure DEGITAL SHIFT REGISTER (MOS SHIFT REGISTER ) END OF SCAN 0.5 mm , operating the MOS shift register . The video data rate is equal to the clock pulse frequency since the video , needed to drive the shift register . These start and clock pulses are positive going pulses and CMOS , the same as the φ1 and φ2 pulses. The shift register starts the scanning at the “High” level , shift register correctly, φ2 must change from the “High” level to the “Low” level only once


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PDF S3902/S3903 S3902 S3903 SE-171 KMPD1043E01
2008 - C8225

Abstract: No abstract text available
Text: Figure 1 Equivalent circuit Start Clock Clock st 1 2 Degital shift register (MOS shift register ) End of , Pulses for operating the MOS shift register . The video data rate is equal to the clock pulse frequency , MOS shift register operation. The time interval between start pulses is equal to the signal , . A start pulse st and 2-phase clock pulses 1, 2 are needed to drive the shift register . These start , of start pulse st is the same as the 1 and 2 pulses. The shift register starts the scanning at the


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PDF S3901/S3904 S3901 S3904 SE-171 KMPD1036E02 C8225
2010 - silicon photodiode array

Abstract: high frequency linear cmos IMAGE SENSOR S3904-512Q S3904-256Q S3904-1024Q S3904 S3901-512Q S3901-256Q S3901-128Q S3901
Text: Active area structure Degital shift register (MOS shift register ) End of scan 2.5 mm Start , ) End of scan NC - Description Pulses for operating the MOS shift register . The video data rate , the rise of 2 pulse. Pulse for starting the MOS shift register operation. The time interval between , 1, 2 are needed to drive the shift register . These start and clock pulses are positive going pulses , 2 pulses. The shift register starts the scanning at the "High" level of st, so the start pulse


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PDF S3901/S3904 S3901 S3904 SE-171 KMPD1036E03 silicon photodiode array high frequency linear cmos IMAGE SENSOR S3904-512Q S3904-256Q S3904-1024Q S3901-512Q S3901-256Q S3901-128Q
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