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Part Manufacturer Description Datasheet Download Buy Part
LTC6905CS5#TRM Linear Technology LTC6905 - 17MHz to 170MHz Resistor Set SOT-23 Oscillator; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C
LTC6905HS5#TRM Linear Technology LTC6905 - 17MHz to 170MHz Resistor Set SOT-23 Oscillator; Package: SOT; Pins: 5; Temperature Range: -40°C to 125°C
LTC6906HS6#TR Linear Technology LTC6906 - Micropower, 10kHz to 1MHz Resistor Set Oscillator in SOT-23; Package: SOT; Pins: 6; Temperature Range: -40°C to 125°C
LTC1799CS5#TRMPBF Linear Technology LTC1799 - 1kHz to 33MHz Resistor Set SOT-23 Oscillator; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C
LTC6907CS6#TRMPBF Linear Technology LTC6907 - Micropower, 40kHz to 4MHz Resistor Set Oscillator in SOT-23; Package: SOT; Pins: 6; Temperature Range: 0°C to 70°C
LTC1799CS5#PBF Linear Technology LTC1799 - 1kHz to 33MHz Resistor Set SOT-23 Oscillator; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C

mxic dsp instruction set Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
768KHZ

Abstract: MX93011 MX93011A X321 mxic dsp instruction set
Text: 'interrupt Operations' 21 MXIC MX93Û11A 7.0 INSTRUCTION SET SUMMARY ABBREVIATIONS a AR pointer ar AR , immediate with high acc 2,2 1000 0110 Oxxx xxxx 24 MXIC MX93Û11A 8.0 INSTRUCTION SET DESCRIPTION abs , REGISTERS SUMMARY 6.0 REGISTERS DESCRIPTION 7.0 INSTRUCTION SET SUMMARY 8.0 INSTRUCTION SET DESCRIPTION , INFORMATION 1 ■vpgc MX93011A 1.0 FEATURES • 16-bit, 46.5ns instruction cycle, up to 21 MIPS DSP , be directly written by one - DSP instruction . Default inactive (5V output).- -HOLD\-IS-67-Hold DSP


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PDF MX9301 MX93011 MX93011A 16-bit, ap93011A MX93Q11A 100-PIN 768KHZ MX93011A X321 mxic dsp instruction set
mxic dsp instruction set

Abstract: No abstract text available
Text: , this pin can be directly written by one DSP instruction . Default inactive (5V output). UPMODX , register 7 (bit 6) will be set . W hen DSP reads CMDR, CRDY bit w ill be reset. PA C KB \ signal is d e fa u ltly set to high. W hen DSP w rites to CM DR, PAC KB\ is reset(active low). The host read w ill set , is set or hardw are H O LD\ signal is activated, DSP o p eratio n s and C odec c lo ck w ill be , operation . Interrupt can't affect HOLDV 2. W hen PWDN is set , DSP will run at 32.768 kHz and hi-crystal o


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PDF 16-bit, 16x16 32-bit 16-bit 16-level IN/IX96037 100-PIN MX96037 mxic dsp instruction set
2007 - MX25L1605

Abstract: MX25L1605M MX25L6405 MX25L1605MC PM1168 C214P IN3064 MX25L3205
Text: change the device content, should be set every time after the WREN instruction setting the WEL bit. The , internal write enable latch is set , the device can accept program/erase/write status register instruction , /erase instruction without hardware protection mode being set . To write the Block Protect (BP2, BP1, BP0 , ) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed) Program/erase , WRSR instruction , the Write Enable (WREN) instruction must be decoded and executed to set the Write


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PDF MX25L1605 16M-BIT 100mA MX25L1605 MX25L1605M MX25L6405 MX25L1605MC PM1168 C214P IN3064 MX25L3205
2006 - MX25L1605ZM

Abstract: 25l1605 8x6mm MX25L1605 IN3064 256-Byte
Text: Enable (WREN) instruction must set to Write Enable Latch (WEL) bit before writing other instructions to , modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL , instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC , set to 0, the CE instruction can be executed) Program/erase error bit. When the program/erase bit , Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance


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PDF MX25L1605ZM 16M-BIT 100mA PM1291 MX25L1605ZM 25l1605 8x6mm MX25L1605 IN3064 256-Byte
2006 - Not Available

Abstract: No abstract text available
Text: change the device content, should be set every time after the WREN instruction setting the WEL bit. The , internal write enable latch is set , the device can accept program/erase/write status register instruction , /erase instruction without hardware protection mode being set . To write the Block Protect (BP2, BP1, BP0 , ) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed) Program/erase , WRSR instruction , the Write Enable (WREN) instruction must be decoded and executed to set the Write


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PDF MX25L1605 16M-BIT 100mA fi6/2006 JUN/08/2006
2006 - MXIC sequential

Abstract: No abstract text available
Text: change the device content, should be set every time after the WREN instruction setting the WEL bit. The , internal write enable latch is set , the device can accept program/erase/write status register instruction , /erase instruction without hardware protection mode being set . To write the Block Protect (BP2, BP1, BP0 , ) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed) Program/erase , WRSR instruction , the Write Enable (WREN) instruction must be decoded and executed to set the Write


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PDF MX25L3205 32M-BIT 100mA JUN/12/2006 MXIC sequential
2006 - MXIC serial Flash

Abstract: No abstract text available
Text: , which are intended to change the device content, should be set every time after the WREN instruction , device to against the program/erase instruction without hardware protection mode being set . To write the , Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be , ) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR , high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP2, BP1, BP0. The


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PDF MX25L3205A 32M-BIT 100mA 50MHz 256-byte 64K-byte 64s/chip MXIC serial Flash
2006 - BP200

Abstract: MXIC serial Flash MX25L1605 ad20bit4 25L1605
Text: , which are intended to change the device content, should be set every time after the WREN instruction , device to against the program/erase instruction without hardware protection mode being set . To write the , Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be , ) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR , high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP2, BP1, BP0. The


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PDF MX25L1605 16M-BIT BP200 MXIC serial Flash MX25L1605 ad20bit4 25L1605
2006 - flash TYPE mx25l3205A

Abstract: No abstract text available
Text: latch is set , the device can accept program/erase/write status register instruction . When WEL bit sets , instruction without hardware protection mode being set . To write the Block Protect (BP2, BP1, BP0) bits , if all Block Protect bits set to 0, the CE instruction can be executed) Program/erase error bit , , the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL , instruction may set the WEL bit and can change the values of SRWD, BP2, BP1, BP0. The protected area, which


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PDF MX25L3205A 32M-BIT 100mA f/2005 JUN/08/2006 flash TYPE mx25l3205A
2006 - 25L3205

Abstract: MX25L3205 MX25L1605
Text: , which are intended to change the device content, should be set every time after the WREN instruction , device to against the program/erase instruction without hardware protection mode being set . To write the , Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be , ) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR , high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP2, BP1, BP0. The


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PDF MX25L3205 32M-BIT 25L3205 MX25L3205 MX25L1605
2002 - MXIC flash disk controller

Abstract: macronix mxic dsp MX93011 HD11 MX51L9692 MXIC sequential
Text: MXIC 's sequential type Mask ROM - Capacity of 64Mbit/128Mbit/256Mbit/512Mbit and higher density. - , well as 16 bit transfer on both host bus and DSP /Flash bus. Host Interface: · AT attachment , control for Host reset signal. DSP core: · High performance MX93011 DSP core. · 2KW Internal Direct , compatible P/N:PM0935 REV. 1.0, JUN. 18, 2002 1 MX51L9692 2. General Description The MXIC , execute Read, Write, and Erase operation for serial type, linear type Flash memory and MXIC 's serial


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PDF MX51L9692 256Mbit 64Mbit/128Mbit/256Mbit/512Mbit PM0935 MXIC flash disk controller macronix mxic dsp MX93011 HD11 MX51L9692 MXIC sequential
2006 - 25L6405

Abstract: MX25L6405
Text: intended to change the device content, should be set every time after the WREN instruction setting the WEL , latch is set , the device can accept program/erase/write status register instruction . When WEL bit sets , /erase instruction without hardware protection mode being set . To write the Block Protect (BP3, BP2, BP1 , ) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed) Program/erase error , Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance


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PDF MX25L6405 64M-BIT 25L6405 MX25L6405
2005 - pm1168

Abstract: MX25L1605 MX25L1605M
Text: clock pulse number to be multiple of eight base. · Write Enable (WREN) instruction must set to Write , change the device content, should be set every time after the WREN instruction setting the WEL bit. The , latch is set , the device can accept program/erase/write status register instruction . When WEL bit sets , instruction without hardware protection mode being set . To write the Block Protect (BP2, BP1, BP0) bits , if all Block Protect bits set to 0, the CE instruction can be executed) Program/erase error bit


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PDF MX25L1605 16M-BIT Peripheral2005 PM1168 pm1168 MX25L1605 MX25L1605M
2005 - 25L6405

Abstract: MX25L6405
Text: ) instruction must set to Write Enable Latch (WEL) bit before writing other instructions to modify data. The WEL , Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit . This bit is returned to its , instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC , instruction can be executed) Program/erase error bit. When the program/erase bit set to 1, there is an error , . Before sending WRSR instruction , the Write Enable (WREN) instruction must be decoded and executed to set


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PDF MX25L6405 64M-BIT JUL/15/2005 AUG/03/2005 PM1107 25L6405 MX25L6405
2005 - Not Available

Abstract: No abstract text available
Text: to be multiple of eight base. • Write Enable (WREN) instruction must set to Write Enable Latch , ) instruction to set the Write Enable Latch (WEL) bit . This bit is returned to its reset state by the , content, should be set every time after the WREN instruction setting the WEL bit. The sequence of , internal write enable latch is set , the device can accept program/erase/write status register instruction , /erase instruction without hardware protection mode being set . To write the Block Protect (BP2, BP1, BP0


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PDF MX25L3205A 32M-BIT 100mA OCT/13/2005
2007 - MX25L3205A

Abstract: 3205a MX25L3205AMI-20 mx25l3205amc-20g MX25L3205 IN3064 flash TYPE mx25l3205A
Text: latch is set , the device can accept program/erase/write status register instruction . When WEL bit sets , instruction without hardware protection mode being set . To write the Block Protect (BP2, BP1, BP0) bits , if all Block Protect bits set to 0, the CE instruction can be executed) Program/erase error bit , , the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL , instruction may set the WEL bit and can change the values of SRWD, BP2, BP1, BP0. The protected area, which


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PDF MX25L3205A 32M-BIT 100mA MX25L3205A 3205a MX25L3205AMI-20 mx25l3205amc-20g MX25L3205 IN3064 flash TYPE mx25l3205A
2005 - 25L3205

Abstract: MX25L3205 MX25L6405 8096 instruction set ad8b IN3064 MX25L3205MC-20 MX25L1605 MX25L3205MI-20
Text: Enable (WREN) instruction must set to Write Enable Latch (WEL) bit before writing other instructions to , modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL , , which are intended to change the device content, should be set every time after the WREN instruction , instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC , set to 0, the CE instruction can be executed) Program/erase error bit. When the program/erase bit


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PDF MX25L3205 32M-BIT 100mA JUL/15/2005 25L3205 MX25L3205 MX25L6405 8096 instruction set ad8b IN3064 MX25L3205MC-20 MX25L1605 MX25L3205MI-20
2005 - Not Available

Abstract: No abstract text available
Text: clock pulse number to be multiple of eight base. · Write Enable (WREN) instruction must set to Write , device to against the program/erase instruction without hardware protection mode being set . To write the , Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be , ) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR , Protection of the Status Register Status Register is Writable (if the WREN instruction has set the WEL bit


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PDF MX25L3205A 32M-BIT 100mA 50MHz 256-byte 64K-byte 64s/chip PM1243
2006 - Not Available

Abstract: No abstract text available
Text: base. • Write Enable (WREN) instruction must set to Write Enable Latch (WEL) bit before writing , €¢ All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the , content, should be set every time after the WREN instruction setting the WEL bit. The sequence of , internal write enable latch is set , the device can accept program/erase/write status register instruction , /erase instruction without hardware protection mode being set . To write the Block Protect (BP2, BP1, BP0


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PDF MX25L1605 16M-BIT 100mA MAY/16/2006
2007 - MX25L6405

Abstract: 25L6405 MX25L1605 MX25L6405MC MX25L64 MX25L* 86 MHz IN3064
Text: all Block Protect bits set to 0, the CE instruction can be executed) Program/erase error bit. When , executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of , (SPM): - When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and , instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which , to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit


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PDF MX25L6405 64M-BIT 100mA MX25L6405 25L6405 MX25L1605 MX25L6405MC MX25L64 MX25L* 86 MHz IN3064
2005 - MX25L1605

Abstract: No abstract text available
Text: to be multiple of eight base. • Write Enable (WREN) instruction must set to Write Enable Latch , that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch , intended to change the device content, should be set every time after the WREN instruction setting the WEL , internal write enable latch is set , the device can accept program/erase/write status register instruction , the program/erase instruction without hardware protection mode being set . To write the Block Protect


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PDF MX25L1605, MX25L3205, MX25L6405 16M/32M/64M-BIT MX25L6405) MX25L3205) MX25L1605) MX25L1605
2006 - Not Available

Abstract: No abstract text available
Text: all Block Protect bits set to 0, the CE instruction can be executed) Program/erase error bit. When , executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of , (SPM): - When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and , instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which , to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit


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PDF MX25L6405 64M-BIT 100mA JUL/15/2005 AUG/03/2005 JUN/08/2006
Not Available

Abstract: No abstract text available
Text: /transmit gain control machine) related product application . Easy interface to general purpose DSP . , power on reset function for DSP and MCU .Easy interface to FAX or Cordless phone use . Automatic , document contains information on a product under development at MXIC . The information is intended to help you to evaluate this product. MXIC reserves the right to change or discontinue work on this proposed product without notice. Ver. 0.20, August 10, 1998 SbôflflflE 0D03515 7Sfl MXIC MX93000C


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PDF X93000C 16-bit 536MHz CA95131 G003S43
2005 - KH25L3205

Abstract: KH25L3205D EN25Q32 EN25 SOP 8 200MIL EN25Q32A mxic KH25L VDFN
Text: . Instruction Set Comparison 4.2.1 Different Block Protection Area EN25Q32A KH25L3205D This Application , Eon Silicon Solution Inc. Application Note EON EN25Q32A vs MXIC KH25L3205D , introduces how to implement a system design from MXIC KH25L3205D Flash to Eon EN25Q32A Flash. 2. GENERAL , . 2. For the general standard / dual SPI mode, Eon EN25Q32A Flash is the same as MXIC KH25L3205D Flash if customer don't use the accelerated (ACC) pin and HOLD# pin functions. 3. MXIC KH25L3205D don't


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PDF EN25Q32A KH25L3205D KH25L3205D EN25Q32A 200mil 100ns KH25L3205 EN25Q32 EN25 SOP 8 200MIL mxic KH25L VDFN
2005 - MX25L1635D

Abstract: mxic EN25Q16 208-MIL VDFN
Text: www.eonssi.com Eon Silicon Solution Inc. 4.2. Instruction Set Comparison EN25Q16 Byte 1 Code Instruction Name Write Disable / Exit OTP mode Sector Erase / OTP erase 20h , system design from MXIC MX25L1635D Flash to Eon EN25Q16 Flash. 2. GENERAL FUNCTION COMPARISON TABLE , and VDFN (5x6mm) package, Eon EN25Q16 Flash is the same as MXIC MX25L1635D Flash. This Application , Disable function. 2. For 20h command, MX25L1635D only supports Sector Erase function. 3. MXIC MX25L1635D


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PDF EN25Q16 MX25L1635D MX25L1635D EN25Q16 mxic 208-MIL VDFN
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