The Datasheet Archive

mt90840 datasheet (12)

Part ECAD Model Manufacturer Description Type PDF
MT90840 MT90840 ECAD Model Mitel Semiconductor Distributed Hyperchannel Switch Original PDF
MT90840 MT90840 ECAD Model Zarlink Semiconductor 512 x 2430 Channel Multiple Rate TDM ( 2, 4, 8Mb-s) to Parallel port Distributed Hyperchannel Switch (DHS) for STS-1 and STS-3 applications Original PDF
MT90840AK MT90840AK ECAD Model Mitel Semiconductor Distributed Hyperchannel Switch Original PDF
MT90840AL MT90840AL ECAD Model Zarlink Semiconductor 512 x 2430 Channel Multiple Rate TDM ( 2, 4, 8 Mbps) to Parallel Port Distributed Hyperchannel Switch (DHS) for STS-1 and STS-3 Applications Original PDF
MT90840AL MT90840AL ECAD Model Zarlink Semiconductor Switch Fabric 5V Supply Voltage, 100-PQFP Original PDF
MT90840AL MT90840AL ECAD Model Mitel Semiconductor Distributed Hyperchannel Switch Scan PDF
MT90840AL1 MT90840AL1 ECAD Model Zarlink Semiconductor Interface - Telecom, Integrated Circuits (ICs), IC DGTL SWITCH DHS 100MQFP Original PDF
MT90840AP MT90840AP ECAD Model Mitel Semiconductor Distributed Hyperchannel Switch Original PDF
MT90840AP MT90840AP ECAD Model Zarlink Semiconductor Switch Fabric 5V Supply Voltage, 84-PLCC Original PDF
MT90840AP MT90840AP ECAD Model Mitel Semiconductor Distributed Hyperchannel Switch Scan PDF
MT90840AP1 MT90840AP1 ECAD Model Zarlink Semiconductor Interface - Telecom, Integrated Circuits (ICs), IC DGTL SWITCH DHS 84PLCC Original PDF
MT90840APR1 MT90840APR1 ECAD Model Zarlink Semiconductor Interface - Telecom, Integrated Circuits (ICs), IC DGTL SWITCH DHS 84PLCC Original PDF

mt90840 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1999 - IC TO STORE AND PLAY VIDEO WITH DELAY

Abstract: No abstract text available
Text: references provided by the MVIP bus. In a ring master station, the MT90840's internal elastic store on the , backbone. This feature is available due to the MT90840's device capabilities to access each 64 kb/s channel , control other transmit devices residing in the same board and sharing the parallel bus with the MT90840. , -161 During the time that other devices are driving the parallel bus, the MT90840's parallel output port can , ® Application Note MSAN-161 Application Hints for the MT90840 ISSUE 1 September 1995


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PDF MSAN-161 MT90840 MT90840 IC TO STORE AND PLAY VIDEO WITH DELAY
1996 - AN303

Abstract: MSAN-161 MT90840 S3011
Text: ring master station, the MT90840's internal elastic store on the parallel data input port is , devices to share a portion of the 155 Mb/s TDM backbone. This feature is available due to the MT90840's , and sharing the parallel bus with the MT90840. The transmit enable signal can be generated over any , -161 Application Note During the time that other devices are driving the parallel bus, the MT90840's parallel , Application Note ® MSAN-161 Application Hints for the MT90840 ISSUE 1 September


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PDF MSAN-161 MT90840 AN303 MSAN-161 MT90840 S3011
2001 - TMS 3450

Abstract: 001H 101H MT90840 MT90840AL MT90840AP
Text: March 1997 Ordering Information MT90840AL 100 Pin PQFP MT90840AP 84 Pin PLCC -40 to 85 C C , low, or if the INTCLK bit is set high, this input is ignored by the MT90840. 84 100 3 In , , or if the INTCLK bit is set high, this input is ignored by the MT90840. (See pin description for C4 , high PPFT becomes an input, and is used to receive the frame reference from another MT90840. Used in , the MT90840. These pins function as eight input address lines to the Address Latch circuit as well as


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PDF MT90840 2430-Byte TMS 3450 001H 101H MT90840 MT90840AL MT90840AP
2001 - psd100

Abstract: 001H 101H MT90840 MT90840AL MT90840AP
Text: /o F0i/o VDD · July 2002 Ordering Information MT90840AL 100 Pin PQFP MT90840AP 84 Pin , input is ignored by the MT90840. 84 100 3 Chip Select (Input). Active low input enabling a , by the MT90840. (See pin description for C4/8R1.) 28-31 70-73 CTo3CTo0 External Control , reference from another MT90840. Used in all timing modes except TM3. 45-52 92-99 PDi7 , for control and monitoring of the MT90840. These pins function as eight input address lines to the


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PDF MT90840 2430-Byte psd100 001H 101H MT90840 MT90840AL MT90840AP
Not Available

Abstract: No abstract text available
Text: ) and a Parallel Data Port (PDP) June 1995 Ordering Information MT90840AK 100PinPQ FP MT90840AP , @ MT90840 M IT E L Distributed Hyperchannel Switch Advance Information H Features , – 2-189 MT90840 Advance Information Functional Description Real time multimedia applications , sequence integrity and provide constant delay through the switch. The MT90840 device bridges existing , MT90840 functional block diagram. Today, transmission links operating at SONET rates utilize


OCR Scan
PDF MT90840 MT90840AK 100PinPQ MT90840AP MT8972B, MT8930/1, MT8910
2002 - PSD10-2

Abstract: 1AB00
Text: Ordering Information MT90840AL 100 Pin PQFP MT90840AP 84 Pin PLCC MT90840AL1 100 Pin PQFP* *Pb Free Matte , the MT90840 driving F0 to control the timing of one or more other MT90840s. If the internal 4.096 MHz , the INTCLK bit is set high, this input is ignored by the MT90840. In Timing Mode 1 (TM1), or at 8.192 , by the MT90840. (See pin description for C4/8R1.) External Control Lines 3 to 0 (Output). Output , another MT90840. Used in all timing modes except TM3. Parallel Data Input Port 7 to 0 (Input). These eight


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PDF MT90840 PSD10-2 1AB00
1999 - Not Available

Abstract: No abstract text available
Text: 1997 Ordering Information MT90840AL 100 Pin PQFP MT90840AP 84 Pin PLCC -40°C to 85°C DTA · , low, or if the INTCLK bit is set high, this input is ignored by the MT90840. 84 100 3 In , , or if the INTCLK bit is set high, this input is ignored by the MT90840. (See pin description for C4 , high PPFT becomes an input, and is used to receive the frame reference from another MT90840. Used in , the MT90840. These pins function as eight input address lines to the Address Latch circuit as well as


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PDF MT90840 2430-Byte
PSD100

Abstract: MT90840 MT90840AL MT90840AP PD06E 8.192 Mc AB5A dta 101 22.53
Text: 1997 Ordering Information MT90840AL 100PinPQFP MT90840AP 84 Pin PLCC -40°C to 85°C • Diagnostic , if the INTCLK bit is set high, this input is ignored by the MT90840. In Timing Mode 1 (TM1), or at , C4/8R bit is set high, or if the INTCLK bit is set high, this input is ignored by the MT90840. (See , , and is used to receive the frame reference from another MT90840. Used in all timing modes except TM3 , for control and monitoring of the MT90840. These pins function as eight input address lines to the


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PDF MT90840 PSD100 MT90840 MT90840AL MT90840AP PD06E 8.192 Mc AB5A dta 101 22.53
1996 - HA711

Abstract: PPS-10 ST-M12 6AB4 100-Pin PQFP Package motorola plcc HA10 MT90840AP MT90840AL MT90840 HA11
Text: TM1, the MT90840's SPCKo clock output is not used. For applications where multiple MT90840 share the , required so that the 8.192 MHz output of the PLL is connected to the MT90840's C4/8R1 & 2 MT90840 1 Rx , Output Driver PDo7 8 Ordering Information MT90840AL 100 Pin PQFP MT90840AP 84 Pin PLCC , MT90840. For more details on the utilization of this signal, see Timing Modes 1 and 2 description. In , outputs. If either C4/8R and INTCLK bits are set HIGH, this input is ignored by the MT90840. In TM3 and


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PDF MT90840 HA711 PPS-10 ST-M12 6AB4 100-Pin PQFP Package motorola plcc HA10 MT90840AP MT90840AL MT90840 HA11
2001 - S3011

Abstract: AN303 MSAN-161 MT90840 TXBC
Text: ring master station, the MT90840's internal elastic store on the parallel data input port is , devices to share a portion of the 155 Mb/s TDM backbone. This feature is available due to the MT90840's , and sharing the parallel bus with the MT90840. The transmit enable signal can be generated over any , -161 Application Note During the time that other devices are driving the parallel bus, the MT90840's parallel , Application Note MSAN-161 Application Hints for the MT90840 ISSUE 1 September 1995


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PDF MSAN-161 MT90840 S3011 AN303 MSAN-161 MT90840 TXBC
2002 - MT90840

Abstract: MT90840AL MT90840AP ha1056 AD5A
Text: Ordering Information MT90840AL1 MT90840AP1 MT90840APR1 · Programmable data rates on the parallel , , and this allows the MT90840 driving F0 to control the timing of one or more other MT90840s. If the , Change 1 Ordering Information Box Removed part numbers MT90840AL and MT90840AP from ordering , bit is set high, this input is ignored by the MT90840. In Timing Mode 1 (TM1), or at 8.192 MHz, the , by the MT90840. (See pin description for C4/8R1.) 28-31 70-73 CTo3CTo0 External Control


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PDF MT90840 MT90840AL1 MT90840AP1 MT90840APR1 MT90840 MT90840AL MT90840AP ha1056 AD5A
2001 - MT90840

Abstract: MT90840AL MT90840AP 001H 101H ha1076 dta 101 22.53
Text: March 1997 Ordering Information MT90840AL 100 Pin PQFP MT90840AP 84 Pin PLCC -40 to 85 C C , low, or if the INTCLK bit is set high, this input is ignored by the MT90840. 84 100 3 In , , or if the INTCLK bit is set high, this input is ignored by the MT90840. (See pin description for C4 , high PPFT becomes an input, and is used to receive the frame reference from another MT90840. Used in , the MT90840. These pins function as eight input address lines to the Address Latch circuit as well as


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PDF MT90840 2430-Byte MT90840 MT90840AL MT90840AP 001H 101H ha1076 dta 101 22.53
Not Available

Abstract: No abstract text available
Text: MT90840's parallel port frame pulse input (PPFRi) and output (PPFRo) signals synchronize the MT90840 , is connected to the MT90840†™s C4/8R1 & 2 inputs. The MT90840 then utilizes the C4/8R1 input , PDoO Output Driver PDo7 • . Ordering Information MT90840AL 100PinPQFP MT90840AP 84 Pin , C4/8R bit is set LOW or if INTCLK bit is set HIGH, this input is ignored by the MT90840. For more , outputs. If either C4/8R and INTCLK bits are set HIGH, this input is ignored by the MT90840. In TM3 and


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PDF MT90840 125ns b24T370
2002 - Not Available

Abstract: No abstract text available
Text: Ordering Information MT90840AL 100 Pin MQFP MT90840AP 84 Pin PLCC MT90840AL1 100 Pin MQFP* MT90840AP1 84 , the MT90840 driving F0 to control the timing of one or more other MT90840s. If the internal 4.096 MHz , the INTCLK bit is set high, this input is ignored by the MT90840. In Timing Mode 1 (TM1), or at 8.192 , by the MT90840. (See pin description for C4/8R1.) External Control Lines 3 to 0 (Output). Output , another MT90840. Used in all timing modes except TM3. Parallel Data Input Port 7 to 0 (Input). These eight


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PDF MT90840
1995 - MT8910

Abstract: MT8972B MT90840 MT90840AK MT90840AP MUX2-b 8029 multiplexer
Text: MT90840 ® Distributed Hyperchannel Switch Advance Information Features ISSUE 1 June , Parallel switching mode for up to 2430 channels non-blocking Ordering Information MT90840AK 100 Pin PQFP MT90840AP 84 Pin PLCC -40°C to 85°C · Bridging ST-BUS/MVIP buses to high speed Time , MT90840 Functional Description Real time multimedia applications require the transmission of mixed , delay through the switch. The MT90840 device bridges existing Mitel ST-BUS components into a new


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PDF MT90840 44Mbyte/s T90840 MT8910 MT8972B MT90840 MT90840AK MT90840AP MUX2-b 8029 multiplexer
1999 - Not Available

Abstract: No abstract text available
Text: 1997 Ordering Information MT90840AL 100 Pin PQFP MT90840AP 84 Pin PLCC -40°C to 85°C DTA · , low, or if the INTCLK bit is set high, this input is ignored by the MT90840. 84 100 3 In , , or if the INTCLK bit is set high, this input is ignored by the MT90840. (See pin description for C4 , high PPFT becomes an input, and is used to receive the frame reference from another MT90840. Used in , the MT90840. These pins function as eight input address lines to the Address Latch circuit as well as


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PDF MT90840 2430-Byte
2001 - AN303

Abstract: dsp bus clock interface asynchronous MSAN-161 MT90840 S3011
Text: ring master station, the MT90840's internal elastic store on the parallel data input port is , devices to share a portion of the 155 Mb/s TDM backbone. This feature is available due to the MT90840's , and sharing the parallel bus with the MT90840. The transmit enable signal can be generated over any , -161 Application Note During the time that other devices are driving the parallel bus, the MT90840's parallel , Application Note MSAN-161 Application Hints for the MT90840 ISSUE 1 September 1995


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PDF MSAN-161 MT90840 AN303 dsp bus clock interface asynchronous MSAN-161 MT90840 S3011
2002 - Not Available

Abstract: No abstract text available
Text: Converters June 2007 Ordering Information MT90840AL1 MT90840AP1 MT90840APR1 100 Pin MQFP* 84 Pin PLCC* 84 , the MT90840 driving F0 to control the timing of one or more other MT90840s. If the internal 4.096 MHz , current issue. Page 1 Item Ordering Information Box Change Removed part numbers MT90840AL and MT90840AP , high, this input is ignored by the MT90840. In Timing Mode 1 (TM1), or at 8.192 MHz, the C4/8 input is , bit is set high, or if the INTCLK bit is set high, this input is ignored by the MT90840. (See pin


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PDF MT90840
001H

Abstract: 101H MT90840 MT90840AL MT90840AP tms 1944 an 22
Text: /o F0i/o VDD · July 2002 Ordering Information MT90840AL 100 Pin PQFP MT90840AP 84 Pin , input is ignored by the MT90840. 84 100 3 Chip Select (Input). Active low input enabling a , by the MT90840. (See pin description for C4/8R1.) 28-31 70-73 CTo3CTo0 External Control , reference from another MT90840. Used in all timing modes except TM3. 45-52 92-99 PDi7 , for control and monitoring of the MT90840. These pins function as eight input address lines to the


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PDF MT90840 2430-Byte 001H 101H MT90840 MT90840AL MT90840AP tms 1944 an 22
Not Available

Abstract: No abstract text available
Text: .; SCSI COMP. VOICE STORAGE PSTN, ISDN T1/E1 CTI SERVER MT90840 MT90840 DHS DHS 2048 , Inter-chassis MT90840 MT90840 STBUS STBUS ANALOG TRUNKS MT8977/9079 T1 & E1 I/f MT8910 & 8931 , Interface Inter-chassis Inter-chassis MT90840 MT90840 MT8910 & 8931 ISDN Framers T3 & E3 FRAMERS


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PDF MT90820 MT90820 MT8977/9079 MT90840 MT8910
DPRAM

Abstract: MT9075 pc parallel port relay board pstn
Text: ST-BUS T1/E1 SCSA MT90840 Parallel Access MT90840 Parallel SONET FRAMING & OPTICS


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PDF MT90210 MT90210 Inte0820 MT90820 MT9075/4 MT9079 DPRAM MT9075 pc parallel port relay board pstn
2004 - Not Available

Abstract: No abstract text available
Text: N/A N/A 32 3 32 3 · · · · · · · · · · MT90840 512 x 2430 8 8 · · · · ·


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PDF MT8920 MT9080 MT9085 MT90812 MT9080
2001 - digital access cross connect switch

Abstract: No abstract text available
Text: Inter-chassis MT90840 MT90840 Frame Relay T1,E1,T3,E3 ISDN POTS Early ATM WAN Figure 4 - Typical MT90820


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PDF MT90820 digital access cross connect switch
2010 - MT89L86

Abstract: ZL50022 ZL50021 ZL50019 ZL50018 ZL50015 ZL50011 ZL50010 MT90863 MT8986
Text: Access Circuit MT90840 512 X 2430 Channel Multiple Rate TDM (2, 4, 8 Mbps) to Parallel Port


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PDF ZL50011 10ZL059 MT89L86 ZL50022 ZL50021 ZL50019 ZL50018 ZL50015 ZL50011 ZL50010 MT90863 MT8986
2005 - "digital switch"

Abstract: ZL50018 ZL50011 ZL50010 MT90863 MT90810 MT89L86 MT8986 ZL50064 ZL50021
Text: ) to Parallel Bus Access Circuit (PAC) MT90840 512 X 2430 Channel Multiple Rate TDM (2, 4, 8 Mbps


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PDF ZL50018 "digital switch" ZL50018 ZL50011 ZL50010 MT90863 MT90810 MT89L86 MT8986 ZL50064 ZL50021
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