The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
J2014001L402 GE Critical Power GP100, 3&934;-480, RS485 communications, controller slot, LAN, RJ45 terminations, configured for slot 3
J2014001L422N GE Critical Power GP100, 3&934;-480, RS485 communications, controller slot, RJ45 terminations, includes a L401 and a L402 shelves in the same enclosure. Hardware included
C2A Visual Communications Company LMP Neon Wire Terminal 1.9mA
5AB-BT Visual Communications Company LMP T-2 Neon Wire Terminal
A1B Visual Communications Company LMP T-2 Neon Wire Terminal
A2B Visual Communications Company LMP T-2 Neon Wire Terminal

mdio termination Datasheets Context Search

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2004 - RGMII 3COM

Abstract: mdio termination r23b DP83865 SCHEMATIC rj45 stackup LM370 DP83865DVH R10B LM3704 duplex-led
Text: Design Sheet Block Diagram 1 1 of 3 5 4 Suggested termination on MAC side. Place resistors close to source. Actual values may differ for series termination resistors and depend on impedance of the MAC chip's output pins. MDC/ MDIO termination as suggested by IEEE spec. TX_EN TX_ER , CRS COL 2 1k5 MDIO MDC 1 R5 2 18 4 33 MDIO MDC 1 U2 1 2 3 4 5 R51 , the same trace length between PHY and MAC (including serial termination resistor). Tolerance +/- 0.5


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PDF DP83865DVH: LINK100 25MHz DP83865 RGMII 3COM mdio termination r23b DP83865 SCHEMATIC rj45 stackup LM370 DP83865DVH R10B LM3704 duplex-led
ip108

Abstract: transforme MDIO MDIO MDC IP1726 IP108 IP1726 SIGNAL PATH DESIGNER mdio termination
Text: the border Utilize the source termination scheme to improve the impendence match and the signal integrity. The termination resistor should be close to the signal output end. Ver. 1.5 -1- Jun.18, 2004 IP1726+IP108 PCB layout guide IP1726 TX signals Source termination R value=22-33 Signal trace Source termination R value=22-33 RX signals IP108 Figure 2.2 Ver. 1.5 Source termination scheme -2- Jun.18, 2004 IP1726+IP108 PCB layout guide 3. Ground


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PDF IP1726 IP108 100mil 100mil transforme MDIO MDIO MDC IP1726 IP108 SIGNAL PATH DESIGNER mdio termination
2001 - LXT971A

Abstract: MDIO MDC LXT970A-to-LXT971A LXT970 AN121 LXT970A LXT970AT
Text: does not require termination resistors on the MII outputs, regardless of whether or not the MDIO , ) Dual-mode control (external pin or MDIO bit) enabled repeater applications. Termination Resistors , 1.2.1.2 Transmit Termination Circuitry .6 1.2.1.3 Receive Termination Circuitry . 6 1.2.1.4 Transmit , . 8 2.3.2 MII Termination Circuitry


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PDF LXT971A LXT970A-to-LXT971A AN121. MDIO MDC LXT970A-to-LXT971A LXT970 AN121 LXT970A LXT970AT
ip108

Abstract: IP1726 IP108 ip101 4.7kohm resistor IP1726 MDIO MDC 33Ohm 34063 application note 34063 isolated 34063
Text: .5 2.1 2.2 SS-SMII termination , .5 MII termination , .7 3.1 PHY address setting and MDC/ MDIO , ] SS-SMII termination For impedance match and signal integrity, IP1726 (1718) and IP108 uses source termination scheme to reduce the signal reflection and EMI radiation. It is recommended to use TOP side of


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PDF IP1726 IP108 100Kohm IP1726 IP108 ip101 4.7kohm resistor IP1726 MDIO MDC 33Ohm 34063 application note 34063 isolated 34063
2002 - LXT971A

Abstract: lxt971a rxer LXT973 100BASE-FX
Text: . 8 2.1.2 Receive Termination Circuitry , .10 2.3.1 MII Termination Circuitry , .13 2.5.2 MDIO /Software Control Mode , Interface (MII) for MAC communications - Configurable via a Management Data Input/Output ( MDIO ) interface , Termination Circuitry The external 100 termination resistors required for the LXT971A have been integrated


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PDF LXT973 LXT971A-to-LXT973 LXT971A lxt971a rxer LXT973 100BASE-FX
2000 - "network interface cards"

Abstract: No abstract text available
Text: LXT970A Block Diagram TX_EN MII TX TX_ER TXD<0:4> TX_CLK MF<0:4> CFG<0:1> FDE TRSTE RESET FDS/MDINT MDIO , . 17 MII Management Interface ( MDIO ) . 18 Hardware Control Interface , Negotiation and Fast Link Pulse Timing .53 MDIO and MII Timing .54 , (Date Code) (Trace Code) (Part#) XXXX XXXX LXT970AQC/ATC XXXXXX (Lot#) RXD2 RXD3 RXD4 MDC MDIO , Analog. 3. If bit 17.3 = 0, 55 series termination resistors are recommended on all output signals to


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PDF LXT970A LXT970A LXT970 100BASE-TX, 10BASE-T, 100BASE-FX "network interface cards"
2005 - AA10

Abstract: AA13 P802 SCAN50C400A SCAN50C400AUT UFJ440A MDIO communication protocol AN1242 HT4 MARKING
Text: LVDS IO IEEE Draft P802.3ae D4.0 - MDIO management interface protocol compatible IEEE 1149.1 (JTAG) compliant test mode 1.35V for core, high-speed circuitry and MDIO 3.3V ± 5% for LVDS IO, Control and JTAG , _3 ± and T1_4 ± . On-chip 50 termination resistors connect from HT1+ and HT1- to VDDHS. HT2+ HT2 , serializer, channel 2. Data is sourced from T1_5 ± , T1_6 ± , T1_7 ± and T1_8 ± . On-chip 50 termination , , T2_2 ± , T2_3 ± and T2_4 ± . On-chip 50 termination resistors connect from HT3+ and HT3- to VDDHS


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PDF SCAN50C400A SCAN50C400A CSP-9-111C2) CSP-9-111S2) CSP-9-111S2. AA10 AA13 P802 SCAN50C400AUT UFJ440A MDIO communication protocol AN1242 HT4 MARKING
1999 - "network interface cards"

Abstract: No abstract text available
Text: 17.3 = 1, termination resistors are not required. 4. The LXT970A supports the 802.3 MDIO register set , TRSTE RESET FDS/MDINT MDIO MDDIS MDC XTALI/O RX_CLK RXD<0:4> MII RX 10Mbps Loopback + Parallel to , . 19 MII Management Interface ( MDIO , . 55 MDIO and MII Timing , XXXXXX (Lot#) RXD2 RXD3 RXD4 MDC MDIO GNDD LEDR LEDT LEDL LEDC LEDS VCCR N/C N/C PWRDWN CFG1


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PDF LXT970A LXT970A LXT970 100BASE-TX, 10BASE-T, 100BASE-FX DS-T970A-R1 "network interface cards"
2007 - AA10

Abstract: AA13 AB14 P802 SCAN50C400A SCAN50C400AUT UFJ440A AN-124 AN-1242 national
Text: Draft P802.3ae D4.0 - MDIO management interface protocol compatible IEEE 1149.1 (JTAG) compliant test mode 1.35V for core, high-speed circuitry and MDIO 3.3V ±5% for LVDS IO, Control and JTAG interface , 50 termination resistors connect from HT1+ and HT1- to VDDHS. HT2+ HT2- J22 J21 O, CML , sourced from T1_5±, T1_6±, T1_7± and T1_8±. On-chip 50 termination resistors connect from HT2+ and HT2 , 50 termination resistors connect from HT3+ and HT3- to VDDHS. HT4+ HT4- E22 E21 O, CML


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PDF SCAN50C400A SCAN50C400A AA10 AA13 AB14 P802 SCAN50C400AUT UFJ440A AN-124 AN-1242 national
2007 - ht4 marking

Abstract: No abstract text available
Text: IO IEEE Draft P802.3ae D4.0 - MDIO management interface protocol compatible IEEE 1149.1 (JTAG) compliant test mode 1.35V for core, high-speed circuitry and MDIO 3.3V ±5% for LVDS IO, Control and JTAG , _4±. On-chip 50 termination resistors connect from HT1+ and HT1- to VDDHS. Inverting and non-inverting , _7± and T1_8±. On-chip 50 termination resistors connect from HT2+ and HT2- to VDDHS. Inverting and , _2±, T2_3± and T2_4±. On-chip 50 termination resistors connect from HT3+ and HT3- to VDDHS. Inverting and


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PDF SCAN50C400A SCAN50C400A ht4 marking
1998 - LXT970AHC

Abstract: digital clock circuit 14053b HALO TG110 rj45 LXT970AQC valor st6118 HALO TG110-S050N2 E1 to fiber optic converter circuit LXT970A LXT970
Text: , termination resistors are not required. 3. The LXT970A supports the 802.3 MDIO register set. Specific bits in , traces. If bit 17.3 = 1, termination resistors are not required. 3. The LXT970A supports the 802.3 MDIO , TRSTE RESET FDS/MDINT MDIO MDDIS MDC XTALI/O RX_CLK CRS COL RX_DV RX_ER Scrambler & , . 18 MII Management Interface ( MDIO , . 55 MDIO and MII Timing


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PDF LXT970A LXT970A LXT970 100BASE-TX, 10BASE-T, 100BASE-FX 10BASE-T 100BASE-TX LXT970AHC digital clock circuit 14053b HALO TG110 rj45 LXT970AQC valor st6118 HALO TG110-S050N2 E1 to fiber optic converter circuit LXT970
2007 - AN-1242 national

Abstract: No abstract text available
Text: backplane TIA/EIA 644-A compatible LVDS IO IEEE Draft P802.3ae D4.0 - MDIO management interface protocol compatible IEEE 1149.1 (JTAG) compliant test mode 1.35V for core, high-speed circuitry and MDIO 3.3V ±5% for , _4±. On-chip 50 termination resistors connect from HT1+ and HT1- to VDDHS. Inverting and non-inverting , _7± and T1_8±. On-chip 50 termination resistors connect from HT2+ and HT2- to VDDHS. Inverting and , _2±, T2_3± and T2_4±. On-chip 50 termination resistors connect from HT3+ and HT3- to VDDHS. Inverting and


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PDF SCAN50C400 SCAN50C400A SNOSA22G AN-1242 national
2001 - bob smith termination

Abstract: atc 17-33 T3D 34 diode LXT970AQC Diode T3D 55 T3D 53 diode aui isolation transformer T2D 17 67 rsm 2814 T3D 43 diode
Text: .29 2.4.1.1 MDIO Control Mode .29 , .24 MDIO Interrupt Signaling , .60 MDIO Timing when Sourced by STA .61 MDIO Timing when Sourced by PHY , Timing Parameters. 60 MDIO Timing Parameters


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PDF LXT970A LXT970A LXT970 100BASE-TX, 10BASE-T, 100BASE-FX bob smith termination atc 17-33 T3D 34 diode LXT970AQC Diode T3D 55 T3D 53 diode aui isolation transformer T2D 17 67 rsm 2814 T3D 43 diode
2004 - AA10

Abstract: AA13 P802 SCAN50C400 UFJ440A SCAN50C400UT AN-124
Text: -A compatible LVDS IO IEEE Draft P802.3ae D4.0 - MDIO management interface protocol compatible IEEE 1149.1 (JTAG) compliant test mode 1.35V for core, high-speed circuitry and MDIO 3.3V ± 5% for LVDS IO , _3 ± and T1_4 ± . On-chip 50 termination resistors connect from HT1+ and HT1- to VDDHS. HT2+ HT2 , serializer, channel 2. Data is sourced from T1_5 ± , T1_6 ± , T1_7 ± and T1_8 ± . On-chip 50 termination , , T2_2 ± , T2_3 ± and T2_4 ± . On-chip 50 termination resistors connect from HT3+ and HT3- to VDDHS


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PDF SCAN50C400 SCAN50C400 AA10 AA13 P802 UFJ440A SCAN50C400UT AN-124
2007 - AMCC DATE CODE MARKING

Abstract: S19227 S19237 OC-192 framer mapper s19227 amcc part marking marking SCC11 VDD12B S19237PB13 10gb TX drive AMCC STS-192
Text: . 9 External Voltage Controlled Oscillator (XVCO) ­ MDIO Register , . 10 Reference Select (REFSEL) ­ MDIO Register , . 10 Phase Initialization (PHINIT) ­ MDIO Register . 10 TSD Output Amplitude Adjust (TSDAMPADJ) ­ MDIO Register . 11 Automatic FIFO Initialization (AUTO_FIFO_INIT) ­ MDIO Register


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PDF S19237 S19237 16-bit FEC/10 DS1454 AMCC DATE CODE MARKING S19227 OC-192 framer mapper s19227 amcc part marking marking SCC11 VDD12B S19237PB13 10gb TX drive AMCC STS-192
tsmc 0.18um

Abstract: TSMC 0.18um data sheet tsmc cmos RTL code for ethernet TSMC cmos 0.18um data sheet TSMC cmos 0.18um ethernet mdio circuit diagram 20 channel data transmitting circuit repeater 3.125G mdio termination
Text: the MDIO interface Programmable on chip termination resistors Per-channel Built-In Self Test with , , rate compensation FIFO, transmit FIFO, serial MDIO port, programmable pre-emphasis, termination , REFCLK+/JTAG SCAN Power Down MDIO I/F MDIO Registers XAUI State Machine SB1000 is a , /60/75 termination resistors. The pre-emphasis circuit enables the device to open up the transmit eye , features are accessed through MDIO interface. PRBS, incremental patterns, serial forward/reverse, and


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PDF SB1000 SB1000 125Gbps 10Gbps 8B/10B tsmc 0.18um TSMC 0.18um data sheet tsmc cmos RTL code for ethernet TSMC cmos 0.18um data sheet TSMC cmos 0.18um ethernet mdio circuit diagram 20 channel data transmitting circuit repeater 3.125G mdio termination
2007 - AMCC DATE CODE MARKING

Abstract: amcc part marking DS2018 S1220PBIC S1220 SCP68 VDDH25 s1220PB
Text: ]) Typical 320 mW power in LVDS mode Internal termination to the OPTICs LVPECL driver rendering seamless , . 11 MDIO Bus and Address Register , . 14 MDIO REGISTER MAPPING , . 37 Figure 17. Differential LVPECL Output to Differential LVPECL Input DC Coupled Termination . 38 Figure 18. Differential LVPECL Output to Differential LVPECL Input AC Coupled Termination VDDH


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PDF S1220 S1220 OC-12) DS2018 AMCC DATE CODE MARKING amcc part marking DS2018 S1220PBIC SCP68 VDDH25 s1220PB
2000 - LXT970AQC

Abstract: LXT970ATC LXT970A digital clock circuit lxt970ahc "Fast Link Pulse" LXT970 100BASE-FX Tx/Fx Media Converter bob smith termination
Text: 17.3 = 1, termination resistors are not required. 4. The LXT970A supports the 802.3 MDIO register set , <0:1> FDE TRSTE RESET FDS/MDINT MDIO MDDIS MDC XTALI/O RX_CLK CRS COL RX_DV RX_ER , . 17 MII Management Interface ( MDIO ) . 18 Hardware Control Interface , .52 Auto Negotiation and Fast Link Pulse Timing .53 MDIO and MII Timing , MDIO GNDD LEDR LEDT LEDL LEDC LEDS VCCR N/C N/C PWRDWN CFG1 FIBOP FIBON VCCT TREF


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PDF LXT970A 10BASE-T 100BASE-TX RJ-45 100BASE-FX DS-T970A-R1 LXT970AQC LXT970ATC LXT970A digital clock circuit lxt970ahc "Fast Link Pulse" LXT970 Tx/Fx Media Converter bob smith termination
2004 - FCBGA* 19x19

Abstract: MDIO 19X19 ieee1149.1 mdio termination TLK6B008
Text: /3.125G/1.25Gbps 2:1 MUX/1:2 D D D D D Supports IEEE1149.1 JTAG D Supports IEEE802.3 Defined MDIO , Termination Control and Configuration Interface D BIST Features to Support Testing Including D D D , /output ( MDIO ) interface to allow ease in configuration and status monitoring of the link. Individual control of each serial link can be accomplished via the MDIO interface. TLK6B008 supports the IEEE1149 , verification. RefClk 16 Lanes @3.125Gbps TLK6B008 MDIO JTAG Control 8 Lanes @6.25Gbps


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PDF TLK6B008 SLLS608 25G/3 125G/1 25Gbps IEEE1149 IEEE802 19X19 105oC FCBGA* 19x19 MDIO ieee1149.1 mdio termination TLK6B008
2006 - Not Available

Abstract: No abstract text available
Text: on-chip termination Advanced testability features – IEEE 1149.1 and 1149.6 – At-speed BIST pattern , though an MDIO interface as well as through pins, featuring configurable transmitter de-emphasis , €“ REVISED MAY 2008 www.ti.com Block Diagram Rate Select etc. MDIO RXCLK CDR Clock Line , MDIO MDC PVDD33 PVDD33 GND GND PVDD33 PVDD33 GND GND GND REFCLKP REFCLKN AVDD33 AVDD18 , outputs of the serializer. On-chip termination resistors connect from DO+ and DO− to an internal


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PDF SCAN12100 SNLS245D SCAN12100 SCAN25100
2006 - MDIO clause 45

Abstract: remote control transmiter 78 los MDIO clause 45 specification remote transmiter TQFP-100 SCAN25100 SCAN12100TYA SCAN12100 AVDD33
Text: though an MDIO interface as well as through pins, featuring configurable transmitter deemphasis , transmit de-emphasis and receive equalization with on-chip termination Advanced testability features - , Inverting and non-inverting high speed CML differential outputs of the serializer. Onchip termination , and non-inverting high speed differential inputs of the deseralizer. On-chip termination resistors connect from RI+ and RI- to an internal reference. On-chip termination resistors are configured for


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PDF SCAN12100 SCAN12100 MDIO clause 45 remote control transmiter 78 los MDIO clause 45 specification remote transmiter TQFP-100 SCAN25100 SCAN12100TYA AVDD33
2006 - Not Available

Abstract: No abstract text available
Text: Programmable Transmit De-Emphasis and Receive Equalization With On-Chip Termination Advanced Testability , SCAN25100 is programmable though an MDIO interface as well as through pins, featuring configurable , etc. MDIO Link Status (Lock, LOS, LOF, etc.) Configuration (Loopback, Rate, BIST, etc.) Delay , ADD0 ADD1 ADD2 ADD3 ADD4 AVDD18 MDIO MDC PVDD33 PVDD33 GND GND PVDD33 PVDD33 GND GND , CML differential outputs of the serializer. On-chip termination resistors connect from DO+ and DOâ


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PDF SCAN25100 SNLS223C SCAN25100
2001 - bob smith termination

Abstract: LXT9785 transistor Comparison Tables LXT9781 Twisted Pair split termination AN152
Text: support JTAG. · Both devices include a Bob Smith Termination . There are some significant differences , · Receive and Transmit Load Termination Fiber RBIAS Magnetics and I/O - Magnetics for , magnetic center taps are connected. Transmit and Receive Termination Circuitry Requires external , . Fiber Interface All ports are selected for fiber via the Hardware Control Interface and MDIO , termination circuitry. Example shown above is suitable for HFBR5900-series devices. VCCPECL +3.3V +3.3V


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PDF LXT9785 LXT9781-to-LXT9785 AN152. bob smith termination transistor Comparison Tables LXT9781 Twisted Pair split termination AN152
IBM thinkpad r51

Abstract: lcx125 ibm thinkpad board diagram x31 MDIO clause 45 thinkpad r51 ibm thinkpad board x31 ibm thinkpad board diagram a2098 BAV99FSCT-ND PCC2257CT-ND
Text: Configuration and Control Jumpers MDIO Interface JTAG Interface DDR Parallel Interface Onboard Oscillator , synchronize remote base station RE modules to the REC. The SCAN25100 is programmable though an MDIO , detection circuits Programmable transmit de-emphasis and receiver equalization with on-chip termination Flexible pin and MDIO configurability Advanced testability features IEEE 1149.1 and 1149.6 At-speed BIST , 1.8V Supply regulation Buffered Parallel Port interface to internal MDIO registers Access to all


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PDF SCAN25100 IBM thinkpad r51 lcx125 ibm thinkpad board diagram x31 MDIO clause 45 thinkpad r51 ibm thinkpad board x31 ibm thinkpad board diagram a2098 BAV99FSCT-ND PCC2257CT-ND
TSMC 0.13um CMOS

Abstract: "programmable on-chip termination" 10gbps serdes tsmc cmos XCVR CHIP EXPRESS SB1011 ethernet mdio circuit diagram mdio termination
Text: synthesizer, transmit FIFO, optional serial MDIO port, programmable pre-emphasis, termination resistors , on chip termination resistors Per-channel power down mode Synchronizer (receive) PLL recovers clock , RXDATA RXCLK TXPLL + Clock Synthesizer REFCLK+/JTAG SCAN Power Down MDIO I/F MDIO , / 75 termination resistors. The pre-emphasis circuit enables the device to open up the transmit eye as , accessed through optional MDIO interface. PRBS, incremental patterns, serial forward/reverse, and parallel


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PDF SB1011 SB1011 25Gbps 0625Gbps, 125Gbps, 25Gbps, 10b/20b TSMC 0.13um CMOS "programmable on-chip termination" 10gbps serdes tsmc cmos XCVR CHIP EXPRESS ethernet mdio circuit diagram mdio termination
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