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Part Manufacturer Description Datasheet Download Buy Part
LT1242IS8#PBF Linear Technology LT1242 - High Speed Current Mode Pulse Width Modulators; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C
LT1242IS8#TRPBF Linear Technology LT1242 - High Speed Current Mode Pulse Width Modulators; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C
LT1242IJ8 Linear Technology IC SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, CDIP8, CERAMIC, DIP-8, Switching Regulator or Controller
LT1242CJ8 Linear Technology IC 1 A SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, CDIP8, 0.300 INCH, HERMETIC SEALED, CERDIP-8, Switching Regulator or Controller
LT1242CN8 Linear Technology LT1242 - High Speed Current Mode Pulse Width Modulators; Package: PDIP; Pins: 8; Temperature Range: 0°C to 70°C
LT1242MJ8/883B Linear Technology IC 1 A SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, CDIP8, CERDIP-8, Switching Regulator or Controller

mPC 1242 H Datasheets Context Search

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Not Available

Abstract: No abstract text available
Text: Package (15 x 15 Grid) The MPC 82389 is a highly integrated VLSI device that maximizes the performance , throughput. The MPC 82389 also supports geographic addressing by providing access to the local interconnect registers for reference and control. The MPC 82389 is designed to interface with an 8-, 16-, or 32 , sheet is supplemented by a MPC User's Manual, Intel literature number 176526-002. The MPC User’s , Dm34Sl 5-67 HOT 82389 1.0 MPC 82389 INTRODUCTION The 82389 Message Passing Coprocessor ( MPC


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PDF 32-Byte 32-Bit CSM/002
Not Available

Abstract: No abstract text available
Text: transitions. -W A IT 19 T h e -W A IT signal is driven by the MPC to hold up a transfer operation , Message-Passing Coprocessor ( MPC ) provides a highintegration interface solution for the Parallel System Bus , memory and I/O references on the iPSB bus. In addition, the MPC is designed to simplify implementation , space inter­ face, the VL82C389 MPC offloads the interprocessor communication tasks from the local , the MPC component to decouple these resources yields several enhance­ ments to system performance


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PDF VL82C389 VL82C389 than100%
Multibus ii protocol

Abstract: 82389 Multibus arbitration protocol 82389 Message Passing Coprocessor A Multibus II Bus IEEE-1296
Text: 32-Bit CPU) - Low-Cost 8-Bit Microcontroller Interface - Dual-Port Memory Interface The MPC , the maximum bus performance and subsequently increase the system throughput. The MPC 82389 also , control. The MPC 82389 is designed to interface with an 8-, 16-, or 32-bit processor. The Parallel System , performance is possible due to decoupling of the CPU from the PSB. This data sheet is supplemented by a MPC User's Manual, Intel literature number 176526-002. The MPC User's Manual provides detailed information


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PDF 32-Byte 149-Pin 32-Bit CSM/002 Multibus ii protocol 82389 Multibus arbitration protocol 82389 Message Passing Coprocessor A Multibus II Bus IEEE-1296
solna d30

Abstract: 74AS1804 AD23-AD16 bsc5 vlsi technology Multibus arbitration protocol AD31-AD24 Multibus ii protocol sis 968 ia05 transistor
Text: VM82C389 Message-Passing Coprocessor ( MPC ) provides a highintegration interface solution for the Parallel , well as memory and I/O references on the PSB bus. In addition, the MPC is designed to simplify , . By performing the message space interface, the VM82C389 MPC offloads the interprocessor communication , MPC component to decouple these resources yields several enhancements to system performance. For , processors being able to process other tasks in parallel, with message transfers being handled by the MPC


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PDF VM82C389 MIL-STD-883C VM82C389 O12341 solna d30 74AS1804 AD23-AD16 bsc5 vlsi technology Multibus arbitration protocol AD31-AD24 Multibus ii protocol sis 968 ia05 transistor
2001 - 82389

Abstract: Multibus ii protocol BUS22 B1 intel 82389 Multibus II Bus Interface Controller Multibus arbitration protocol multibus II architecture specification IEEE-1296 multibus ARCHITECTURE MPC processor
Text: Technology 149-pin PGA Package (15 x 15 Grid) The MPC 82389 is a highly integrated VLSI device that , the system throughput. The MPC 82389 also supports geographic addressing by providing access to the local interconnect registers for reference and control. The MPC 82389 is designed to interface with an , Interface Controller Contents 1.0 2.0 3.0 4.0 5.0 6.0 7.0 Datasheet MPC 82389 , . 6 1.1.1 MPC 82389 Interfaces


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PDF 32-Byte FIF09 32-bit A8475-01 A8476-01 82389 Multibus ii protocol BUS22 B1 intel 82389 Multibus II Bus Interface Controller Multibus arbitration protocol multibus II architecture specification IEEE-1296 multibus ARCHITECTURE MPC processor
STK 501

Abstract: SN74AS8835 drb-15 74AS8835
Text: Low All Low All Low All Low All Low NO L L L L STK MPC TRAP MPC±DRA MPC±DRA NO L L L H Reserved Reserved Reserved Reserved Reserved NO L L H L STK MPC±DRA MPC + DRA MPC TRAP NO L L H H Reserved Reserved Reserved Reserved Reserved NO L H L L MPC±DRA MPC TRAP DRB DRB NO L H L H Reserved Reserved Reserved Reserved Reserved NO L H H L MPC ± DRA STK STK MPC TRAP NO L H H H Reserved Reserved Reserved Reserved Reserved NO H L L L STK MPC TRAP DRA DRA NO H L L H STK MPC TRAP DRB DRB NO H L H L STK DRA DRA


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PDF SN74AS8835 16-Bit AS890 65-word 20-bit STK 501 SN74AS8835 drb-15 74AS8835
BA021

Abstract: MPC32389 IEEE-1296 82389 ba021p 290145 BAD22 176526
Text: ns for 32-Byte Interrupt Packet) CMOS Technology m 149-Pin PGA Package (15 x 15 Grid) The MPC , the maximum bus performance and subsequently increase the system throughput. The MPC 82389 also , control. The MPC 82389 is designed to interface with an 8-, 16-, or 32-bit processor. The Parallel System , performance is possible due to decoupling of the CPU from the PSB. This data sheet is supplemented by a MPC User's M anual, Intel literature number 176526-002. The MPC U ser's M anual provides detailed


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PDF 32-Byte 32-Bit CSM/002 BA021 MPC32389 IEEE-1296 82389 ba021p 290145 BAD22 176526
Not Available

Abstract: No abstract text available
Text: * i'F p T r * c o H n * n DUAL CONTROL • i * * iPSB INTE R FA C E Figure 3-1. MPC , -Pin PGA Package (15 x 15 Grid) The MPC 82389 is a highly integrated VLSI device that maximizes the , system throughput. The MPC 82389 also supports geographic addressing by providing access to the local interconnect registers for reference and control. The MPC 82389 is designed to interface with an 8-, 16-, or , . This data sheet is supplemented by a MPC User’s Manual, Intel literature number 176526-002. The MPC


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PDF 32-Byte 32-Bit CSM/002
Multibus arbitration protocol

Abstract: multibus II architecture specification BA026
Text: -Byte Interrupt Packet) CMOS Technology 149-Pin PGA Package (15 x 15 Grid) The MPC 82389 is a highly , performance and subsequently increase the system throughput. The MPC 82389 also supports geographic addressing by providing access to the local interconnect registers for reference and control. The MPC 82389 is , to decoupling of the CPU from the PSB. This data sheet is supplemented by a MPC User's Manual, Intel literature number 176526-002. The MPC User's Manual provides detailed information regarding hardware and


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PDF 32-Byte 32-Bit CSM/002 Multibus arbitration protocol multibus II architecture specification BA026
Multibus ii protocol

Abstract: solna d30 176526 multibus II architecture specification
Text: DESCRIPTION The VM82C389 Message-Passing Coprocessor ( MPC ) provides a highintegration interface solution for , spaces, as well as memory and I/O references on the PSB bus. In addition, the MPC is designed to simplify , . By performing the message space inter face, the VM82C389 MPC offloads the interprocessor , . Using the MPC component to decouple these resources yields several en hancements to system performance , handled by the MPC component. BLOCK DIAGRAM ORDER INFORMATION Part Number VM82C389-GMB Package


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PDF VM82C389 MIL-STD-883C VM82C389 Multibus ii protocol solna d30 176526 multibus II architecture specification
82C389

Abstract: No abstract text available
Text: Message-Passing Coprocessor ( MPC ) provides a highintegration interface solution for the Parallel System Bus (PSB , I/O references on the PSB bus. In addition, the MPC is designed to simplify implementation of , MPC offloads the interprocessor communication tasks from the local on-board CPU, which decouples , increases, the dual-port structure degrades system performance even more dramatically. Using the MPC , by the MPC component. ORDER INFORMATION Part Number VM82C389-GMB Package Ceramic Pin Grid


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PDF VM82C389 VM82C389 82C389
1999 - BWP 34

Abstract: SMD Transistor PD8 SMD Transistor PB23 A22 SMD CODE RSM-200 transistor SMD PB29 transistor SMD PB28 SMD TRANSISTOR PD3 SMD LD3 pcmcia for RS232
Text: Bridges 3.3V Indicator - LD1 USB - On Indicator - LD2 USB-PWR - LD3 MEMORY MAP MPC Registers , resonator or 4A MHz Clock generator. t On-Board Expansion connectors, including all MPC pins and , Source. · MPC Keep Alive Power Source 4 Release 0.1 MPC850SARDB User's Manual Hardware , The Device. WARNING Since the MPC clock input is NOT 5V TOLERANT, any clock generator inserted to , DAMAGE might be inflicted to the MPC . 2·3·2 Power-On Reset Source Selection As there are


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PDF MPC850SARDB MPC850SARDB MPC850FADSDB BWP 34 SMD Transistor PD8 SMD Transistor PB23 A22 SMD CODE RSM-200 transistor SMD PB29 transistor SMD PB28 SMD TRANSISTOR PD3 SMD LD3 pcmcia for RS232
BA021

Abstract: No abstract text available
Text: . As an output, the MPC asserts BREQ to request access to the PSB bus. A H B <5.0> (Arbitration) A , ´ iE L O H O M M f DMA CONTROL SIGNALS The MPC provides several DMA control signals to support an , the MPC User’s Manual for more details. — Support of accesses to local interconnect space by , PSB bus via the MPC . Dual-Port Memory Interface to support an alterna­ tive communication approach , the actual data that are transmitted from one MPC to another. The data is once again broken into


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PDF M82389 32-Byte 149-Pin 164-Lead CSM/002 BA021
IEEE-1296

Abstract: BA017 BA011 BAD29 BA022 176526 Multibus ii protocol D1301S M82389 271091
Text: the MPC interconnect interface registers. IWR must provide clean transitions. This pin exhibits V| h , bus via the MPC . Dual-Port Memory Interface to support an alterna tive communication approach which , data that are transmitted from one MPC to another. The data is once again broken into packets and these , initiated by the CPU to the MPC . The MPC responds by putting the CPU on hold while ar bitrating for PSB bus , pattern stored in the slot address reg ister of the MPC . DMA INTERFACE The DMA interface transfers data


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PDF M82389 32-Byte 32-Bit M82389 IEEE-1296 BA017 BA011 BAD29 BA022 176526 Multibus ii protocol D1301S 271091
stk 2250

Abstract: 7B266 microsequencer stk 420 22 pin LV-11S 18-WAY STK 501 DRA13-DRA7 20DR-A branch conditional unconditional instruction
Text: ZERO = H CC = H X X X YES ALL LOW ALL LOW ALL LOW L L L NO STIC MPC DRA L L H NO STK MPC DRB L H L NO STK DRA MPC L H H NO STK DRB MPC H L L NO DRA MPC DRB H L H NO DRA' (18-WAY BRANCH) MPC DRB' (16-WAY BRANCH) H H L NO DRA STK MPC H H H NO DRB STK MPC 2-346 , Texas Instruments POSTOFFICE , MUX2-MUX0 INT RT 12 B3-B0 INT RT 14 Y13-Y0 MPC 10 < h Any Input Any Destination 2 SN74AS890 , 12 S2-S0 Any Destination 10 MUX2 MUXO INT RT 12 B3 BO INT RT 14 Y13-Y0 MPC 10 ' h Any


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PDF SN54AS890, SN74AS890 D2662, 1982-REVISED AS890 Y13-Y0 SN74AS890-1 stk 2250 7B266 microsequencer stk 420 22 pin LV-11S 18-WAY STK 501 DRA13-DRA7 20DR-A branch conditional unconditional instruction
74AS890

Abstract: 74699 DRB11 F11IO D3032
Text: ALL LOW MPC MPC DRA DRB MPC MPC STK STK Y OUTPUT SOURCE CC = H A LL LOW DRA DRB MPC MPC DRB DRB' (16-W AY BRANCH) MPC MPC i H = high level, L = low level, X = irrelevant. * Reset command is , E91 E10 E11 FI F2 F3 F9 F10 F11 G1 G2 G3 G9 G10 G11 H1 H2 H10 H 11 J1 J2 J5 PIN NAME Y12 Y9 S2 SO Y11 , 0074L.Û3 H f j D * T ' " r7'*5l TIET890 M IC RO SEQ U ENCER description (continued , STblTEE 0D74bflS h | ~ D ' T ' H ' Ì - l l S l TIET890 M IC RO S EQ U ENCER PIN NAME BO B1 B2 B3 CC


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PDF 0D74L D3032, TIET890 74AS890 74699 DRB11 F11IO D3032
stk 3105

Abstract: branch conditional unconditional instruction
Text: BRANCH) DRA DRB ZERO = H ALL LOW MPC MPC DRA DRB MPC MPC STK STK Y OUTPUT SOURCE CC = H ALL LOW DRA DRB MPC MPC DRB DRB' (16-W AY BRANCH) MPC MPC H = high level, L = low level, X = irrelevant. ·Reset , division or as loop counters when iterative routines are required. H J K · · · · · , microprogram counter ( MPC register) An external input onto the bidirectional Y output port A 16-way branch , OUTPUT CONTROL MUX CONTROL RESET* MUX2 MUX1 X L L L L H H H H X L L H H L L H H MUXO X L H L H L H L H


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PDF 007ST40 TIET890A TIET890A 0Q7515fl stk 3105 branch conditional unconditional instruction
2015 - MS3470L

Abstract: No abstract text available
Text: Operator’s Guide MPC -1500 Series Military Power Conditioner MPC -1500-S-1U MADE IN USA , . 12 MPC Efficiency , . 31 Two MPC units with AC OUTPUTs Paralleled DS Options. 31 Three MPC units with AC OUTPUTs Paralleled , Hazardous Voltages The INPUT AND OUTPUT POWER connectors and cables of the SynQor MPC may have voltages


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PDF MPC-1500 MPC-1500-S-1U 80Vrms MS3470L
1998 - transistor SMD PB28

Abstract: A29 SMD transistor SMD PB29 A22 SMD CODE Motorola diode SMD code B14 POE-A LXT970 SMD LD3 RJ45 8pin PC MOTHERBOARD CIRCUIT diagram
Text: .10 . . . . . . . . . . .2·3·1·1 . . MPC TOP VIEW , . 15 . . . . . . . . . . .3·4 . . . . MPC Registers' Programming , Specification Document. · MPC - In this document it can be one of the MPC860T or MPC860SAR or MPC860. 1·3 Related Documentation · MPC User's Manual. · ADI Board Specification. · , Thickness 145mm 125 mm 0.063" (1.6 mm) 1·5 MPC860DB Features o MPC running upto 50 MHz o


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PDF MPC860DB MPC860SARDB MPC860TDB MPC860DB MPC860X transistor SMD PB28 A29 SMD transistor SMD PB29 A22 SMD CODE Motorola diode SMD code B14 POE-A LXT970 SMD LD3 RJ45 8pin PC MOTHERBOARD CIRCUIT diagram
1997 - somc1603

Abstract: MPC8XXFADS 1F27FC04 MPC812 MPC860SAR tfds*6000 MPC823 MPC821 MPC801 4816P-001
Text: platform for s/ w and h /w development around the MPC8XX family processors. Using its on-board resources , , display memory and registers and connect his own proprietary h /w via the expansion connectors, to be , / Over Voltage Protection for Power Inputs. t 3.3V / 2V MPC Internal Logic OperationD, 3.3V MPC I/O , platform for s/w and h /w development around the MPC8XX family. Using its on-board resources and its , registers and connect his own proprietary h /w via the expansion connectors, to be incorporated to a system


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PDF 74LCX08D S-8051HN-CD-X LM317MDT 25Mhz CTX093 RSM-200-32 BGA357 MPC860TFADS somc1603 MPC8XXFADS 1F27FC04 MPC812 MPC860SAR tfds*6000 MPC823 MPC821 MPC801 4816P-001
1996 - Telefunken

Abstract: zener Diode B23 DALE SOMC PLUG 41612 elco elco 330 u Elco 90 pin connector 74ACT86 siemens rs232 connector com RMC TYOHM RJ45 datasheet 8P8C
Text: LD14 5V Indicator - LD15 3.3V Indicator - LD16 3·3 MEMORY MAP 3·4 Programming The MPC Registers , Manual Soft Reset 4·2·4 Manual Hard Reset 4·2·5 MPC Internal Sources 4·2·6 Reset Configuration , information about the ADS. The MPC860ADS is meant to serve as a platform for s/w and h /w development around , code, run it, set breakpoints, display memory and registers and connect his own proprietary h /w via , MPC860ADS revision ENG. 1·4·1 Flash Size Limitation Due to H /W design bug, the Flash memory size


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PDF MPC860ADS MPC860ADS, MPC860ADS Telefunken zener Diode B23 DALE SOMC PLUG 41612 elco elco 330 u Elco 90 pin connector 74ACT86 siemens rs232 connector com RMC TYOHM RJ45 datasheet 8P8C
Diode SMD ED 98

Abstract: sw1 spdt Telefunken RSM-200 elco 330 u mt8d432x LD11 MPC821 Siemens LCD Display C75 RCA29
Text: . whenE MPC IV · H DRAMEN~ becomes active-low to allow buffer manipulation supporting LEDs darkCness , BY H RC A D VE I Board Revision - A Issue 0.1 - Draft 8/24/95 - ENG Issue 1.1a - 2/9 , - LD15 3·3 MEMORY MAP 3·4 Programming The MPC Registers 3·4·1 Memory Controller Registers , O 4·2·4 Manual Hard Reset IC 4·2·5 MPC Internal Sources M 4·2·6 Reset Configuration SE E , Buffering IV H - Select Generator 4·6 Chip RC DRAM 4·7 A 4·7·1 DRAM 16 Bit Operation 4·7·2 DRAM


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PDF MPC821 MPC821ADS, Diode SMD ED 98 sw1 spdt Telefunken RSM-200 elco 330 u mt8d432x LD11 Siemens LCD Display C75 RCA29
ROMO

Abstract: yamaha ym yamaha VDP yamaha 68000
Text: Y A M A H A ' L S I Y M 7 3 0 2 M aster Peripheral Controller ( MPC ) OUTLINE The MPC (Master Peripheral Controller) is a single chip integrated circuit , D 5 93 D 6 92 D 7 91 V d d 90 H I B Y T E * 89 U D S * L D S * V s s A , * VSC1* ROM O* ROM1* O E* NVRAM * V DP* EX T0* EX T 1* PIA * V SR* FDC* DMAC* CDC* O 32 H L D R Q , TS TS TS TS TS TS Pin function w affla I/o I/O I/O H ost M PU address input (output when


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PDF CA95112 3K-0305 ROMO yamaha ym yamaha VDP yamaha 68000
2000 - transistor SMD PB28

Abstract: transistor SMD PB29 PC MOTHERBOARD SERVICE MANUAL SMD A18 Transistor A29 SMD P6 MOTHERBOARD SERVICE MANUAL mother board POE-A smd diode code a30 b14 smd diode
Text: .10 . . . . . . . . . . .2·3·1·1 . . MPC TOP VIEW , . 15 . . . . . . . . . . .3·4 . . . . MPC Registers' Programming , Specification Document. · MPC - In this document it can be one of the MPC860T or MPC860SAR or MPC860. 1·3 Related Documentation · MPC User's Manual. · ADI Board Specification. · , Thickness 145mm 125 mm 0.063" (1.6 mm) 1·5 MPC860DB Features o MPC running upto 50 MHz o


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PDF MPC860DB MPC860SARDB MPC860TDB MPC860DB MPC860FADSDBUM/D transistor SMD PB28 transistor SMD PB29 PC MOTHERBOARD SERVICE MANUAL SMD A18 Transistor A29 SMD P6 MOTHERBOARD SERVICE MANUAL mother board POE-A smd diode code a30 b14 smd diode
video transceiver

Abstract: RJ45 datasheet 8P8C DALE SOMC1603 MPC860 MPC850 MPC823 MPC821 MPC801 somc1603 D1639
Text: platform for s/ w and h /w development around the MPC8XX family processors. Using its on-board resources , , display memory and registers and connect his own proprietary h /w via the expansion connectors, to be , / Over Voltage Protection for Power Inputs. t 3.3V / 2V MPC Internal Logic OperationD, 3.3V MPC I/O , become a general platform for s/w and h /w development around the MPC8XX family. Using its on-board , , display memory and registers and connect his own proprietary h /w via the expansion connectors, to be


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