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m80c186 datasheet (11)

Part ECAD Model Manufacturer Description Type PDF
M80C186 M80C186 ECAD Model Intel CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR Original PDF
M80C186-10 M80C186-10 ECAD Model Intel Microprocessor: 16-Bit Data Bus: 10MHz Processor: 68-PGA QFP Original PDF
M80C186-12 M80C186-12 ECAD Model Intel CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR Original PDF
M80C186EB-13 M80C186EB-13 ECAD Model Intel 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Original PDF
M80C186EB-16 M80C186EB-16 ECAD Model Intel 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Original PDF
M80C186EB-8 M80C186EB-8 ECAD Model Intel 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Original PDF
M80C186XL M80C186XL ECAD Model Intel 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Original PDF
M80C186XL10 M80C186XL10 ECAD Model Intel 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Original PDF
M80C186XL12 M80C186XL12 ECAD Model Intel 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Original PDF
M80C186XL16 M80C186XL16 ECAD Model Intel 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Original PDF
M80C186XL20 M80C186XL20 ECAD Model Intel 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Original PDF

m80c186 Datasheets Context Search

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270500

Abstract: M80286 M80C186
Text: HIGH. Only the rising edge is internally synchronized by the M80C186. This means that the falling edge , externally to the M80C186. The use of SRDY provides a relaxed system-timing specification on the Ready input , to the M80C186. When HIGH the M80C186 places write data on the data bus. Data Enable is provided as , following Functional Description describes the base architecture of the M80C186. This architecture is common , 32- and 64-bit integers are supported us ing a Numeric Data Coprocessor with the M80C186. · Ordinal


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PDF M80C186 16-BIT M80186 M80C86/C88 16-Bit 270500 M80286
M801

Abstract: M80C186
Text: the rising edge is internally synchronized by the M80C186. This means that the falling edge of ARDY , externally to the M80C186. The use of SRDY provides a relaxed system-timing specification on the Ready input , transceiver. When LOW, data is transferred to the M80C186. When HIGH the M80C186 places write data on the data , Description describes the base architecture of the M80C186. This architecture is common to the M8086, M8088 , 32- and 64-bit integers are supported us ing a Numeric Data Coprocessor with the M80C186. · Ordinal


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PDF M80C186 16-BIT M80186 M80C86/C88 16-Bit M801
Not Available

Abstract: No abstract text available
Text: connected to the M80C186†™s TEST/BUSY pin. During the RESET se­ quence this pin is HIGH. The M80C186 , /M82188/M8087 Systems 10 MHz and 12 MHz Expands M80C186†™s Data Types to Include 32-, 64-, 80-Bit Floating-Point, 32-, 64-Bit Integers and 18-Digit BCD Operands Directly Extends M80C186†™s Instruction Set , Sheet for an explanation of the M80C186†™s sig­ nals.) This interface has the following characteris , NPRW pins are connected to the RD and WR pins of the M80C186. • CMD 1 and CMDO come from the


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PDF M80C187 80-BIT M8087 M8067 M80387. M80387 M80C186 M80C166/M80C187
Not Available

Abstract: No abstract text available
Text: asynchronous input, and is active HIGH. Only the rising edge is internally synchronized by the M80C186. This , . Synchronous Ready must be synchronized externally to the M80C186. The use of SRDY provides a relaxed , M8286/M8287 data bus transceiver. When LOW, data is transferred to the M80C186. When HIGH the M80C186 , architecture of the M80C186. This architecture is common to the M8086, M8088, M80186 and M80286 , ­ ing a Numeric Data Coprocessor with the M80C186. • Register Operand Mode: The operand is located


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PDF M80C186 16-BIT M8086/M8088 M80186 M8086 M80186 M80C186 M80C86/C88 16-Bit
Not Available

Abstract: No abstract text available
Text: accept a new command. BUSY is active HIGH. 20-74 M80C186 Table 1. M80C186Pin Description , synchronized by the M80C186. This means that the falling edge of ARDY must be synchronized to the M80C186 , the M80C186. The use of SRDY provides a relaxed system-timing specification on the Ready input. This , to the M80C186. When HIGH the M80C186 places write data on the data bus. DËN 39 39 0 , the base architecture of the M80C186. This architecture Is common to the M8086, M8088, M80186 and


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PDF M80C186 16-BIT M80186 M80C86/C88 16-Bit
1996 - m80188

Abstract: M80C m82c59a M80186 M80286 M80C86 M80C186 M8088 M8086 P56H
Text: M80C186 CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR Military Y Y Y Operation Modes , for M80C186 System Development Assembler PL M Pascal Fortran and System Utilities , M80C186 is a CHMOS high integration microprocessor It has features which are new to the M80186 family , ``compatible'' mode the M80C186 is 100% pin-for-pin compatible with the NMOS M80186 (except for M8087 applications) The ``enhanced'' mode of operation allows the full feature set of the M80C186 to be used The


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PDF M80C186 16-BIT M80186 M80C86 16-Bit m80188 M80C m82c59a M80286 M80C186 M8088 M8086 P56H
m8087 intel

Abstract: No abstract text available
Text: Expands M80C186†™s Data Types to Include 32-, 64-, 80-Bit Floating-Point, 32-, 64-Bit Integers and 18-Digit BCD Operands l Directly Extends M80C186†™s Instruction Set to Trigonom etric, Logarithmic , currently executing an instruction. This pin is active HIGH. It should be connected to the M80C186's TEST , an explanation of the M80C186†™s sig­ nals.) This interface has the following characteris­ tics , ­ sponding pins of the M80C186. • The M80C186 pin MCS3/NPS is connected to NPS1; NPS2 is connected to


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PDF M80C187 80-BIT M8087 M80387. M80387 M80C186 80C18 m8087 intel
Not Available

Abstract: No abstract text available
Text: M80C186†™s TEST/BUSY pin. During the RESET se­ quence this pin is HIGH. The M80C186 uses this HIGH , Figure 10 shows. (Refer to the M80C186 Data Sheet for an explanation of the M80C186†™s signals.) With , M80C186†™s Data Types to Include 32-, 64-, 80-Bit Floating-Point, 32-, 64-Bit Integers and 18-Digit BCD Operands ■Directly Extends M80C186†™s Instruction Set to Trigonometric, Logarithmic, Exponential , M80C186. input signals to determine whether the cycle is a read or a write cycle and examines the CMDO


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PDF M80C187 80-BIT M8087 M80387. M80387 M80C186 M80C186/M80C187
M80C187

Abstract: 2-CQFP M82188 2-CQFP package 271087 Tag c0 665 800
Text: Figure 10 shows. (Refer to the M80C186 Data Sheet for an explanation of the M80C186's signals.) With this , / M8087 Systems 10 MHz, 12.5 MHz, and 16 MHz I Expands M80C186's Data Types to Include 32-, 64-, 80-Bit Floating-Point, 32-, 64-Bit Integers and 18-Digit BCD Operands l Directly Extends M80C186's Instruction Set to , instruction. This pin is active HIGH. It should be connected to the M80C186's TEST/BUSY pin. During the RESET , are connected directly to the corre sponding pins of the M80C186. · The M80C186 pin MCS3/NPS is


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PDF M80C187 80-BIT M8087 M80387. M80387 M80C186 M80C186/M80C187 2-CQFP M82188 2-CQFP package 271087 Tag c0 665 800
Not Available

Abstract: No abstract text available
Text: M80C186 Data Sheet for an explanation of the M80C186†™s signals.) With this arrangement, a flipf l opi s , M80C186†™s Data Types to Include 32-, 64-, 80-Bit Floating-Point, 32-, 64-Bit Integers and 18-Digit BCD Operands Directly Extends M80C186†™s Instruction Set to Trigonometric, Logarithmic, Exponential, and , currently executing an instruction. This pin is active HIGH. It should be connected to the M80C186†™s , M80C186†™s sig­ nals.) This interface has the following characteris­ tics: • The M80C187’s NPS1


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PDF M80C187 80-BIT M8087 M80387. M80387 M80C186 M80C186/M80C187
Fortran-86

Abstract: intel 8088 memory 8088 instruction set intel 80186 memory map 80C186XL 80c187
Text: ( M80C186XL16 ) - 12.5 MHz ( M80C186XL12 ) - 10 MHz ( M80C186XL ) Direct Addressing Capability to 1 MByte Memory , , data is transferred to the M80C186XL. When HIGH the M80C186XL places write data on the data bus. DT/R , ) INTRODUCTION The following Functional Description describes the base architecture of the M80C186XL. The , . This is used as the time base for the M80C186XL. The output of the oscillator is not directly available outside the M80C186XL. The recommended crystal configuration is shown in Figure 3b. When used in


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PDF M80C186XL20 16-BIT M80C186XL20) M80C186XL16) M80C186XL12) M80C186XL) 80C186 M80C186XL PL/M-86, Pascal-86, Fortran-86 intel 8088 memory 8088 instruction set intel 80186 memory map 80C186XL 80c187
M80C188

Abstract: UPPER10 GCS2
Text: modes. The M80C186EB is object code compatible with the M80C186 /M80C188 microprocessors. The feature set , /counters and sixteen multiplexed I/O port pins round out the feature set .rf the M80C186EB. M80C186EB , SI Dl BP SP OVERVIEW Figure 1 shows a block diagram of the M80C186EB. The Execution Unit (EU) is , and 1 must not exceed one fourth the operating frequency of the M80C186EB. When the count register , M80C186EB INTRODUCTION The M80C186EB is the first product in a new gener ation of low-power


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PDF M80C186EB M80C186EB M80C186/M80C188 M80C187 M80C188 UPPER10 GCS2
Not Available

Abstract: No abstract text available
Text: ­ fies memory-to-processor interfacing. Figure 3 de­ picts two M28F020s tied to the M80C186 system bus , program verify—are accessed via the command register. M80C186 VCC Ai - ¿ in Vpp VPP Aq a , in a M80C186 System 4fl2bl75 0151455 431 4-106 © ja is n niMiniNi/arsm ■iniel


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PDF M28F020 2048K MD28F020-90 MF28F020-90 MD28F020-12 MF28F020-12 MD28F020-15 MF28F020-15 MD28F020-20 MF28F020-20
M80C186

Abstract: 80C186RP
Text: I R a d i a t i o n H a r d e n e d CHMOS Field 16 - bit Microprocessor 80C186RP For Space Applications s El's 80C186RP (RP for RAD-PAK®) high speed CMOS microcircuit fea tures a minimum 100 kilorad (Si) total dose toler ance. Using SEI's radia tion hardened RAD-PAK® packaging technology, the 80C186RP is fully equivalent to the commercial Intel's M80C18616-bit CMOS microprocessor. It features a , -bit CMOS Microprocessor · Pin Compatible with Intel M80C186 · RAD-PAK® Radiation Hardened Against Natural


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PDF 80C186RP 80C186RP M80C18616-bit 16-bit A19-S6 A19-A16 A15-A0 M80C186
Not Available

Abstract: No abstract text available
Text: M80C186 SYSTEM BUS VC C Ai-A, DQ8-DQ15 * - Vpp VP P A(TA16 vcc A0~A16 DQg-DQy , . > ^ k > RD. 3 O E Figure 3. M28F010 in a M80C186 System PRINCIPLES OF OPERATION


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PDF 1024K M28F010 ER-20, ER-24, 28F010 RR-60, AP-316,
IC1431

Abstract: i28F010
Text: /PRPHLS) 20E 0 M28F010 402bl7S 0001540 7 ßR gyM M A R nf T «Ke-I3-Z-) Vcc M80C186 SYSTEM BUS , . > OE WE 51 271111-4 Figure 3. M28F010 In a M80C186 System PRINCIPLES OF OPERATION


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PDF Hfl2bl75 M28F010 1024K M28F010 00aiSb3 402bl7S IC1431 i28F010
TCS 4199

Abstract: M80C186
Text: *6 5 1 1 7 5 OlbqflQ? 57b _4-181 M28F010 VCC ` ` M80C186 SYSTEM , MCS1 AND MCS2 BHË W R *0 R D _=o WE OE OE 271111-4 Figure 3. M28F010 in a M80C186


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PDF M28F010 1024K M28F010 TCS 4199 M80C186
Intel 82786

Abstract: M80286 M82786 IC cd 1619 CP M80C186 s24 cst 82786 intel
Text: cycles. The M80C186 can execute write cycles with one less wait state than mentioned above. For , 8 (16 MHz M80386, 8 MHz M82786) Minimum M80C186 Wait States = 3 (10 MHz M80C186 and M82786, WT = 1) Minimum M80C186 Wait States = 2 (10 MHz M80C186 and M82786, WT = 0) The values mentioned above are for


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PDF M82786 M82786 TM10- M802B6 M80186 M827S6 Intel 82786 M80286 IC cd 1619 CP M80C186 s24 cst 82786 intel
M28F020

Abstract: intel 27122
Text: M28F020S tied to the M80C186 system bus. The M28F020's architecture minimizes inter face circuitry needed , a M80C186 System 4-156 m 4fl2bl?5 G i p f l e 07b P R ig y a a o iM o w


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PDF M28F020 2048K 32-Pin 32-Lead MIL-STD-883: 1bl75 M28F020 120ns MD28F020-90 MD28F020-12 intel 27122
M28F020

Abstract: M80C186 M28F020-20
Text: . Figure 3 de picts two M28F020s tied to the M80C186 system bus. The M28F020's architecture minimizes inter , M80C186 System P R B y o a O N A IO T M28F020 Table 2. M28F020 Bus Operations Pins Operation


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PDF M28F020 2048K 32-Pin 32-Lead MIL-STD-883: M28F020 MD28F020-90 MF28F020-90 M80C186 M28F020-20
M28F020-20

Abstract: MD28F020-20/B
Text: two M28F020s tied to the M80C186 system bus. The M28F020’s architecture minimizes inter­ face , M80C186 System 3-26 ß fölLD O M O D IK l^O ftf ■4 û 2 b l ? b OGfib'ilS 36b ■intel


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PDF M28F020 2048K MD28F020-90 MD28F020-12 MD28F020-15 MD28F020-20 MF28F020-90 MF28F020-12 MF28F020-15 MF28F020-20 M28F020-20 MD28F020-20/B
tcl 110011 ic

Abstract: lm 398- SAMPLE AND HOLD
Text: ( M80C186XL16 ) - 12.5 MHz ( M80C186XL12 ) - 10 MHz ( M80C186XL ) Direct Addressing Capability to 1 MByte Memory , Symbol Parameter M80C186XL16 Min Max M80C186XL20 Min Max Unit Test Conditions M80C186XL GENERAL TIMING , M80C186XL is a Modular Core re-implementation of the M80C186 microprocessor. It offers higher speed and , flow through an external data bus transceiver. When LOW, data is transferred to the M80C186XL. When , Description describes the base architecture of the M80C186XL. The M80C186XL is a very high integration 16


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PDF M80C186XL20 16-BIT M80C186XL20) M80C186XL16) M80C186XL12) M80C186XL) 80C186 M80C186XL PL/M-86, Pascal-86, tcl 110011 ic lm 398- SAMPLE AND HOLD
1996 - MG80C186

Abstract: MG80C186EB M80C188 m80c187 M80C186EB-13 order 231369 MG80C AD947 M80C186EB-8 MG80C186EB-13/Q
Text: Characteristics M80C186EB-13 AC Characteristics M80C186EB-8 Relative Timings ( M80C186EB-16 -13 -8) Serial Port , ) 13 MHz ( M80C186EB-13 ) 8 MHz ( M80C186EB-8 ) Available In 88-Lead Pin Grid Array (MG80C186EB) Y , 55 V 0 32 MHz M80C186EB-13 0 26 08 MHz M80C186EB-8 0 16 MHz b , (Notes 2 7) ICC Supply Current Cold (RESET) M80C186EB-16 90 mA (Note 3) M80C186EB-13 , M80C186EB-16 -13 -8 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Full Static Operation True CMOS


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PDF M80C186EB-16 16-BIT 16-Bit ASM86 MG80C186 MG80C186EB M80C188 m80c187 M80C186EB-13 order 231369 MG80C AD947 M80C186EB-8 MG80C186EB-13/Q
1996 - 80C186

Abstract: 80C187 M80C186 M80C186XL M80C186XL12 M80C186XL16 M80C186XL20
Text: Speed Versions Available 20 MHz ( M80C186XL20 ) 16 MHz ( M80C186XL16 ) 12 5 MHz ( M80C186XL12 ) 10 MHz , Parameter M80C186XL16 Min Max M80C186XL20 Min Unit Test Conditions Max M80C186XL , M80C186XL16 Min Max M80C186XL20 Min Unit Test Conditions Max M80C186XL GENERAL TIMING , M80C186XL16 Min Max M80C186XL20 Min Unit Test Conditions Max M80C186XL GENERAL TIMING , Range b 55 C to a 125 C (TC) The Intel M80C186XL is a Modular Core re-implementation of the M80C186


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PDF M80C186XL20 16-BIT M80C186 80C187 16-Bit TP118 80C186 80C187 M80C186 M80C186XL M80C186XL12 M80C186XL16
mg80c186

Abstract: 523ap order 231369 M801 80C186EB
Text: Voltage Input Clock Frequency M80C186EB-16 M80C186EB-13 M80C186EB-8 TC Case Temperature Under Bias Min 4.5 , and 64 Kbyte I/O Speed Versions Available: - 16 MHz ( M80C186EB-16 ) - 13 MHz ( M80C186EB-13 ) - 8 MHz ( M80C186EB-8 ) Low-Power Operating Modes: - Idle Mode Freezes CPU Clocks but keeps Peripherals Active - , Characteristics- M80C186EB-16 _ 3-24 AC Characteristics- M80C186EB-13 _ 3-25 AC Characteristics- M 80C 186E , in te i M80C186EB-16 , -13, -8 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR · Full Static Operation ·


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PDF M80C186EB-16, 16-BIT M80C186EB-16) M80C186EB-13) M80C186EB-8) mg80c186 523ap order 231369 M801 80C186EB
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