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Part Manufacturer Description Datasheet Download Buy Part
DC392A-B Linear Technology LTC1628 or LTC3728 Evaluation Kit
DC392A-A Linear Technology LTC1628 or LTC3728 Evaluation Kit
DC392A-C Linear Technology LTC1628 or LTC3728 Evaluation Kit
LF198AJ8 Linear Technology IC SAMPLE AND HOLD AMPLIFIER, CDIP8, Sample and Hold Circuit
LF198S Linear Technology IC SAMPLE AND HOLD AMPLIFIER, PDSO, Sample and Hold Circuit
LF198AS Linear Technology IC SAMPLE AND HOLD AMPLIFIER, PDSO, Sample and Hold Circuit

logic diagram of 74185 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
7408 CMOS

Abstract: TTL 7452 ttl 74183 LS 74141 7408, 7404, 7486, 7432 7404 7408 7432 TTL 74289 CMOS 4017 series ttl 74395 74106
Text: COUNTS OF C-MOS LOGIC Part No. Count Part No. Count Part No. Count Part No. Count 4000 5 4038 74 4153 , consists of silicon gate CMOS arrays whose interconnection are initially unspecified, therefore custom LSI , . Master chip consists of basic cell, i.e. 2 input NAND gate equivalently which is placed at regular intervals along the row and column of the chip, also consist of I/O pads which are compatible of CMOS or TTL , capabilities as schematic or netlist entry, logic simulation, internal layout, automatic place and route and a


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PDF KG10000 7408 CMOS TTL 7452 ttl 74183 LS 74141 7408, 7404, 7486, 7432 7404 7408 7432 TTL 74289 CMOS 4017 series ttl 74395 74106
truth table for ic 74138

Abstract: ALU IC 74183 16CUDSLR IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
Text: cycles Elim ination of un u sed gates A utom atic pin and p art assignm ents SALSA logic m inim ization , ation. Figure 1. A+PLUS Block Diagram A+PLUS Simulation Virtual Logic Analyzer (V LA) Functional , allow s the user to quickly construct a w ide range of logic circuits. LogiCaps provides two libraries , EPLD nam e, the T ranslator autom atically selects the EPLD best suited to the logic requirem ents of , ct term s. Logic m inim ization of designs is perform ed by the M inim izer m odule. M inim ization


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PDF 44-Mbyte, 386-based truth table for ic 74138 ALU IC 74183 16CUDSLR IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
74ls82

Abstract: 74245 BIDIRECTIONAL BUFFER IC 74ls150 ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 74245 BUFFER IC ic 7483 BCD adder Quad 2 input nand gate cd 4093 data sheet ic 74139
Text: most common interface points are unsimulated logic diagram or simulated netlist though, of course, many , capability. The corresponding library (Lib D4) offers a large choice of logic functions ranging from simple , cells may be configured to give a variety of logic functions by changing the way in which the , example configuration for a 2-input NAND gate is shown in figure 2. The complexity of logic functions made , control logic etc. This overhead is dependent upon the exact configuration of the memory in question


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74LS82

Abstract: 74245 BIDIRECTIONAL BUFFER IC ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 advantages for ic 7473 la 4508 ic schematic diagram 4 BIT COUNTER 74669 XF107 random number generator by using ic 4011 and 4017 74295
Text: interface points are unsimulated logic diagram or simulated netllst though, of course, many others are , large choice of logic functions ranging from simple Boolean gates to com plex counter bit slices and , an inner core of identical uncommited logic cells arranged as a complete matrix without the customary , figure 1). These uncommitted cells may be configured to give a variety of logic functions by changing the , of logic functions made in this way ranges from simple Boolean gates, needing only a single array


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ic 74226

Abstract: jk flip flop 74103 ic D flip flop 7474 7471 rs flip flop 4011 flip flop IC 7400 SERIES list 7414 NOT gate ic IC LA 74141 Ic ttl 7490, 7493, 7495 ci 74386
Text: IP LAYOUT OF Bi-CMOS GATE ARRAY A s seen in th e p a tte r n la y o u t o f th e 3G 02 m a s te r ch , designing th e logic c ir c u it, it is recom m en d ed to u se C M O S 4000 s e r ie s a v a ila b le in th , perature Storage Tem perature Conditions W ith respect to GND In case of the lowest potential being , 1SE ? 7744^0 0000705 T c LIST OF CHA RA CTERISTICS · SMALL SIGNAL N PN TRANSISTOR Param , 58 In the case of same shape resistor ELECTRICAL C HA RA CTERISTICS · DC ELECTRICAL C H A RA


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PDF RP3G01 RP3G01 ic 74226 jk flip flop 74103 ic D flip flop 7474 7471 rs flip flop 4011 flip flop IC 7400 SERIES list 7414 NOT gate ic IC LA 74141 Ic ttl 7490, 7493, 7495 ci 74386
74LS324

Abstract: 7400 TTL 74LS327 7402, 7404, 7408, 7432, 7400 80C96 74251 multiplexer 74LS324 equivalent 74C08 equivalent 74C923 equivalent Flip-Flop 7473
Text: LOGIC (INCLUDES SERIES 74C CMOS) NTE TYPE NO. ·DESCRIPTION . PAGE DIAG NO. NO. NTE TYPE NO , controlled rise and fall times. H = The 74H series Is a line of high speed gates and flip-flops. These , Schottky, a type of TTL with a current and power reduction by a factor of 5 (compared to 7400 TTL), and an anti saturation schottkydiode. · .· . · S = The 74S series is a line of super high speed devices. A type of TTL. They have a schottky-barrier diode clamping on all normally saturated devices. 1-272


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PDF G0G513S 74C00 74H00 74LS00 74S00 74H01 74LS01 74C02 74LS02 74S02 74LS324 7400 TTL 74LS327 7402, 7404, 7408, 7432, 7400 80C96 74251 multiplexer 74LS324 equivalent 74C08 equivalent 74C923 equivalent Flip-Flop 7473
ALU IC 74381

Abstract: encoder IC 74147 16CUDSLR 74139 truth table ic 7447 truth table alu 74382 truth table for 7446 from IC 74373 truth table pin diagram of ic 74190 truth table for ic 74138
Text: PLDS-HPS, PLS-HPS, PLS-OS & PLS-ES A N & r * a \ MAX+PLUS II Programmable Logic , internal nodes. T h e b id irectio n al H D IF 2 0 0 netlist interface is com patible w ith a v a rie ty of , U S II is an integrated C A E tool for d esigning logic w ith A lte ra 's Classic, M A X 5000, M A X , lock d ia g ram of M A X + P L U S II. T he P L D S - H P S D e v e lo p m e n t System includes M A X , ith m u ltip le files open at a n y time. In ad d itio n , M A X + P L U S II includes a lib ra ry of


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PDF 486-based 12-ms 44-Mbyte, ALU IC 74381 encoder IC 74147 16CUDSLR 74139 truth table ic 7447 truth table alu 74382 truth table for 7446 from IC 74373 truth table pin diagram of ic 74190 truth table for ic 74138
1998 - LEAPER-3

Abstract: 74189 7489 sram 89C51 interfacing with lcd display 4N34 ic 74192 pin configuration interfacing 20x4 LCD with 89c51 IC 74189 DATA LEAP-U1 LEAPER-10 driver
Text: environment of development. Additional, the Company has been qualified by major IC manufacturer such as ATMEL , currently offers four types of product lines which are Programmer, Emulator, Tester, Protector. They are developed and manufactured by using a broad range of processes and methods. Programmer which is providing in a wide variety of modules has dominated the priority in Leap for a long time. To meet the demands of mass production,Gang Programmer SU-2000 is the revolutionized product released in the mid 1997


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PDF PIC16C52/54/54A PIC16C55/56/57/57A/58A PIC12C508/509 PIC16C61 PIC16C620/621/622 PIC16C71/710 PIC16C62/63/64/65 PICC16C72/73/74/74A PIC16C83/84 PIC17C42/42A/43/44 LEAPER-3 74189 7489 sram 89C51 interfacing with lcd display 4N34 ic 74192 pin configuration interfacing 20x4 LCD with 89c51 IC 74189 DATA LEAP-U1 LEAPER-10 driver
FZK101

Abstract: FZK105 upd101 SNF10 SN76131 TAA700 FZH111 MFC8010 FZJ101 MFC8001
Text: (Union Carbide) LTT Unitra Lucas Valvo Marconi Westinghouse Mostek CONTENTS PART 1 Index of Integrated Circuit Type Numbers 2 Index Of Groups 3 Equivalents L ist 4 Equivalents too Late for Classification in F art 3 PAGE 7 68 \ . 78 122 IN TR O D U C TIO N T h is book Includes all available types of Integrated Circuits made throughout the world at the tim e of publication which have some possible equivalent , Index of IC type numbers (Fart 1) : opposite this type is shown a number denoting the’section o r


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PDF Grou19 CN127-128-638 ZN220-320. CN131-132-642. ZN221-321. CN133-134-644. ZN248-348. CN135-136-646 ZN222-322. CN121-122-682. FZK101 FZK105 upd101 SNF10 SN76131 TAA700 FZH111 MFC8010 FZJ101 MFC8001
2003 - Not Available

Abstract: No abstract text available
Text: - Timing Diagram of Clock Correction - Add a SKP ©2000-2003 Genesys Logic Inc.—All rights , Diagram of Disparity Error ©2000-2003 Genesys Logic Inc.—All rights reserved. Page 21 , ] PHYSTS TXP/TXN ACTIVE Figure 5.15 - Timing Diagram of P0 to P0s ©2000-2003 Genesys Logic , [1:0] P0 P2 PHYSTS Figure 5.19 - Timing Diagram of P2 Entry ©2000-2003 Genesys Logic , PD[1:0] P2 P1 PHYSTS Figure 5.20 - Timing Diagram of P2 Exit ©2000-2003 Genesys Logic


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PDF GL230 GL230
2003 - TSMC 0.35Um

Abstract: No abstract text available
Text: : Copyright © 2003 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic Inc. Disclaimer , RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC. GENESYS LOGIC HEREBY DISCLAIMS , WITHOUT NOTICE. Trademarks: is a registrated trademark of Genesys Logic Inc. All trademarks are the properties of their respective owners. Office: Genesys Logic , Inc. 12F, No. 205, Sec. 3, Beishin Rd


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PDF GL800AHU35 GL800AHU35 TSMC 0.35Um
1998 - lms algorithm using verilog code

Abstract: lms algorithm using vhdl code ATM machine working circuit diagram using vhdl verilog code for lms adaptive equalizer for audio verilog code for lms adaptive equalizer digital IIR Filter VHDL code 8086 microprocessor based project verilog DTMF decoder qpsk demodulation VHDL CODE verilog code for fir filter using DA
Text: ensures that the placement of the megafunction is optimized for high performance. Assign the WYSIWYG logic , very compact design that minimizes logic cell count while offering double the bandwidth performance of , descriptions of megafunctions from each AMPP partner. The information in this catalog is current as of the , includes a list of key features, a functional description with information on applicable standards , company. The partner profile may also include a list of available megafunctions and a description of


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2008 - gl827l

Abstract: No abstract text available
Text: © 2008 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic , Inc. Disclaimer: ALL , GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC. GENESYS LOGIC HEREBY DISCLAIMS ALL , trademark of Genesys Logic , Inc. All trademarks are the properties of their respective owners. Office , FIGURE 6.3 - TIMING DIAGRAM OF RESET WIDTH . 17


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PDF GL827L GL827L 827L-01 827L-02 827L-03
1996 - M68000

Abstract: 000000FFFF
Text: advantage of PLDs is that at this stage the designer needs to be concerned only with the required logic , logic block. The outputs generated are ROMCS1, ROMCS2 and RAMCS. The generation of signals for , the functional nature of the problem. Sometimes timing and logic considerations can also dictate the , that must be provided in a PLD is the number of pins needed for the basic logic function. This , Diagram Logic Equations Assemble Design File Assemble Design File Simulate the Design


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PDF 0002A-13 M68000 000000FFFF
1999 - FUZZY MICROCONTROLLER

Abstract: block diagram induction heating C422 ST52 Dualogic TYPE 2 FUZZY LOGIC TRIAC THREE PHASE ANGLE CONTROLLER DESIGN A SPEED CONTROL OF DC MOTOR USING FUZZY LOGIC Block dig of speed control of single phase induction motor induction heating oscillator circuit 3 phase induction motor control using triac
Text: ST52 TM DuaLogic A NEW FAMILY OF MCU WITH FUZZY CAPABILITIES Fuzzy Logic B.U , .0 DEVELOPMENT SYSTEM Fuzzy Logic B.U. 3 ST52 Family Block Diagram OSCILLATOR ALU & FUZZY CORE , Logic B.U. 5 ST52x301 Block Diagram ALU & FUZZY CORE OSCILLATOR BAND-GAP REFERENCE , 4 5 6 7 REG_CONF11 Fuzzy Logic B.U. 9 TIMER BLOCK DIAGRAM TOS 0 1 2 , period of 80 kHz Fuzzy Logic B.U. 12 ST52x301 Triac Driver Characteristics 16 bit prescaler


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PDF ST52x410 ST52x301 FUZZY MICROCONTROLLER block diagram induction heating C422 ST52 Dualogic TYPE 2 FUZZY LOGIC TRIAC THREE PHASE ANGLE CONTROLLER DESIGN A SPEED CONTROL OF DC MOTOR USING FUZZY LOGIC Block dig of speed control of single phase induction motor induction heating oscillator circuit 3 phase induction motor control using triac
half-adder by using D flip-flop

Abstract: ME 9926 fairchild micrologic L9915 700S2 rtl micrologic 900 mod 8 using jk flipflop rs FLIPFLOP SCHEMATIC rtl micrologic dual flip flop 8-pin
Text: resistor-transistor logic and capable of performing logic functions for use in digital electronic equipment. The , * GND FUNCTIONS POSITIVE LOGIC : B = A NEGATIVE LOGIC : B = A SCHEMATIC DIAGRAM TYPICAL RESISTOR VALUES Ri , of any logic function through the exclusive use of gate elements. Individual gate elements may be , LOGIC : F = AB + CD SCHEMATIC DIAGRAM TYPICAL RESISTOR VALUES R, = 450S 2 Ri = 640S! Ri = 800SÌ INPUTS , logic inputs, while the third provides the complement of the gating signal at an output pin. Because of


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PDF SL-218 half-adder by using D flip-flop ME 9926 fairchild micrologic L9915 700S2 rtl micrologic 900 mod 8 using jk flipflop rs FLIPFLOP SCHEMATIC rtl micrologic dual flip flop 8-pin
2006 - 93C46 SMD

Abstract: 93c46 wp 93C46
Text: Timing Diagram of External Flash ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 20 , Reader Controller Figure 6.5 - Timing Diagram of SmartMedia ©2000-2006 Genesys Logic Inc. - All , Stick PRO Figure 6.7 - Timing Diagram of MemoryStick PRO ©2000-2006 Genesys Logic Inc. - All , : Copyright © 2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic Inc. Disclaimer


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PDF GL827 GL827 100-pin 48-pin 93C46 SMD 93c46 wp 93C46
2006 - Memory Stick pro duo pinouts

Abstract: memory stick pro duo pin datasheet Memory Stick pinouts 93C46 93C46 IC GL817 Memory Stick Micro pro duo card IC 93c46 SD Card and MMC Reader
Text: Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic Inc. Disclaimer: ALL MATERIALS ARE , PATENT OR TRADEMARK OF GENESYS LOGIC INC. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS , LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF , . Trademarks: is a registered trademark of Genesys Logic , Inc. All trademarks are the properties of their


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PDF GL817E GL817E 48-pin Memory Stick pro duo pinouts memory stick pro duo pin datasheet Memory Stick pinouts 93C46 93C46 IC GL817 Memory Stick Micro pro duo card IC 93c46 SD Card and MMC Reader
2001 - HVo5 diode

Abstract: transistor bipolar driver schematic MSC1164 MSC1164GS-K SSOP32-P-430-1 HVO10
Text: Diagrams of Logic Portion Input and Output Circuits Input Pin VCC VCC INPUT GND GND Output Pin VCC VCC DOUT GND GND Schematic Diagram of Driver Output Circuit VHV VHV HVO , power of the logic portion while holding the CL pin to "L". 2) Turn on the power of the driver portion , in documents to OKI Semiconductor Co., Ltd. The semiconductor business of Oki Electric Industry Co , that although the terms and marks of "Oki Electric Industry Co., Ltd.", "Oki Electric", and "OKI"


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ups circuit schematic diagram

Abstract: led driver circuit diagram ups schematic diagram MSC1212-01 MSC1212-01GS-BK P048 QFP64-P-1414-0
Text: -01 INPUT AND OUTPUT CONFIGURATION • Schematic Diagrams of Logic Portion Input Circuit Vdisp à Vcc^ A INPUT □-—wv- A 777" GND Th- GND Schematic Diagrams of Logic Portion Input • Schematic Diagrams of Logic Portion Input Circuit (Pull-up) Circuit (Pull-down) Schematic Diagrams of Logic Portion , . Input pin of shift register. Display data input is synchronized with clock signal, (positive logic , consists of a 48-bit shift register and a 48-bit latch; they control display data, which is output from


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PDF E2C0021-27-Y3 MSC1212-01 48-Bit MSC1212-01 64-pin ups circuit schematic diagram led driver circuit diagram ups schematic diagram MSC1212-01GS-BK P048 QFP64-P-1414-0
2001 - MSC1212-01

Abstract: po48 MSC1212-01GS-BK QFP64-P-1414-0
Text: Semiconductor MSC1212-01 INPUT AND OUTPUT CONFIGURATION · Schematic Diagrams of Logic Portion Input Circuit VDISP VCC INPUT GND GND · Schematic Diagrams of Logic Portion Input · Schematic Diagrams of Logic Portion Input Circuit (Pull-down) Circuit (Pull-up) VDISP VCC VDISP INPUT VCC INPUT GND GND GND GND · Schematic Diagrams of Logic Portion Output · Schematic , logic ) Input pin without pull-up or pull-down resistor. Clock Input 23 CLK Data of shift


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PDF FEDL1212-01-03 MSC1212-01 48-Bit MSC1212-01 64-pin po48 MSC1212-01GS-BK QFP64-P-1414-0
2006 - power one pmp 6.24

Abstract: 8051 timing diagram block diagram of fingerprint sensor "Fingerprint Sensor" fingerprint twc digital cable tv decoder diagram fingerprint image sensor genesys logic usb reader to dvd player circuit diagram 128-PIN
Text: without prior written consent of Genesys Logic Inc. Disclaimer: ALL MATERIALS ARE PROVIDED "AS IS , TRADEMARK OF GENESYS LOGIC INC. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO , PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR , registeredd trademark of Genesys Logic , Inc. All trademarks are the properties of their respective owners , /02/2006 Modified the timing diagram of host interface 1.04 07/10/2006 Modified the timing


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PDF GL824/GL824C GL824/GL824C GL824C GL824-MZGXX 208-pin GL824C-MXGXX 128-pin power one pmp 6.24 8051 timing diagram block diagram of fingerprint sensor "Fingerprint Sensor" fingerprint twc digital cable tv decoder diagram fingerprint image sensor genesys logic usb reader to dvd player circuit diagram
2007 - Not Available

Abstract: No abstract text available
Text: without prior written consent of Genesys Logic , Inc. Disclaimer: ALL MATERIALS ARE PROVIDED “AS ISâ , TRADEMARK OF GENESYS LOGIC INC. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO , PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR , registered trademark of Genesys Logic , Inc. All trademarks are the properties of their respective owners , flash memory in page10. 1.03 06/02/2006 Modified the timing diagram of host interface 1.04


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PDF GL824/GL824C GL824/GL824C NON-551) GL824C GL824 208-pin GL824C 128-pin
2001 - MSC1164

Abstract: SSOP32 MSC1164GS-K SSOP32-P-430-1 VHV65V
Text: MSC1164 INPUT AND OUTPUT CONFIGURATION Schematic Diagrams of Logic Portion Input and Output Circuits , Schematic Diagram of Driver Output Circuit VHV VHV HVO GND GND 3/13 FEDL1164-03 ¡ , power of the logic portion while holding the CL pin to "L". 2) Turn on the power of the driver portion , chip. The logic portion such as the input stage, shift register and latch is fabricated by CMOS and , pull-down and built-in 20-bit shift register and latch. · Logic Supply Voltage (VCC) : 5V : 65V · Driver


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PDF FEDL1164-03 MSC1164 20-Bit MSC1164 32-pin SSOP32 MSC1164GS-K SSOP32-P-430-1 VHV65V
2006 - Not Available

Abstract: No abstract text available
Text: diagram of host interface First Formal Release ©2000-2006 Genesys Logic Inc. - All rights reserved , without prior written consent of Genesys Logic Inc. Disclaimer: ALL MATERIALS ARE PROVIDED “AS ISâ , TRADEMARK OF GENESYS LOGIC INC. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO , PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR , registeredd trademark of Genesys Logic , Inc. All trademarks are the properties of their respective owners


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PDF GL824/GL824C GL824/GL824C GL824C GL824-MZGXX 208-pin GL824C-MXGXX 128-pin
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