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DC392A-A Linear Technology LTC1628 or LTC3728 Evaluation Kit
DC392A-B Linear Technology LTC1628 or LTC3728 Evaluation Kit
DC392A-C Linear Technology LTC1628 or LTC3728 Evaluation Kit
LF198S Linear Technology IC SAMPLE AND HOLD AMPLIFIER, PDSO, Sample and Hold Circuit
LF198AJ8 Linear Technology IC SAMPLE AND HOLD AMPLIFIER, CDIP8, Sample and Hold Circuit
LF198AS Linear Technology IC SAMPLE AND HOLD AMPLIFIER, PDSO, Sample and Hold Circuit

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74160 pin description

Abstract: 74160 pin diagram of 74163 74160 function table LS161A 74161 logic diagram of 74160 74163 74163 four bit binary counter LS161
Text: Multistage Counting Scheme LOGIC DIAGRAM , 74160 »0 5 o O O <14) °0 December 4, 1985 5-286 This , 853-0531 81502 Signetics Logic Products Product Specification Counters 74160 , 74161, 74163, LS160A , pulse can be used to enable the next cascaded stage (see Figure B). For conventional operation of 74160 , By Its Respective Manufacturer Signetics Logic Products Product Specification Counters 74160 , Counters 74160 , 74161, 74163, LS160A, LS161A, LS162A, LS163A LOGIC DIAGRAMS LS160A 03 Oj D, o0 LD03030S


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PDF 74LS160A, 74LS162A) 74LS161A, 74LS163A) LS160A, LS161A, LS162A, LS163A 74160 pin description 74160 pin diagram of 74163 74160 function table LS161A 74161 logic diagram of 74160 74163 74163 four bit binary counter LS161
IC 74161

Abstract: IC 74160 lm 74161 IC 74160 decade counter diagram ic 74163 IC 74160 for decade counter 74160 LM 74160 pin diagram of ic 74163 74161/74160 function table
Text: AF0230'S Figure 1 LOGIC DIAGRAM , 74160 d3 d2 d, Do LD03020S December 4, 1985 5-286 Signetics Logic Products Product S pecification Counters 74160 , 74161, 74163, LS160A, LS161A , (see Figure B). For conventional operation of 74160 , 74161 and 74163, the following transitions should , Logic Products Product S pecifica tio n Counters 74160 , 74161, 74163, LS160A, LS161A, LS162A , roduct S pe cifica tio n Counters 74160 , 74161, 74163, LS160A, LS161A, LS162A, LS163A LOGIC


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PDF 74LS160A, 74LS162A) 74LS161A, 74LS163A) 54LS/74LS IC 74161 IC 74160 lm 74161 IC 74160 decade counter diagram ic 74163 IC 74160 for decade counter 74160 LM 74160 pin diagram of ic 74163 74161/74160 function table
Not Available

Abstract: No abstract text available
Text: 1 74160 , 74161, 74163, LS160A, LS161A, LS162A, LS163A S ig n e lic s Counters Logic , 81502 Product Specification Signetics Logic Products Counters 74160 , 74161, 74163, LS160A , PE inputs are HIGH at or before the transi­ tion. For conventional operation of 74160 , 74161 , Specification Signetics Logic Products Counters 74160 , 74161, 74163, LS160A, LS161A, LS162A, LS163A , MR Qo Qi C 3a Q* È TERMINAL CO U N T *6 AF02301S Figure 1 LOGIC DIAGRAM


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PDF LS160A, LS161A, LS162A, LS163A 32MHz 74LS160A 74LS163A 74LS160tput S4LS/74LS
ic 74160

Abstract: IC 74160 decade counter diagram ic 74163 IC 74161 pin diagram of ic 74163 lm 74161 diagram of IC 74160 of 74160 ic LM 74160 diagram of IC 74161
Text: Counting Scheme LOGIC DIAGRAM , 74160 O3 Dj Dj D0 December 4, 1985 5-286 Signetics Logic , Signetics 74160 , 74161, 74163, LS160A, LS161A, LS162A, LS163A Counters Logic Products '160 , 653-0531 81502 Signetics Logic Products P roduct S pecifica tio n Counters 74160 , 74161, 74163 , enable the next cascaded stage (see Figure B). For conventional operation of 74160 , 74161 and 74163, the , Signetics Logic Products P roduct S p ecification Counters 74160 , 74161, 74163, LS160A, LS161A


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PDF LS160A, LS161A, LS162A, LS163A 74LS160A, 74LS162A) 74LS161 74LS163A) 54LS/74LS F08270S ic 74160 IC 74160 decade counter diagram ic 74163 IC 74161 pin diagram of ic 74163 lm 74161 diagram of IC 74160 of 74160 ic LM 74160 diagram of IC 74161
pin diagram of 74160

Abstract: 74160 function table pin diagram of 74163 74160 pin 74163 pin configuration 74ls161 counter pin configuration 74160 logic diagram of 74160 logic diagram 74160 74160 counter
Text: .6 AF02301S Figure 1 LOGIC DIAGRAM , 74160 December 4, 1985 5-286 This Material Copyrighted By Its Respective Manufacturer Signetics Logic Products Product Specification Counters 74160 , 74161, 74163 , Signetics 74160 , 74161, 74163, LS160A, LS161A, LS162A, LS163A Counters Logic Products , 853-0531 81502 Signetics Logic Products Product Specification Counters 74160 , 74161, 74163, LS160A , can be used to enable the next cascaded stage (see Figure B). For conventional operation of 74160


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PDF LS160A, LS161A, LS162A, LS163A 74LS160A, 74LS162A) 74LS161 74LS163A) 54ls/74ls pin diagram of 74160 74160 function table pin diagram of 74163 74160 pin 74163 pin configuration 74ls161 counter pin configuration 74160 logic diagram of 74160 logic diagram 74160 74160 counter
74163 four bit binary counter

Abstract: LS162A 74163 pin configuration pin diagram of 74160 counter diagram 74161 pin diagram of 74163 162 bcd 74160 function table LS160A 74LS163A equivalent
Text: 1 1 U Oo O i D j TT 8 O LOGIC DIAGRAM , 74160 O3 Oj D, Dg s 8 O D3 - TC PE CEP , S ig n e tic s 74160 , 74161, 74163, LS160A, LS161A, LS162A, LS163A Counters Logic Products , conventional operation of 74160 , 74161 and 74163, the following transitions should be avoided. 1. 2 , December 4, 1985 5*285 Signetlcs Logic Products Product Specification Counters 74160 , 74161 , Counters 74160 , 74161, 74163, LS160A, LS161A, LS162A, LS163A LOGIC DIAGRAMS 'LS160A LD03030S


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PDF LS160A, LS161A, LS162A, LS163A 74LS160A, 74LS162A) 74LS161A, 74LS163A) 54LS/74LS S4LS/74LS 74163 four bit binary counter LS162A 74163 pin configuration pin diagram of 74160 counter diagram 74161 pin diagram of 74163 162 bcd 74160 function table LS160A 74LS163A equivalent
74160 pin layout

Abstract: am7416 IC 74160 DATA SHEET ic 74163 AM-7416 pin diagram of ic 74163 pin diagram of 74163 pins and their function in ic 74163 7416l data sheet IC 74161
Text: SN54J63W SN&4163X LOGIC SYMBOL VCC - P.n 16 GND " P-n 8 CONNECTION DIAGRAM Top View Vcc0,"T*jT- q . - , AmS4/74163 High-speed, look-ahead carry counter tor BCD |Am54/ 74160 Of Am54/74162) or binary (Am54 , Duration of tha Mi ort circuit tast tfiouM not axcaad on* mcckvJ. 6. içc to masaurad «vitti aU outputs , multiplanar*. DEFINITION OF FUNCTIONAL TERMS ICj, 2Cj Data Inputs. The four data inputs to each multiplexer ¡ = 0,1,2, and 3. 1Y,2Y Multiplexer Outputs. The output of each four-input multiplexer. A, B


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PDF 150ft Am74163 Am64153 74160 pin layout am7416 IC 74160 DATA SHEET ic 74163 AM-7416 pin diagram of ic 74163 pin diagram of 74163 pins and their function in ic 74163 7416l data sheet IC 74161
Truth Table 74160

Abstract: Truth Table 74161
Text: . The LOW -to-HIGH transition of SPE on the 54/74161 and 54/ 74160 should only occur w hile CP is high , to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite , (SEU) Immunity < 2 x 10"9 Errors/Bit-Day (Typ) level of reliability. The Harris HCTS160T is a , reset and look-ahead carry logic . Counting and parallel presetting are accomplished synchronously with the low-to-high transition of the clock. A low level on the synchronous parallel enable input, SPE


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PDF HCTS160T MIL-PRF-38535 100kRAD HCTS160T 1-800-4-HARRIS Truth Table 74160 Truth Table 74161
Truth Table 74160

Abstract: IC 74160 Truth Table 74161 IC 74161
Text: atellite A pplications FlowTM (SAF) is a tradem ark of Harris C orporation. HCTS160T Functional Diagram , transition of PE or TE on the 54/74161 and 54/ 74160 should only occur while CP is high for conventional operation. 3. The LOW -to-HIGH transition of SPE on the 54/74161 and 54/ 74160 should only occur w hile CP is , intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Harris HCTS160T is a Radiation Hardened High Speed Presettable


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PDF HCTS160T 100kRAD HCTS160T 1-800-4-HARR Truth Table 74160 IC 74160 Truth Table 74161 IC 74161
Truth Table 74161

Abstract: No abstract text available
Text: ark of Harris C orporation. HCTS160T Functional Diagram PO P1 P2 P3 TRUTH TABLE , HLLH for 160). 2. The H IG H-to-LO W transition of PE or TE on the 54/74161 and 54/ 74160 should only , devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large , - Single Event Upset (SEU) Immunity < 2 x 10"9 Errors/Bit-Day (Typ) level of reliability. The , features an asynchronous reset and look-ahead carry logic . Counting and parallel presetting are


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PDF HCTS160T MIL-PRF-38535 100kRAD HCTS160T 1-800-4-HARR Truth Table 74161
2002 - IC 74160

Abstract: Truth Table 74161 ic 74161 Truth Table 74160 IC 74160 decade counter diagram IC 74160 DATA SHEET logic diagram of 74160 data sheet IC 74161 HCTS160KTR IC 74160 decade counter
Text: . The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/ 74160 should only occur while CP is high for conventional operation. 3. The LOW-to-HIGH transition of SPE on the 54/74161 and 54/ 74160 should , standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HCTS160T is a Radiation Hardened , look-ahead carry logic . Counting and parallel presetting are accomplished synchronously with the


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PDF HCTS160T FN4626 MIL-PRF-38535 100kRAD HCTS160T IC 74160 Truth Table 74161 ic 74161 Truth Table 74160 IC 74160 decade counter diagram IC 74160 DATA SHEET logic diagram of 74160 data sheet IC 74161 HCTS160KTR IC 74160 decade counter
1999 - Truth Table 74160

Abstract: IC 74160 ic 74161 Truth Table 74161 IC 74160 DATA SHEET IC 74160 decade counter diagram data sheet IC 74161 74161 truth table HCTS160 HCTS160DTR
Text: trademark of Intersil Corporation. HCTS160T Functional Diagram P0 P1 3 P2 4 P3 5 6 , HLLH for 160). 2. The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/ 74160 should only , standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HCTS160T is a Radiation Hardened , look-ahead carry logic . Counting and parallel presetting are accomplished synchronously with the


Original
PDF HCTS160T MIL-PRF-38535 100kRAD HCTS160T Truth Table 74160 IC 74160 ic 74161 Truth Table 74161 IC 74160 DATA SHEET IC 74160 decade counter diagram data sheet IC 74161 74161 truth table HCTS160 HCTS160DTR
74160 pin layout

Abstract: No abstract text available
Text: achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic , HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/ 74160 should only occur while CP is high for conventional operation 3. The LOW-to-HIGH transition of SPE on the 54/74161 and 54/ 74160 should only occur , decade synchronous counter that features an asynchronous reset and look-ahead carry logic . Counting and parallel presetting are accomplished synchro nously with the iow-to-high transition of the clock. A low


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PDF HCTS160MS MIL-STD-1835 CDIP2-T16, 05A/cm2 74160 pin layout
Not Available

Abstract: No abstract text available
Text: device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS160MS is supplied , transition of SPE on the 54/74161 and 54/ 74160 should only occur while CP is high for conventional operation , counter that features an asynchronous reset and look-ahead carry logic . Counting and parallel presetting are accomplished synchro­ nously with the low-to-high transition of the clock. A low level on the , letterindicate the state of the referenced output prior to the LOW-to+IIGH clock transition _ /~ =


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PDF HCTS160MS MIL-STD-1835 CDIP2-T16,
IC 74160 decade counter diagram

Abstract: IC 74160 for decade counter 74163 four bit binary counter ND06 counter diagram 74161 pin diagram of ic 74163 CD74HC160 92C540
Text: High-Speed CMOS Logic FUNCTIONAL DIAGRAM PO PI P2 PÎ Presettable Counters C D 54/74H C /H C T160 CD54 , -37957RI Fig. 2 - Logic diagram fo r the CDS4/74HC/HC T161 and 163. MODE SELECT - FUNCTION TABLE, 160 , ). (b) The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/ 74160 should only occur while CP , devices are presettable synchronous counters that feature look ahead carry logic for use in high-speed , negative-to-positive transition of the clock. _ A low level on the synchronous parallel enable input, SPE, disables


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PDF CD54/74HC/HCT160, CD54/74HC/HCT161 CD54/74HC/HCT162, CD54/74HC/HCT163 54/74H CD54/74H CT161 IC 74160 decade counter diagram IC 74160 for decade counter 74163 four bit binary counter ND06 counter diagram 74161 pin diagram of ic 74163 CD74HC160 92C540
pin diagram of ic 74163

Abstract: CD74HCT160 CD74HC160 IC 74160 CD54HC160 74163 four bit binary counter AL207 C074HC16
Text: 160 V IICL-1'IUII Fig. 1 - Logic diagram lor the CD54/74HC/HCT160 and 162. 160,162 STATE DIAGRAM , TO 92CM-37957RI Fig. 2 - Logic diagram lor the CDS4/74HC/HCT161 arid 163. UJ M a; Cd of PE or TE on the 54/74161 and 54/ 74160 should , /HCT163 HARRIS SEMICOND SECTOR 27E D B 43G2271 0G17hl2 □■HAS High-Speed CMOS Logic t- FUNCTIONAL DIAGRAM po pi p2 p3 _ 5 spe 92CS-37958 Presettable Counters CD54/74HC/HCT160 BCD Decade Counter


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PDF CD54/74HC/HCT160, CD54/74HC/HCT161 CD54/74HC/HCT CD54/74HC/HCT163 43G2271 0G17hl2 92CS-37958 CD54/74HC/HCT160 CD54/74HC/HCT162 pin diagram of ic 74163 CD74HCT160 CD74HC160 IC 74160 CD54HC160 74163 four bit binary counter AL207 C074HC16
1999 - Truth Table 74160

Abstract: IC 74160 74161 pin diagram and truth table IC 74161 CDFP4-F16 HCTS160DMSR HCTS160HMSR HCTS160KMSR HCTS160MS
Text: LOW-to-HIGH transition of SPE on the 54/74161 and 54/ 74160 should only occur while CP is high for conventional , reset and look-ahead carry logic . Counting and parallel presetting are accomplished synchronously with the lowto-high transition of the clock. A low level on the synchronous parallel enable input, SPE , advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS160MS is supplied in a 16 lead Ceramic flatpack (K


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PDF HCTS160MS -55oC 125oC 05A/cm2 HCTS160 TA14445A. Truth Table 74160 IC 74160 74161 pin diagram and truth table IC 74161 CDFP4-F16 HCTS160DMSR HCTS160HMSR HCTS160KMSR HCTS160MS
Truth Table 74161

Abstract: 74161 pin diagram and truth table
Text: high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The H , . The LOW-to-HIGH transition of SPE on the 54/74161 and 54/ 74160 should only occur while CP is high for , presettable BCD decade synchronous counter that features an asynchronous reset and look-ahead carry logic . Counting and parallel presetting are accomplished synchronously with the lowto-high transition of the clock , Diagram PO P1 P2 P3 TRUTH TABLE INPUTS OPERATING MODE Reset (Clear) Parallel Load MR L H H Count


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PDF HCTS160MS MIL-STD-1835 CDIP2-T16 CTS160 HCTS160 TA14445A. Truth Table 74161 74161 pin diagram and truth table
Not Available

Abstract: No abstract text available
Text: 161 and HLLH for 160) 2. The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/ 74160 should , look-ahead carry logic . Counting and parallel presetting are accomplished synchronously with the lowto-high transition of the c lock. A low level on the synchronous parallel enable input, SPE, disables counting and , CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The H C T S 1 6 0 M S is s u p p lie d in a 16 lead C e ra m ic fla tp a


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PDF HCTS160MS 05A/cm HCTS160 isTA14445A.
CMOS 4000B series 4161

Abstract: timing diagram of 74160 74160 4-bit Decade Counter Asynchronous reset 74163 four bit binary counter logic diagram of 74160 pin diagram of 74163 4163B 4162B 4160B 4000B
Text: output capacitive load. 4160B 4Ì61B 4162B 4163B 4161B, 4163B LOGIC DIAGRAM (Clear is Synchronous for , structure. These counters are functionally equivalent to the 74160 - 74163 TTL counters. Two are , (4161, 4163). CONNECTION DIAGRAM (all packages) VDD C0 Q-j Q2 Q3 Q4 TE L I 16 15 14 13 12 11 10 9 , « Low level X » Don't care BLOCK DIAGRAM 7 O—— PE Ol —Ol4 10 O- TE 10— Clear Q2 , maximum rise and fall times of the clock input should be equal to or less than the transition times of


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PDF 4160B 4160B, 4162B) 4161B, 4163B) 4161B) 4162B, 10Vdc CMOS 4000B series 4161 timing diagram of 74160 74160 4-bit Decade Counter Asynchronous reset 74163 four bit binary counter logic diagram of 74160 pin diagram of 74163 4163B 4162B 4160B 4000B
IC 74160

Abstract: No abstract text available
Text: Input Logic Levels -VIL = 30% of VCC Max -VIH = 70% of VCC Min · Input Current Levels li < 5 ^ @ VOL , achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic , -to-HIGH transition of SPE on the 54/74161 and 54/ 74160 should only occur while CP is high for conventional , BCD decade synchronous counter that features an asynchronous reset and look-ahead carry logic . Counting and parallel presetting are accomplished synchronously with the lowto-high transition of the clock


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PDF HCS160MS IL-STD-1835 CDIP2-T16, IC 74160
Not Available

Abstract: No abstract text available
Text: . This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS160MS is , transition of PE orTE on the 54/74161 and 54/ 74160 should only occur while CP is high for conventional operation 3. The LOW-to-HIGH transition of SPE on the 54/74161 and 54/ 74160 should only occur while CP is , counter that features an asynchronous reset and look-ahead carry logic . Counting and parallel presetting are accomplished synchronously with the lowto-high transition of the clock. A low level on the


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PDF HCTS160MS 05A/cm2 HCTS160 TA14445A.
1999 - 74161 pin diagram and truth table

Abstract: IC 74160 Truth Table 74161 bcd 74160 74160 pin layout HCTS160DMSR CDFP4-F16 HCTS160MS HCTS160KMSR HCTS160HMSR
Text: LOW-to-HIGH transition of SPE on the 54/74161 and 54/ 74160 should only occur while CP is high for conventional , reset and look-ahead carry logic . Counting and parallel presetting are accomplished synchronously with the lowto-high transition of the clock. A low level on the synchronous parallel enable input, SPE , advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS160MS is supplied in a 16 lead Ceramic flatpack (K


Original
PDF HCTS160MS -55oC 125oC 05A/cm2 HCTS160 TA14445A. 74161 pin diagram and truth table IC 74160 Truth Table 74161 bcd 74160 74160 pin layout HCTS160DMSR CDFP4-F16 HCTS160MS HCTS160KMSR HCTS160HMSR
74160PC

Abstract: 74LS160 parallel counter 74LS160PC BCD Decade logic diagram 74160 74LS160D 74LS162 74LS160DC 74160 74LS162 parallel counter logic diagram of 74ls160
Text: state of a flip-flop, whether from the counting logic or the parallel entry logic if either mode is , 160 • 162 /m 0 " 54/ 74160 ^^4/74162 ^SYNCHRONOUS PRESETTABLE BCD DECADE COUNTERS yà , programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in , counting and parallel loading and allows all outputs to be simultaneously reset on the rising edge of the , LOADING • HIGH SPEED SYNCHRONOUS EXPANSION • TYPICAL COUNT RATE OF 35 MHz • LS VERSIONS FULLY


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PDF 54LS/74LS160 S4LS/74LS162 S4/74LS 02T30S2 74160PC 74LS160 parallel counter 74LS160PC BCD Decade logic diagram 74160 74LS160D 74LS162 74LS160DC 74160 74LS162 parallel counter logic diagram of 74ls160
Not Available

Abstract: No abstract text available
Text: ) 2. The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/ 74160 should only occur while CP is high for conventional operation 3. The LOW-tO'HIGH transition of SPE' on the 54/74161 and 54/ 74160 , asynchronous reset and look-ahead carry logic . Counting and parallel presetting are accomplished synchro­ nously with the low-to-high transition of the clock. A low level on the synchronous parallel enable , HCTS160MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of


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PDF M30S271 MIL-STD-1835 CDIP2-T16, 200K-or HCTS160MS 00441bfl 10sA/cm2
Supplyframe Tracking Pixel