The Datasheet Archive

lh543611 datasheet (11)

Part ECAD Model Manufacturer Description Type PDF
LH543611 LH543611 ECAD Model Sharp 512 x 36 x 2 - 1024 x 36 x 2 Synchronous Bidirectional FIFO Original PDF
LH543611M-15 LH543611M-15 ECAD Model Sharp 512 x 36 x 2 synchronous bidirectional FIFO Original PDF
LH543611M-20 LH543611M-20 ECAD Model Sharp 512 x 36 x 2 synchronous bidirectional FIFO Original PDF
LH543611M-25 LH543611M-25 ECAD Model Sharp 512 x 36 x 2 synchronous bidirectional FIFO Original PDF
LH543611M-30 LH543611M-30 ECAD Model Sharp 512 x 36 x 2 synchronous bidirectional FIFO Original PDF
LH543611M-35 LH543611M-35 ECAD Model Sharp 512 x 36 x 2 synchronous bidirectional FIFO Original PDF
LH543611P-15 LH543611P-15 ECAD Model Sharp 512 x 36 x 2 synchronous bidirectional FIFO Original PDF
LH543611P-20 LH543611P-20 ECAD Model Sharp 512 x 36 x 2 synchronous bidirectional FIFO Original PDF
LH543611P-25 LH543611P-25 ECAD Model Sharp 512 x 36 x 2 synchronous bidirectional FIFO Original PDF
LH543611P-30 LH543611P-30 ECAD Model Sharp 512 x 36 x 2 synchronous bidirectional FIFO Original PDF
LH543611P-35 LH543611P-35 ECAD Model Sharp 512 x 36 x 2 synchronous bidirectional FIFO Original PDF

lh543611 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
DNA 1001 DL

Abstract: DSB45 D-33A D35B 60 74
Text: LH543611 /21 512x36x2/1024x36 x2 Synchronous Bidirectional FIFO FEATURES • Pin-Compatible and , Setup and Flag Out Timing • Two 512 x 36-bit FIFO Buffers ( LH543611 ) or Two 1024 x 36-bit FIFO Buffers , DESCRIPTION The LH543611 and LH543621 contain two FIFO buffers, FIFO #1 and FIFO#2. These operate in parallel , as512or1024 by 36 bits. The LH543611 and LH543621 are ideal either for wide unidirectional applications or for bidirectional data applications; component count and board area are reduced. The LH543611 and LH543621 have two


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PDF LH543611/21 512x36x2/1024x36 LH5420 LH543601, 36-bit LH543611) LH543621) 36/18/9-bit DNA 1001 DL DSB45 D-33A D35B 60 74
Not Available

Abstract: No abstract text available
Text: FIFO FUNCTIONAL DESCRIPTION The LH543611 and LH543621 contain two FIFO buff ers, FIFO #1 and FIFO #2. , #2 each are organized as 512 or 1024 by 36 bits. The LH543611 and LH543621 are ideal either for wide , . The LH543611 and LH543621 have two 36-bit ports, Port A and Port B. Each port has its own port-synchro , the minimum pulse-width conditions for clock-HIGH and clock-LOW remain satis fied; the LH543611 and , initialized to eight locations from the respective FIFO boundaries at reset. Adata block of 512 ( LH543611 ) or


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PDF 512x36x2/1024x36x2 LH543611 LH543621 36-bit risi/21 144-pin,
Not Available

Abstract: No abstract text available
Text: ADVANCE INFORMATION LH543611 /21 FEATURES · Fast Cycle Times: 20/25/30/35 ns · Pin-Compatible , 0 2 4 x 3 6 x 2 Synchronous Bidirectional FIFO FUNCTIONAL DESCRIPTION The LH543611 /21 contains , bidirectional data buffering. FIFO #1 and FIFO #2 each are organized as 512/1024 by 36 bits. The LH543611 /21 is , count and board area are reduced. The LH543611 /21 has two 36-bit ports, Port A and Port B. Each port has , single-byte field for parity checking. A reset operation initializes the LH543611 /21 Control Register for


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PDF LH543611/21 LH5420 LH543601 36-bit 36/18/9-bit 9/18-Bit
1995 - D35B 60 74

Abstract: D35B 60 D33A D26A D28B D35B D31A LH5420 D26B LH543621
Text: ADVANCE INFORMATION LH543611 /21 512 × 36 × 2 / 1024 × 36 × 2 Synchronous Bidirectional FIFO , * The LH543611 /21 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in , by 36 bits. The LH543611 /21 is ideal either for wide unidirectional applications or for bidirectional data applications; component count and board area are reduced. * The LH543611 /21 has two 36 , initializes the LH543611 /21 Control Register for LH5420/LH543601compatible operation, but it may be


Original
PDF LH543611/21 LH5420 LH543601 36-bit 36/18/9-bit LH5420/LH543601 D35B 60 74 D35B 60 D33A D26A D28B D35B D31A D26B LH543621
1995 - D35B

Abstract: D35B 60 pqfp132 TEF 2421 TQFP 144 PACKAGE D26B D35A
Text: representative for availability Example: LH543611P-20 (512 x 36 x 2 Bidirectional FIFO, 20 ns, 132-pin, Plastic , 512 & 1024 × 36 × 2 BiFIFOs LH543611 /21 TIMING DIAGRAMS t RS RS t RSS t RSH t RSS , 2 BiFIFOs LH543611 /21 TIMING DIAGRAMS (cont'd) RS t RSS t RSH CKA tRWS t RWH , Page 24 512 & 1024 × 36 × 2 BiFIFOs LH543611 /21 TIMING DIAGRAMS (cont'd) READ FROM FIFO #2 , 13. Port A FIFO Read/Write Page 25 512 & 1024 × 36 × 2 BiFIFOs LH543611 /21 TIMING DIAGRAMS


Original
PDF LH543611/21 J63428 SMT95017 D35B D35B 60 pqfp132 TEF 2421 TQFP 144 PACKAGE D26B D35A
D35B 60

Abstract: D35B D35B 60 74 D35B 60 89 D35B 80 D26A LH543621 LH543611 LH543601 LH5420
Text: LH543611 /21 512 × 36 × 2 / 1024 × 36 × 2 Synchronous Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION · Pin-Compatible and Functionally The LH543611 and LH543621 contain two FIFO , data buffering. FIFO #1 and FIFO #2 each are organized as 512 or 1024 by 36 bits. The LH543611 and , Setup and Flag Out Timing Two 512 × 36-bit FIFO Buffers ( LH543611 ) or Two 1024 × 36-bit FIFO Buffers , LH543611 and LH543621 have two 36-bit ports, Port A and Port B. Each port has its own port-synchronous


Original
PDF LH543611/21 LH543611 LH543621 LH5420 LH543601, 144-pin, TQFP144-P-2020) 132-pin, D35B 60 D35B D35B 60 74 D35B 60 89 D35B 80 D26A LH543601
1996 - D35B

Abstract: D35B 60 D35A LH5420 D15A D12A D11A FIFO error reset full empty diode A1A 115 16 D35B 60 89
Text: LH543611 /21 512 × 36 × 2 / 1024 × 36 × 2 Synchronous Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION · Pin-Compatible and Functionally The LH543611 and LH543621 contain two FIFO , data buffering. FIFO #1 and FIFO #2 each are organized as 512 or 1024 by 36 bits. The LH543611 and , Setup and Flag Out Timing Two 512 × 36-bit FIFO Buffers ( LH543611 ) or Two 1024 × 36-bit FIFO Buffers , PGA Package Conversion * The LH543611 and LH543621 have two 36-bit ports, Port A and Port B. Each


Original
PDF LH543611/21 LH543611 LH543621 LH5420 LH543601, LH5420/LH543601 LH543611/21 D35B D35B 60 D35A D15A D12A D11A FIFO error reset full empty diode A1A 115 16 D35B 60 89
L2735

Abstract: D-34A i-box
Text: LH543611 /21 FEATURES · Pin-Compatible and Functionally Upwards-Compatible with Sharp LH5420 and , /1024x36x2 Synchronous Bidirectional FIFO FUNCTIONAL DESCRIPTION The LH543611 and LH543621 contain two FIFO , data buffering. FIFO#1 and FIFO #2 each are organized as 512 or 1024 by 36 bits. The LH543611 and , ; component count and board area are reduced. The LH543611 and LH543621 have two 36-bit ports, Port A and Port , clock-LOW remain satis fied; the LH543611 and LH543621 arefully-static parts. Conceptually, the port clocks


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PDF LH543611/21 LH5420 LH543601, 512x36x2/1024x36x2 LH543611 LH543621 L2735 D-34A i-box
D2SB 73

Abstract: No abstract text available
Text: -Lead, Pin-Grid-Array Package (PGA120-C-S1360) f 256 x 36 x 2/512 x 36 x 2 Bidirectional FIFO Example: LH543611P-20 , format for flag-programming words for the LH543611. Also, Table 4a defines the meaning of each of the , lists the same definitions for the LH543611. WARNING: Control inputs which may affect the compu tation , locations from the respective FIFO boundaries at reset. A data block of 256 (LH543601) or 512 ( LH543611 ) or , vidually, through one of four eight-bit (LH543601) or ninebit ( LH543611 ) status words. Table 3a


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PDF LH5420 36-bi1/512x 36-bit 18/9-bit LH543601/11 132-Lead, PQFP132-P-S950) 120-Lead, PGA120-C-S1360) D2SB 73
U24A

Abstract: No abstract text available
Text: (PGA120-C-S1360) - 256 x 36 x 2/512 x 36 x 2 Bidirectional FIFO Example: LH543611P-20 (512 x 36 x 2 , flag-programming words for the LH543611. Also, Table 4a defines the meaning of each of the five flags, both the , for the LH543611. Mailbox Operation Two mailbox registers are provided for passing system hardware or , respective FIFO boundaries at reset. Adata block of 256 (LH543601) or 512 ( LH543611 ) or fewer words may be , , through one of four eight-bit (LH543601) or ninebit ( LH543611 ) status words. Table 3a illustrates the data


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PDF LH543601/11 LH5420 36-bit/512 36-bit 36/18/9-bit LH543601/11 132-Lead, PQFP132-P-S950) 120-Lead, U24A
n 18k U

Abstract: 132-QFP
Text: LH543611 LH543621 36k 1k x 36 - 72k 18k Bidirectional 4k x 18 256 x 36 x 2 -512x36x2 36k 72k , -30 LH543611M /P-18 LH543611M /P-20 5 12 x 36 x 2 LH543611M /P-25 r LH543611M /P-30 LH543611M /P-35 LH540205D


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PDF LH5481 LH5491 512x9 LH5496 LH540202 LH540203 LH540204 LH540205 LH540215 LH540225 n 18k U 132-QFP
IR3Y29B

Abstract: ir3y26a1 IR4N IR3T24N IR3Y08 li3301 ir2c05 IR3C08N ir2c53 IR2E02
Text: LH540225 LH540235 LH540245 LH543601 LH543611 LH543620 LH543621 LH5481 LH5491 LH5496 25 25.26 25.26 25.26 25


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PDF ARM710 ARM810 IR3T24 IR3T24N IR3Y05Y IR3Y08 IR3Y12B IR3Y18A IR3Y21 IR3Y26A IR3Y29B ir3y26a1 IR4N IR3T24N li3301 ir2c05 IR3C08N ir2c53 IR2E02
IR2E27A

Abstract: IR2E02 IR2C53 IR2E31A IR2E10 IR2E27 IR3N34 IR2E01 IR2C07 ir2e31
Text: LH543611 LH543620 LH543621 LH5481 LH5491 LH5496 LH590436 LH590836 LH5P1632 LH5P8128 LH5P8129 LH5P832


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PDF Core28 IR2C24A/AN IR2C26 IR2C30/N IR2C32 IR2C33 IR2C34 IR2C36 IR2C38/N IR2C43 IR2E27A IR2E02 IR2C53 IR2E31A IR2E10 IR2E27 IR3N34 IR2E01 IR2C07 ir2e31
D35B

Abstract: D35B 60 D35B 60 74 D20A D22A
Text: ADVANCE INFORMATION LH54V3611/21 FEATURES · Upwards-Compatible with Sharp LH543611 /21 · Cycle Time as fast as 15 ns · Two 512 × 36-bit FIFO Buffers (LH54V3611) or · · · · · · · · · · · · · · · Two 1024 × 36-bit FIFO Buffers (LH54V3621) Selectable 36/18/9-bit Word Width on Port B; Selection May be Changed Without Reset Programmable Byte-Order Reversal ­ `Big-Endian , : WS[1:0]= 2 (HL) LH543611 /21 Bus Example: IBM, Motorola, etc. INPUT DB0 CKA 2 3


Original
PDF LH54V3611/21 LH543611/21 36-bit LH54V3611) LH54V3621) 36/18/9-bit 144TQFP 144-pin D35B D35B 60 D35B 60 74 D20A D22A
aei cr

Abstract: a04l
Text: ADVANCE INFORMATION LH54V3611/21 FEATURES · Upwards-Compatible with Sharp LH543611 /21 · Cycle Time as fast as 15 ns · Two 512 x 36-bit FIFO Buffers (LH54V3611) or Two 1024 x 36-bit FIFO Buffers (LH54V3621) · Selectable 36/18/9-bit Word Width on Port B; Selection May be Changed Without Reset · Programmable Byte-Order Reversal `Big-Endian 0 Little-Endian Conversion' · Independent Clocks for Both Ports · Clock Enable Control at Each Port · Synchronous Request/Acknowledge `Handshake' · Programmable


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PDF LH54V3611/21 LH543611/21 36-bit LH54V3611) LH54V3621) 36/18/9-bit Almost-Full611/21 144-pin aei cr a04l
20M32

Abstract: u1520
Text: -20/25/35 LH540235M/U*20/25/35 LH543620P-20/25/30 LH543611M /P-18/20/25/30/35 LH540205D-20/25/35 LH540245M


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PDF 280sk orx16 x8/x16 ID244DXX ID244Exx ID244Gxx ID244Hxx ID244KXX 20M32 u1520
ak25

Abstract: 20U20
Text: 20 25 30 18 1k x 36 36k LH543C20P-25 LH543620P-30 LH543611M /P-18 LH543611M /P-20 LH5436riM /P-25 LH543611M /P-30 LH543611M /P-35 LH540205D-20 1X540205D-25 LH5402050-35 LH540245MAI-20 ! *LH540245M /U-25 j


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PDF LH5481D/U-25 LH5481D/U-35 LH5491D/U-25 LH5491D/U-35 LH5496/D/U-20 LH5496/D/U-35 LHS496/D/U-50 LH540201AD/AN/AK/AU-10 LH590436M-20 LH59043-6M-25 ak25 20U20
LM24P20

Abstract: LQ070T5BG01 LM162KS1 BSCR86L00 LM5Q31 IR2C07 IR3Y29B lq6bw BSCU86L60 lq6bw506
Text: -20/25/35. 10 LH543601P-20/25/30/35 .10 LH543611M /P-18/20/25/ 30/35.10


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PDF 109-n GL1PR112. GL1PR135. GL1PR136. GL1PR211. GL1PR212. GL3KG63. GL3P201. GL3P202. GL3P305. LM24P20 LQ070T5BG01 LM162KS1 BSCR86L00 LM5Q31 IR2C07 IR3Y29B lq6bw BSCU86L60 lq6bw506
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