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JTAGJET-XSCALE IAR Systems JTAG EMULATOR PXA25X/270&IXP4XX
JTAGJET-ARM IAR Systems JTAG EMULATOR FOR ARM7/ARM9
JTAGJET-CORTEXM3 IAR Systems JTAG EMULATOR FOR CORTEX-M3
JTAGJET-TRACE-2M IAR Systems JTAG EMULATOR W/2M TRACE BUFFER
JTAGJET-TRACE-1M IAR Systems JTAG EMULATOR W/1M TRACE BUFFER
JTAGJET-TRACE-256K IAR Systems JTAG EMULATOR ARM7/9/CORTEX-M3

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2004 - EE-68

Abstract:
Text: /processors Analog Devices JTAG Emulation Technical Reference Contributed by David M. Doyle Introduction This document provides technical information to properly design a JTAG emulator interface for , Signal Processors (DSPs). ADI designs, manufactures, and sells several different types of JTAG emulators for use with ADI DSP targets supporting an embedded JTAG emulator port. This document has been , continuing with this document. Most questions addressed by users regarding differences with our JTAG


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PDF EE-68 EE-68) EE-68 JTAG series termination resistors BTMS DSP JTAG JTAG header jtag 14 IDT5T9050 IDT49FCT805 IDT49FCT3805E 74AVC16244
2004 - DSP JTAG

Abstract:
Text: technical support. Analog Devices JTAG Emulation Technical Reference Contributed by David M. Doyle , design a JTAG emulator interface for Analog Devices, Inc. (ADI) processor targets, which are all , ( JTAG ) standard, see Appendix E: Introduction to IEEE Std. 1149.1 ( JTAG ) Boundary Scan. ADI designs, manufactures, and sells several different types of JTAG emulators for use with ADI DSP targets supporting an embedded JTAG emulator port. This document has been revised to only support the current line of ADI


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PDF EE-68 EE-68) DSP JTAG JTAG series termination resistors TRST 74AVC16244 JTAG header JTAG IDT5T9050 IDT49FCT805 IDT49FCT3805E EE-68
GS8640Z36

Abstract:
Text: SRAMs 144Mb SigmaQuad-II+ Package GSI P/N Config Speed ( MHz ) Voltage Features Avail , Speed ( MHz ) Voltage 165 BGA GS81302D36yy-### GS81302D18yy-### GS81302D09yy-### GS81302D08yy , Speed ( MHz ) Voltage 165 BGA GS8662D37Ayy-### GS8662D19Ayy-### 2M x 36 4M x 18 400, 375, 333, 300 1.8 V 72Mb SigmaQuad-II Package GSI P/N Config Speed ( MHz ) Voltage 165 BGA , Speed ( MHz ) Voltage Features Avail. 165 BGA GS8342D36Ayy-### GS8342D18Ayy


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PDF 144Mb GS81302D37yy-# GS81302D19yy-# GS81302D36yy-# GS81302D18yy-# GS81302D09yy-# GS81302D08yy-# GS8640Z36 GS840Z18A GS816032 GS8342T36 GS8662Q18
1996 - JTAG-102

Abstract:
Text: AP-630 APPLICATION NOTE Designing for On-Board Programming Using the IEEE 1149.1 ( JTAG , .5 2.0 WHAT IS JTAG ? .5 3.0 WHY USE THE JTAG TAP TO PROGRAM FLASH 4.0 JTAG PROGRAMMING PERFORMANCE , .12 APPENDIX A JTAG VENDOR REFERENCES


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PDF AP-630 JTAG-102, JTAG-102 jtag sequence AP-630 intel HANDBOOK INTEL FLASH MEMORY DATA SHEET INTEL DX2 INTEL application notes Intel AP flash memory databook pcb sms controller
msi motherboard circuit diagram

Abstract:
Text: frequency is 6.25 MHz . JTAGCLK Mod 50% duty cycle Clock used to clock Mbus module JTAG circuitry. Maximum frequency is 6.25 MHz . JTAGDI JTAG Scan data input into scan ring. Signal Descriptions 3-1 530 , Status Register Scan Ring Addresses JTAG Control Circuitry JTAG Clock Generation System Reset Signals , con tains the JTAG circuitry and glue logic needed on the SparKIT-40/SS10 motherboard. Each component , 0.5-ns skew at the chip boundary. Contains the IEEE P. 1149 JTAG standard master control circuitry


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PDF 5304A04 53D4AD4 01313A L64863 SparKIT-40/SS D-102 msi motherboard circuit diagram MSI MOTHERBOARD schematic diagram MSI MOTHERBOARD SERVICE MANUAL amd MOTHERBOARD SERVICE MANUAL circuit diagram of msi motherboard L64811 MOTHERBOARD msi CIRCUIT diagram MSI motherboard intel D102 motherboard
1996 - JTAG-102

Abstract:
Text: AP-630 APPLICATION NOTE Designing for On-Board Programming Using the IEEE 1149.1 ( JTAG , .5 2.0 WHAT IS JTAG ? .5 3.0 WHY USE THE JTAG TAP TO PROGRAM FLASH 4.0 JTAG PROGRAMMING PERFORMANCE , .12 APPENDIX A JTAG VENDOR REFERENCES


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PDF AP-630 JTAG-102, JTAG-102 JTAG Example 7.0 Needhams Electronics
2004 - 74AC14

Abstract:
Text: , at a frequency of up to 16 MHz . It generates the clocks for the CPU and for the on-chip peripherals , ) Range 4 MHz [15625 Hz, 70 MHz ] 8 MHz [31250 Hz, 70 MHz ] 16 MHz [62500 Hz, 70MHz] 5 , frequency of 48 MHz . This clock must be provided by an external oscillator connected to the USB clock pin USBCLK or generated by the internal PLL2, multiplying by 12 an external reference at a speed of 4 MHz , either 48 MHz or 4Mhz is required as shown in the figure below: Figure 7. USB Clock management 4 MHz


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PDF AN1775 STR71x AN1775/0404 74AC14 74AC14 application notes AN1775 HE10 MAX6315
1996 - jtag mhz

Abstract:
Text: E AP-630 APPLICATION NOTE Designing for On-Board Programming Using the IEEE 1149.1 ( JTAG , .5 2.0 WHAT IS JTAG ? .5 3.0 WHY USE THE JTAG TAP TO PROGRAM FLASH MEMORY? .7 4.0 JTAG PROGRAMMING PERFORMANCE , .12 APPENDIX A JTAG VENDOR REFERENCES


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PDF AP-630 JTAG-102, jtag mhz tsop sensors JTAG CONNECTOR JTAG algorithm jtag 14 Intel+486+DX2 intel microcontroller handbook INTEL DX2 flash memory databook corelis JTAG CONNECTOR
2007 - XAPP424

Abstract:
Text: RUNTEST parameters for JTAG clock frequencies greater than 1 Mhz . The SVF instruction, RUNTEST, is used , when generating the SVF file. In systems with a JTAG TCK frequency slower than 1 MHz , this is not an , some devices. If the actual JTAG clock frequency is faster than 1 Mhz , the SVF2ACE utility can scale , Application Note: All Families R Embedded JTAG ACE Player Author: Roy White, and Arthur Khu , provided software utilities, and update the remote system through the JTAG interface using the Embedded


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PDF XAPP424 XAPP424 SSYA002C XAPP412 XAPP502 X424 XAPP058 XAPP500 XAPP503 XAPP693
2007 - ACE FLASH

Abstract:
Text: Mhz . The SVF instruction, RUNTEST, is used to insert wait states in the JTAG system and is necessary , Application Note: All Families R Embedded JTAG ACE Player Author: Roy White, and Arthur Khu , provided software utilities, and update the remote system through the JTAG interface using the Embedded JTAG ACE Player. Included Design Files Included with this application note are source files , . Introduction Xilinx FPGA, CPLD, and PROM families incorporate industry standard IEEE 1149.1 JTAG support


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PDF XAPP424 ACE FLASH XAPP502 X424 XAPP058 XAPP412 XAPP424 XAPP500 XAPP503 XAPP693
TQFP 100 PACKAGE footprint

Abstract:
Text: JTAG , IEEE 1149.1 BGA Package 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 , speed up to 250 MHz · Data rates up to 500 Mbps/pin with user selectable double data rate interface · Port-selectable I/O voltage levels and bus-width · BGA packaging, plus JTAG ¥ ¥ 7HUD6\QF 7KH ,QGXVWU\·V , Packaging plus JTAG 4 TeraSync FIFOs Product Table TeraSync FIFOs Product Table TeraSync DDR , 3.3/2.5/1.8/1.5 225 MHz 324-BGA 32Kx72 2M 72T7295 2.5 3.3/2.5/1.8/1.5 225 MHz 324


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PDF
2006 - Not Available

Abstract:
Text: during normal operation. • • • • • • Internal non-volatile EEPROM JTAG and FAST mode I2C serial interfaces Input Frequency Ranges: 1 MHz to 400 MHz Output Frequency Ranges: 4.9 kHz to 500 MHz Reference Crystal Input with programmable oscillator gain and programmable linear load capacitance – Crystal Frequency Range: 8 MHz to 50 MHz • Each PLL has an 8-bit pre-scaler and a 12-bit The IDT5V9885C can be programmed through the use of the I2C or JTAG interfaces. The programming


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PDF IDT5V9885C IDT5V9885C
1997 - STP2016

Abstract:
Text: clock motherboard JTAG circuitry. Maximum frequency is 6.25 MHz . JTagClkMod Output Mod50% duty cycle Clock used to clock MBus module JTAG circuitry. Maximum frequency is 6.25 MHz . JTAG_DI , ), operating at either 40 or 50 MHz with a 64-bit wide data path. The SBus is a multi-master bus primarily intended for I/O transactions with operation between 16 and 25 MHz . The STP2016 generates the 40/50 MHz MBus clock signal by dividing the inputs from a 80/100 MHz crystal oscillator by two. The 20/25 SBus


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PDF STP2016 STP2016 64-bit PQFP100 100-Pin STP2016QFP mbus 10 application SuperSPARC STP2011 mbus MCLK11 MOSC STP2012 STP2016QFP
Not Available

Abstract:
Text: | Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview The Joint Test Action Group ( JTAG )-HS2 , VIO GND TCK TMS JTAG-HS2 FPGA 1 2 3 4 5 6 Digilent JTAG Header Single row, 100 , HS2 The JTAG bus can be shared with other devices as systems hold JTAG signals at highimpedance , , complete, all-in-one JTAG programming solution for Xilinx FPGAs  Compatible with all Xilinx tools  Compatible with IEEE 1149.7-2009 Class T0 Class T4 (includes 2-Wire JTAG )  Separate Vref drives JTAG /SPI


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PDF 100-mil 100-mil, 30MHz 30MHz, 15MHz, 10MHz,
2010 - GS8673EQ

Abstract:
Text: SRAMs 72Mb SigmaQuad-IIIe+ Config GS8673ED37Ayy-### GS8673ED19Ayy-### Speed ( MHz ) 714/675 , x 36 4M x 18 GS8673ED36Ayy-### GS8673ED18Ayy-### Speed ( MHz ) -600 (600/450) -550 (550/400 , + SRAMs 144Mb SigmaQuad-II+ GSI P/N Config Speed ( MHz ) Voltage GS81302D38yy , /N GS81302D36yy-### GS81302D18yy-### GS81302D09yy-### GS81302D08yy-### Config Speed ( MHz , GS81302Q36yy-### GS81302Q18yy-### GS81302Q09yy-### GS81302Q08yy-### Config Speed ( MHz ) Voltage


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PDF GS8673ED37Ayy-# GS8673ED19Ayy-# GS8673EQ37Ayy-# GS8673EQ19Ayy-# GS8673EQ SIGMA SigmaQuad-IIIe GS8673ED36 GS8673ET GS8673ED18 GS8662Q18 GS8322Z36 GS818 GS8171DW
STP2012

Abstract:
Text: to clock motherboard JTAG circuitry. Maxim um frequency is 6.25 MHz . M od50% duty cycle C lock used to clock MBus m odule JTAG circuitry. Maximum frequency is 6.25 MHz . JTAG Scan data input into scan , MBus is designed for multiprocessing (MP), operating at either 40 or 50 MHz with a 64-bit wide data , and 25 MHz . The STP2016 generates the 40/50 MHz MBus clock signal by dividing the inputs from a 80/100 MHz crystal oscillator by two. The 20/25 SBus clock signal is derived in the same manner from the MBus


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PDF STP2016 STP2016 64-bit 100-Pin STP2016Q STP2012 STP2016QFP SuperSPARC
2001 - SB21150BC

Abstract:
Text: of Section 3, "Setup Violations of 66 MHz PCI Control Signals on the 21150" on page 11. · · · , (Tval) and Input Hold Timer from CLK (Th) Violations of 66 MHz PCI Signals on the 21150" on page 10 , : descriptions of two signals when bus speed is set for 66 MHz . 5/5/00 005 PBGA added, trst_l updates , circuit errata. 9/1/99 003 Added documentation change item 3 for 66 MHz operation. Updated Hold , Using the 66 MHz 21150 as an AGP - PCI Bridge White Paper 278214-001 21150 PCI-to-PCI Bridge


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PDF m66ena: SB21150BC SB21150AC GD21150BC dc1111d SB21150 DC1030G 74ls166 GD21150AC SB21150-AC 21150-AC
2005 - MCP430

Abstract:
Text: support · JTAG clock operation up to 50 MHz The JTAG clock frequency is dependent on the delay , tolerant in all ranges · Multiprocessor support · JTAG clock operation of 10 MHz viii HPUSB, USB , up to 50 MHz , while USB-ICE supports a JTAG clock operation of 10 MHz . There is a relationship , . JTAG Frequency Selection Field Dialog Field Description Select frequency ( MHz ) Selects the , . 1-5 JTAG Frequency Selection . 1-6


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PDF MSP430 MSP430 MCP430 EE-68 MS430 MSP430-ICE
2006 - differences between ARM7 and ARM9

Abstract:
Text: recognition Maximum JTAG speed 12 MHz Download speed up to 600 Kbytes/second * DCC speed up to 800 Kbytes , (SDK) available * = Measured with J-Link Rev.5, ARM7 @ 50 MHz , 12MHz JTAG speed. 1.3 J-Trace , thumb mode Automatic core recognition Maximum JTAG speed 12 MHz Download speed up to 420 Kbytes , from IAR C-SPY debugger. * = Measured with J-Trace, ARM7 @ 50 MHz , 12MHz JTAG speed. 1.3.2 , speeds up to 1/6 of the CPU speed. JTAG speeds of more than 10 MHz are not recommended. 2.5.2


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TMS320C67XX

Abstract:
Text: 2.6W x 1.2H 5.6L x 2.6W x 1.2H Max. JTAG / CPU Clock 30 MHz / no limit 30 MHz / no limit , small, universal In-Circuit Debugger that connects to targets via a JTAG port. It is equipped with USB , Instruments DSP, ARM7, ARM9, ARM11 and Cortex based devices. Optional, fully isolated JTAG probe Active JTAG probes to support the TI-14, cTI-20, ARM-20, ARM14, Mictor-38 and Cortex pin debug headers , MHz maximum CPU speed) Supports all ARM7, ARM9, OMAP and DM devices equipped with the Embedded Trace


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PDF TMS470, C6000, C5000 C2000 XDS510 XDS560 TMS470 TMS320 JTAGjet-470 TMS320C67XX TMS320F24x omap1710 JTAGjet DM331 ARM processor cortex R4 TMS320C64xx OMAP750 arm9 pinout JTAGjet-570
2007 - STR75x

Abstract:
Text: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 JTAG , 5.2 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , Clock overview Figure 6. Clock overview PLL 1-10 MHz UP TO 64 MHz FREEOSC 4MHz PLL 48 MHz CKD FLAG XT1 XT2 CK_SYS OSC4M AHB & APB DIVIDERS HCLK UP TO 64MHz PCLK UP , 32kHz CK_USB 48 MHz RTC ALARM WAKEUP 300kHz USB_CK For further details see the


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PDF AN2419 STR75x p031 STM1818TWX7F STM1818 STM1813LWX7F STM1813 pc motherboard schematics OSC4M OSC32K mrc-C
2000 - XCR5064C

Abstract:
Text: (ISP) using a JTAG interface - On-chip supervoltage generation - ISP commands include: Enable, Erase, Program, Verify - Supported by multiple ISP programming platforms - Four pin JTAG interface (TCK, TMS, TDI, TDO) - JTAG commands include: Bypass, Idcode Support for complex asynchronous clocking , industry-standard, IEEE 1149.1, JTAG interface through which In-System Programming (ISP) and reprogramming of the , 60 80 100 120 140 160 180 200 FREQUENCY ( MHz ) SP00663 Figure 5: ICC vs


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PDF com/partinfo/notify/pdn0007 XCR5064C: DS044 44-pin VQ100: 100-pin XCR5064C VQ100 XCR5064C MC16 XCR5084C
2008 - Parallel Flash Loader

Abstract:
Text: 3. JTAG and In-System Programmability MII51003-1.6 Introduction This chapter discusses how , the following sections: "IEEE Std. 1149.1 ( JTAG ) Boundary-Scan Support" on page 3­1 "In System Programmability" on page 3­4 IEEE Std. 1149.1 ( JTAG ) Boundary-Scan Support All MAX® II devices provide Joint Test Action Group ( JTAG ) boundary-scan test (BST) circuitry that complies with the IEEE Std. 1149.1-2001 specification. JTAG boundaryscan testing can only be performed at any time after VCCINT and all


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PDF MII51003-1 Parallel Flash Loader ieee 1532 EPM1270 ieee 1532 ISP EPM570 EPM240Z EPM240G EPM240 EPM2210 stapl
1998 - Not Available

Abstract:
Text: 15dB 15dB 70 MHz BPF AD6640 AD6620 AD6620 DSP DSP DSP DSP DSP Local Oscillator AD6620 , 200 MHz IF CH. A AD6600 AD6630 200 MHz IF CH. B AD6620 DSP a digital - 5 Wideband , Output Format Serial or Parallel Outputs Complex NCO Phase Sync JTAG MicroPort a , Complex Phase Sync NCO JTAG MicroPort · High Data Rate ­ Single Real Channel at 65 MSPS ­ Dual , CH · fSAMP, (up to 65 MHz ) · Direct Interface to High Performance ADCs ­ 16 Linear Bits (Standard


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PDF AD6640 AD6620 AD6620 AD6640
divmode

Abstract:
Text: . Syncln Input Synchronization clock input. Input of synchronization clock. JTDI Input JTAG data input. Input of JTAG serial data. 7 NEC Pin Name JTDO I/O ¿iPD30200, 30210 Function JTAG data output. Output of JTAG serial data. Output JTMS Input JTAG command. Indicates that input serial data is command data. JTCK Input JTAG clock input. Input of JTAG serial clock. If the JTAG interface is not used, set it to low level. DivMode Input Mode setting. Sets frequency


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PDF uPD30200 uPD30210 32-bit divmode
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