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ARM SecurCore SC100

Abstract: jazelle ARM7EJ-S ARM10E ARM11 arm1136 ARM920T ARM11 intel ARM1026 ARM SC100
Text: TCM AHB Thumb DSP Jazelle MMU ARM9 Cache TCM / ARM920T 16K/16K MMU AHB Thumb DSP Jazelle , AHB AHB AHB Thumb DSP Jazelle AHB ARM10E , MMU AHB MMU AHB MMU+M MU AHB Thumb DSP Jazelle , DSP Jazelle MMU 64 AHB 64 AHB MMU SIMD


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PDF ARM10E, ARM11 ARM720T ARM920T 16K/16K ARM922T ARM940T ARM926EJ- 4-128K/4MMU ARM946E- ARM SecurCore SC100 jazelle ARM7EJ-S ARM10E ARM11 arm1136 ARM11 intel ARM1026 ARM SC100
2005 - jazelle

Abstract: ARM926EJ-S ARM926EJ CP15 ARM926EJ-STM
Text: Features · ARM9EJ-S Based on ARM® Architecture v5TEJ with Jazelle ® Technology · Three Instruction Sets · · · · · · · · · ­ ARM® High-performance 32-bit Instruction Set ­ Thumb® High Code Density 16-bit Instruction Set ­ Jazelle ® 8-bit Instruction Set 5-Stage Pipeline Architecture when Jazelle is not Used ­ Fetch (F) ­ Decode (D) ­ Execute (E) ­ Memory (M) ­ Writeback (W) 6-Stage Pipeline when Jazelle is Used ­ Fetch ­ Jazelle /Decode (Two Cycles) ­ Execute ­ Memory


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PDF 32-bit 16-bit 6128AS 11-Apr-05 jazelle ARM926EJ-S ARM926EJ CP15 ARM926EJ-STM
2002 - ARMv5TEJ

Abstract: jazelle ARM1026EJ-S ARM720T ARM920T ARM922T ARM926EJ-S
Text: RISC core has extensive 64-bit bussing, and includes JazelleTM technology from ARM for Java , . ARM1026EJ-S, Jazelle , AMBA, EmbeddedICE-RT, ARM720T, ARM920T, ARM922T, ARM926EJ-S and Thumb are trademarks , Corporation. All rights reserved. 303.A.SR.W - Printed in USA Jazelle Technology. ARM's Jazelle , Java Virtual Machine (JVM). The Jazelle technology-enabled core uses 87% less energy per CaffieneMark


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PDF ARM1026EJ-STM ARM1026EJ-STM ARM1026EJ-S 32bit 64-bit ARMv5TEJ jazelle ARM720T ARM920T ARM922T ARM926EJ-S
2002 - ARMv5TEJ

Abstract: ARM7EJ-S ARMv5T jazelle ARMv5 ARM processors LSI coreware library
Text: core includes JazelleTM technology from ARM® for Java acceleration and also an enhanced 16 x 32 , -bit arithmetic capabilities, providing improved performance and flexibility. JazelleTM Technology ARM's Jazelle technology provides Java acceleration to deliver significantly higher performance than a softwarebased Java Virtual Machine (JVM). The Jazelle technology-enabled core uses 87% less energy per , Corporation. ARM and Thumb are registered trademarks of ARM Limited. ARM7EJ-S, Jazelle , AMBA and ARM7TDMI


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PDF 32-bit G12TM ARMv5TEJ ARM7EJ-S ARMv5T jazelle ARMv5 ARM processors LSI coreware library
2006 - applications of arm processor

Abstract: 0324A data flow model of arm processor TrustZone the arm modeling ARM TrustZone API jazelle ARMv7 microcontrollers ARM processor data sheet thumb2
Text: instruction such as BX, BLX. See also Jazelle ® state, Thumb state, and ThumbEE state. 2 Copyright , can be the inverse of others. Jazelle The Jazelle architecture extends the existing ARM architecture to enable direct execution of selected JVM (Java Virtual Machine) opcodes. Jazelle state A processor that is executing Jazelle bytecode instructions is operating in Jazelle state. See also ARM state , also ARM state, Jazelle state, and ThumbEE state. Thumb-2 instruction Thumb-2 is a major


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PDF 32-bit applications of arm processor 0324A data flow model of arm processor TrustZone the arm modeling ARM TrustZone API jazelle ARMv7 microcontrollers ARM processor data sheet thumb2
2001 - ARM DDI 0225

Abstract: Jazelle v1 Architecture Reference Manual DDI 0225 0222B 0x47004700 ARM9EJ-S ARMv5TE instruction set b10010 B-28
Text: 2.3 2.4 2.5 2.6 2.7 2.8 2.9 ARM DDI 0222B About the ARM9EJ-S with Jazelle technology . 1-2 ARM9EJ-S architecture with Jazelle technology . 1-6 , Using Watchpoints and breakpoints in Jazelle state . 6-24 Copyright , pipeline . 1-3 Six-stage Jazelle , Development Kit User Guide (ARM DUI 0040) Jazelle V1 Architecture Reference Manual (ARM DDI 0225). Other


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PDF 0222B ARM DDI 0225 Jazelle v1 Architecture Reference Manual DDI 0225 0222B 0x47004700 ARM9EJ-S ARMv5TE instruction set b10010 B-28
ETSI ts 102.221

Abstract: uicc 102.221 NOR Flash java card 00-S3-J9CH jazelle "JAVA CARD" sim card chip 256KB static RAM
Text: -bit CPU core with enhanced security Crypto Accelerator (Tornado-IITM) - Jazelle , java accelerator , 28KB RAM 32KB MASK ROM (256KB x2) Jazelle SC200 Arbiter FIFO FIFO MMC HOST


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PDF 00-S3-J9CH 16/32-bit SC200 SC200, 32-bit 16/32-bo 15MHz ISO7816 512KB 256KB ETSI ts 102.221 uicc 102.221 NOR Flash java card 00-S3-J9CH jazelle "JAVA CARD" sim card chip 256KB static RAM
2009 - cortex-a5

Abstract: cortex 5 Jazelle v1 Architecture Reference Manual cortex-a5 integration manual cortex-a5 processor 8 stage pipeline architecture of ARMv7 VFPv4-D16 cortex a5 CP15 CP14
Text: . Jazelle extension , . 5-2 CP14 Jazelle register summary . 5-3 CP14 Jazelle register descriptions , . 4-65 CP14 Jazelle registers summary , . 5-6 Jazelle Parameters Register bit assignments


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PDF ID012010) ID012010 Glossary-15 cortex-a5 cortex 5 Jazelle v1 Architecture Reference Manual cortex-a5 integration manual cortex-a5 processor 8 stage pipeline architecture of ARMv7 VFPv4-D16 cortex a5 CP15 CP14
"head up display"

Abstract: up 6103 digital car dashboard ARM926EJ-S ITU656 MB86R01 TN16
Text: -40 to +85°C. The ARM926EJ-S is a fully synthesisable processor with a Jazelle ® technology (JavaTM , processor `Coral PA'. Ends.PR873 Notes to Editors ARM926EJ-S and Jazelle are trademarks or registered


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PDF PR873 32-bit MB86R01 32-bit ARM926EJ-STM "head up display" up 6103 digital car dashboard ARM926EJ-S ITU656 MB86R01 TN16
2008 - MB86H60

Abstract: HDMI YPbPr H.264 encoder arm H.264 encoder ethernet iso7816 ARM1176JZ iso7816 smart card MPEG-4 decoder CI LED IR RX tv tuner module secam
Text: , ARM's Jazelle ® technology and Thumb® instruction set extensions for compact code. The ARM11 provides , , Jazelle and Thumb are registered trademarks of ARM Limited. 2Dolby is a registered trademark of Dolby


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PDF MB86H60 324MHz ITU-R656 ISO7816 324MHz, 484-pin 1ARM1176JZF-S H264-FS-21343-12/2008 HDMI YPbPr H.264 encoder arm H.264 encoder ethernet iso7816 ARM1176JZ iso7816 smart card MPEG-4 decoder CI LED IR RX tv tuner module secam
2010 - ARM pin configuration

Abstract: Coresight 6-pin JTAG AMBA AXI specifications ARM microcontroller ARM1136J-S jazelle ahb to axi
Text: instruction such as BX or BLX. See also Jazelle state, Thumb state, and ThumbEE state. ARM Streamline , can be the inverse of others. J Jazelle ® The Jazelle architecture extends the existing ARM architecture to enable direct execution of selected Java Virtual Machine (JVM) opcodes. Jazelle state A processor that is executing Jazelle bytecode instructions is operating in Jazelle state. See also ARM state , directed to do so by a state-changing instruction such as BX, BLX. See also ARM state, Jazelle state, and


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PDF 0490B ID100410 32-bit ARM pin configuration Coresight 6-pin JTAG AMBA AXI specifications ARM microcontroller ARM1136J-S jazelle ahb to axi
2002 - ARM926EJ-S

Abstract: ARM processor data flow ARM926EJScore embedded trace macrocell ARM926EJ etm lsi logic
Text: five-stage pipeline, Harvard cache architecture processor including the embedded JazelleTM JavaTM technology , ) written to work with the Jazelle hardware. For more information please call: LSI Logic Corporation , trademark of ARM Limited. ARM926EJ-S, AMBA, and Jazelle are trademarks of ARM Limited. Java is a trademark


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PDF 266/200MHz ARM926EJ-STM ARM926EJ-S 266MHz ARM926EJ-S ARM processor data flow ARM926EJScore embedded trace macrocell ARM926EJ etm lsi logic
2009 - mrc 438

Abstract: cortex-a5 processor at550 cortex-a5 integration manual Jazelle v1 Architecture Reference Manual ARM IHI 0029 cortex-a5 VMSA CP15SDISABLE AT551
Text: . Jazelle extension , . 5-2 CP14 Jazelle register summary . 5-3 CP14 Jazelle register descriptions , . 4-66 CP14 Jazelle registers summary , . 5-6 Jazelle Parameters Register bit assignments


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PDF 0433B ID101810) ssary-14 ID101810 Glossary-15 mrc 438 cortex-a5 processor at550 cortex-a5 integration manual Jazelle v1 Architecture Reference Manual ARM IHI 0029 cortex-a5 VMSA CP15SDISABLE AT551
state machine between axi and apb protocol

Abstract: Coresight AMBA ahb bus protocol thumb2 trustzone AMBA Trace Bus state machine for axi to apb bridge 0324B AMBA APB bus protocol Coresight RVI
Text: directed to do so by a state-changing instruction such as BX, BLX. See also Jazelle ® state, Thumb state , others. Jazelle The Jazelle architecture extends the existing ARM architecture to enable direct execution of selected Java Virtual Machine (JVM) opcodes. Jazelle state A processor that is executing Jazelle bytecode instructions is operating in Jazelle state. See also ARM state, Thumb state, and ThumbEE , as BX, BLX. See also ARM state, Jazelle state, and ThumbEE state. Thumb-2 instruction Thumb


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PDF 0324B 032on. 32-bit state machine between axi and apb protocol Coresight AMBA ahb bus protocol thumb2 trustzone AMBA Trace Bus state machine for axi to apb bridge 0324B AMBA APB bus protocol Coresight RVI
ARM1156T2F-S

Abstract: AMBA AXI ARM1026EJ-S thumb2 instruction set arm11 dac adc
Text: ARM11 MPCore x4 MMU, Jazelle , arch v6 SMP 32KB I and D 1MB shared 200MHz CT1156T2F-S ARM1156T2F-S MPU , Powered, StrongARM, Thumb, Multi-ICE, PrimeCell, RealView, ARM7TDMI, ARM9TDMI, EmbeddedICE and Jazelle are


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PDF ARM1156T2F-S CT1156T2F-S. CT1156T2F-S AMBA AXI ARM1026EJ-S thumb2 instruction set arm11 dac adc
2005 - LFBGA-516

Abstract: LFBGA516 PNX5221 voice record to SD card ARM9 processor arm9 architecture ARM926EJ block diagram of MP3 player with video block diagram of speech to text converter ARM926
Text: power and can be programmed to keep pace with evolving algorithms and new codecs. An ARM Jazelle Java , , UARTs, SPIs, I2S, IOM2 high performance ARM926EJ - running @ 208Mhz - ARM Jazelle Java


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PDF PNX5221 LFBGA-516 LFBGA516 PNX5221 voice record to SD card ARM9 processor arm9 architecture ARM926EJ block diagram of MP3 player with video block diagram of speech to text converter ARM926
2010 - cortex-a5

Abstract: cortex-a5 processor arm cortex a5 mpcore arm cortex a9 mpcore Jazelle v1 Architecture Reference Manual CP15 Powered Monitor PL390 CP15SDISABLE CP15 D32DIS
Text: . Jazelle extension , . 5-2 CP14 Jazelle register summary . 5-3 CP14 Jazelle register descriptions , . 4-68 CP14 Jazelle registers summary , . 5-6 Jazelle Parameters Register bit assignments


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PDF 0434B ID101810) ID101810 Glossary-15 Glossary-16 cortex-a5 cortex-a5 processor arm cortex a5 mpcore arm cortex a9 mpcore Jazelle v1 Architecture Reference Manual CP15 Powered Monitor PL390 CP15SDISABLE CP15 D32DIS
2010 - AMBA AXI dma controller designer user guide

Abstract: cortex-a5 integration manual Jazelle v1 Architecture Reference Manual PL390 cortex-a5 Coresight CORTEX-A9 arm cortex a9 mpcore arm generic interrupt controller cortex-a5 processor
Text: . Jazelle extension , . 5-2 CP14 Jazelle register summary . 5-3 CP14 Jazelle register descriptions , . 4-68 CP14 Jazelle registers summary , . 5-6 Jazelle Parameters Register bit assignments


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PDF ID052910) ID052910 Glossary-15 Glossary-16 AMBA AXI dma controller designer user guide cortex-a5 integration manual Jazelle v1 Architecture Reference Manual PL390 cortex-a5 Coresight CORTEX-A9 arm cortex a9 mpcore arm generic interrupt controller cortex-a5 processor
2010 - ARM1136J-S

Abstract: state machine for axi to apb bridge state machine for ahb to apb bridge 6-pin JTAG thumb2 trustzone AMBA AHB protocol for ARM 7 basic architecture of ARM Processors AMBA AXI to APB BUS Bridge AMBA AXI specifications
Text: instructions) when directed to do so by a state-changing instruction such as BX or BLX. See also Jazelle , same, or some can be the inverse of others. J Jazelle The Jazelle architecture extends the , . Jazelle state A processor that is executing Jazelle bytecode instructions is operating in Jazelle state , directed to do so by a state-changing instruction such as BX, BLX. See also ARM state, Jazelle state, and , available, and some new instructions become available. See also ARM state, Jazelle state, and Thumb state


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PDF ID070310) 32-bit ID070310 ARM1136J-S state machine for axi to apb bridge state machine for ahb to apb bridge 6-pin JTAG thumb2 trustzone AMBA AHB protocol for ARM 7 basic architecture of ARM Processors AMBA AXI to APB BUS Bridge AMBA AXI specifications
2005 - ARML210

Abstract: ARM1136 ARM1136JF-S L210 jazelle i.MX31
Text: (0.9V in Standby mode) · Jazelle ® Java acceleration Technology · Vector floating point , service names are the property of their respective owners. ARM and Jazelle are registered trademarks of


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PDF MX31L MX31L ARM1136JF-S ARM1136JF-STM ARM1136, ARM1136JF-S MC9328MX31FS ARML210 ARM1136 L210 jazelle i.MX31
2 input nand gate 24v

Abstract: TPCA8103 ARM10 ARM1026EJ TPCA8101 TPCA8102 2 input nor gate 24v
Text: LSI 20042 ARM1026EJ-S Java Jazelle ® 264 AMBATM AHB ARM 1998


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PDF ARM1026EJ-S 03-3457-3405FAX. ARM1026EJ-S ARM10 2 input nand gate 24v TPCA8103 ARM10 ARM1026EJ TPCA8101 TPCA8102 2 input nor gate 24v
1999 - ARM Debug Interface v5 architecture specification

Abstract: Qualcomm ARM IHI 0029 QUALCOMM Reference manual Jazelle v1 Architecture Reference Manual CoreSight Architecture Specification qualcomm 8 ATB flush ARMv7-M Architecture Reference Manual armv7-a
Text: 4-53 Jazelle state , with exception, Jazelle state . 4-15 Branch address packet cycle count , ThumbEE instructions can be fully traced. In processors that include a nontrivial Jazelle ® implementation


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ARM1136J-S

Abstract: use of clock generator in ARM 64 bit pci backplane
Text: , ARM7TDMI, ARM9TDMI, EmbeddedICE and Jazelle are registered trademarks of ARM Limited. ARM7TDMI-S, ARM7EJ-S


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PDF ARM926EJ-S ARM1136J-S use of clock generator in ARM 64 bit pci backplane
S3C2412

Abstract: Samsung s3c2412 S3C2410A ARM926EJ-S samsung NAND Flash DIE ARM926EJ uart protocol touch screen 272-FBGA
Text: 's Jazelle Java technology enhanced ARM architecture · MMU to support WinCE, Symbian and Linux ¡ · Power


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PDF S3C2412 S3C2412 S3C2410A. 10-bit 100/133MHz 200MHz 266MHz 272-FBGA Samsung s3c2412 S3C2410A ARM926EJ-S samsung NAND Flash DIE ARM926EJ uart protocol touch screen
2004 - CMOS Camera Module CSI imx

Abstract: MI0343 AMI-120 symbian GS1000 MC9328MX1 ARM920T CMOS Camera Module interface with arm 11 sharp CMOS Camera Module CSI TRACE32-PowerTrace-ARM9TM
Text: ARM926EJ-STM core, with Jazelle ® Java acceleration, the i.MX21 is your key to robust multimedia applications , property of their respective owners. ARM, the ARM POWERED logo, and Jazelle are the registered trademarks


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PDF ARM920T ARM926EJ-S CMOS Camera Module CSI imx MI0343 AMI-120 symbian GS1000 MC9328MX1 CMOS Camera Module interface with arm 11 sharp CMOS Camera Module CSI TRACE32-PowerTrace-ARM9TM
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