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LTC3730CG Linear Technology LTC3730 - 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C
LTC3738CUHF Linear Technology LTC3738 - 3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C
LTC3738CUHF#PBF Linear Technology LTC3738 - 3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C
LTC3730CG#TRPBF Linear Technology LTC3730 - 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C
LTC3730CG#TR Linear Technology LTC3730 - 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C
LTC3738CUHF#TR Linear Technology LTC3738 - 3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C

intel 8257 interrupt controller Datasheets Context Search

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block and pin diagram of 8257

Abstract: IC 8212 internal block diagram DMA Controller 8257 intel 8257 dma 8257 DIWA 200 ic 8257 block diagram intel 8212 intel 8257 interrupt controller 8257
Text: Controller 6-115 AFN-01840B intel 8257 /8257-5 A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD , inteT 8257 /8257-5 PROGRAMMABLE DMA CONTROLLER i MCS-85® Compatible 8257-5 ■Terminal Count , DMA controller for use in Intel® microcomputer systems. After being initialized by software, the 8257 , 6-108 AFN-0184GB intel 8257 /8257-5 3. Read/Write Logic When the CPU is programming or reading one , Function 6-109 AFN-01840B intel 8257 /8257-5 (A4-A7) Address Lines. These four address lines are


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PDF MCS-85Â T9-50 Tcy-50 2Tcy-50 AFN-01840B block and pin diagram of 8257 IC 8212 internal block diagram DMA Controller 8257 intel 8257 dma 8257 DIWA 200 ic 8257 block diagram intel 8212 intel 8257 interrupt controller 8257
Intel 8237 dma controller block diagram

Abstract: DMA interface 8237 WITH 8088 DMA Controller 8257 8086 8257 DMA controller intel d 8274 intel 8257 interrupt controller intel 8274 8257 intel block and pin diagram of 8257 dma 8257
Text: 8274 MULTI-PROTOCOL SERIAL CONTROLLER (MPSC) Asynchronous, Byte Synchronous and Bit Synchronous , , 8088, 8086, 80188 and 80186 CPU's; 8257 and 8237 DMA Controllers; and 8089 I/O Proc. 4 Independent DMA , -16) - CCITT X.25 Compatible Available in EXPRESS and Military The Intel 8274 Multi-Protocol Series Controller (MPSC) is designed to interface High Speed Communications Lines using Asynchronous, IBM Bisync, and SDLC/HDLC protocol to Intel microcomputer systems. It can be interfaced with Intel 's MCS-48, -85


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PDF CRC-16) Intel 8237 dma controller block diagram DMA interface 8237 WITH 8088 DMA Controller 8257 8086 8257 DMA controller intel d 8274 intel 8257 interrupt controller intel 8274 8257 intel block and pin diagram of 8257 dma 8257
8086 8257 DMA controller

Abstract: Intel 8237 dma controller block diagram block and pin diagram of 8257 intel 8257 interrupt controller Block Diagram of 8237 DMA Controller 8257 CCITT-16 DMA interface 8237 WITH 8088 intel 8274 pin diagram of 8257
Text: Intel 's MCS-48, -85, -51 ; iAPX-86, -88, -186 and -188 families, the 8237 DMA Controller , or the 8089 I , Available in EXPRESS and Military MULTI-PROTOCOL SERIAL CONTROLLER (MPSC) Fully Compatible with 804B, 8051, 8085, 8088, 8086, 80188 and 80186 CPU's; 8257 and 8237 DMA Controllers; and 8089 I/O Proc. 4 , Parity; 1, 1.5 or 2 Stop Bits - Error Detection: Framing, Overrun, and Parity The Intel 8274 Multi-Protocol Series Controller (MPSC) Is designed to interface High Speed Communications Lines using


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PDF CRC-16) CCITT-16) MCS-48, iAPX-86, 8086 8257 DMA controller Intel 8237 dma controller block diagram block and pin diagram of 8257 intel 8257 interrupt controller Block Diagram of 8237 DMA Controller 8257 CCITT-16 DMA interface 8237 WITH 8088 intel 8274 pin diagram of 8257
8295 printer controller

Abstract: programmable dot matrix printer controller 8295 intel 8295 block and pin diagram of 8257 8257 DMA controller "dot matrix printer controller" intel 8295 printer controller intel 8295 microprocessor DMA Controller 8257 dma 8257
Text: low. 8-342 AFN-00231C intel 8295 DOT MATRIX PRINTER CONTROLLER ■Interfaces Dot Matrix , to the 8257 DMA controller without further CPU intervention. Figure 4 shows a block diagram of the 8295 in DMA mode. Figure 3. Host to 8295 Protocol Flowchart 8257 DMA CONTROLLER PFM 8295 STB , follows: 1. Set up the 8257 DMA controller channel by sending a starting address and a block length. 2 , the 8257 that a DMA transfer is requested; in the serial mode used as clear-to-send signal. IRQ/SËR


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PDF AFN-00231C AFN-00231C 8295 printer controller programmable dot matrix printer controller 8295 intel 8295 block and pin diagram of 8257 8257 DMA controller "dot matrix printer controller" intel 8295 printer controller intel 8295 microprocessor DMA Controller 8257 dma 8257
programmable dot matrix printer controller 8295

Abstract: 8295 printer controller UART 8251 block diagram of dot matrix printer intel 8295 STB-34 intel 8295 microprocessor USART 8251 15 pin dot matrix printer head Intel* 8295 Dot Matrix Printer Controller
Text:  intel 8295 DOT MATRIX PRINTER CONTROLLER Interfaces Dot Matrix Printers to MCS-48™, MCS , Outputs The Intel * 8295 Dot Matrix Printer Controller provides an interface for microprocessors to the , assert the required DMA requests to the 8257 DMA controller without further CPU intervention. Figure 4 , 8295 STATUS IBF = 1 Figure 3. Host to 8295 Protocol Flowchart £ 8257 DMA CONTROLLER OACKx DRQx  , request output pin to indicate to the 8257 that a DMA transfer is requested; in the serial mode used as


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PDF MCS-48â MCS-80/85â MCS-86â AFN-00231C programmable dot matrix printer controller 8295 8295 printer controller UART 8251 block diagram of dot matrix printer intel 8295 STB-34 intel 8295 microprocessor USART 8251 15 pin dot matrix printer head Intel* 8295 Dot Matrix Printer Controller
block and pin diagram of 8257

Abstract: IC 8212 internal block diagram ic 8257 block diagram i8257 DMA Controller 8257 d8257 bu 808 af intel 8257 interrupt controller 8257 E8257C
Text: in t e i 8257 / 8257-5 PROGRAMMABLE DMA CONTROLLER MCS-85® Compatible 8257-5 4-Channel DMA Controller Priority DMA Request Logic Channel Inhibit Logic Terminal Count and Modulo 128 Outputs , fo r use in Intel » m icro com p uter systems. A fter being initialized by software, the 8257 can , program m ed by an interrupt structure 8257 Register Selection ·Ao-A, 5: DMA Starting Address C0-C13 , In te l1 8257 is a 4-channel dire ct m em ory access (DMA) con troller. It is s p e c ific a lly


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PDF MCS-85® pli257 block and pin diagram of 8257 IC 8212 internal block diagram ic 8257 block diagram i8257 DMA Controller 8257 d8257 bu 808 af intel 8257 interrupt controller 8257 E8257C
block diagram of dot matrix printer

Abstract: Intel* 8295 Dot Matrix Printer Controller
Text: ­ tions w ill then remain valid until new Set Tab commands are issued. the 8257 DMA controller without , procedure is as follows: 1. Set up the 8257 DMA controller channel by sending a starting address and a , in te !' 8295 DOT MATRIX PRINTER CONTROLLER ■Programmable Print Intensity ■Interfaces , Character Density (10 or 12 Chararcters/inch) ■2 General Purpose Outputs The Intel * 8295 Dot Matrix Printer Controller provides an interface for microprocessors to the LRC 7040 Series dot matrix


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PDF MCS-48â MCS-80/85â MCS-86â AFN-00231C block diagram of dot matrix printer Intel* 8295 Dot Matrix Printer Controller
8086 8257 DMA controller interfacing

Abstract: intel 8257 interrupt controller interfacing of 8257 with 8086 GA27-3093 Intel 8257 intel d 8273 8086 8257 DMA controller intel 8273 8273 dma controller 80188 application note
Text: transfer. DMA transfers require the use of a DMA controller such as the Intel 8257 . The function of the ,  intel 8273 PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER CCITT X.25 Compatible HDLC/SDLC , The Intel 8273 Programmable HDLC/SDLC Protocol Controller is a dedicated device designed to support , TTL clock. 2-84 intel . FUNCTIONAL DESCRIPTION General The Intel 8273 HDLC/SDLC controller is a , the MCS-80/ 85™ bus with an 8257 DMA controller . However, the interface is flexible, and allows


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Intel BUBBLE

Abstract: intel 8257 interrupt controller BPK72 intel 7242
Text: memory access (DMA), interrupt or poll. The 7220-1 bubble-memory controller (BMC) has several functional , and transfer counts and initiate the data transfer; Intel 's 8257 DMA-controller hardware automatically , tradeoffs helps configure a system that best suits your needs. Richard Pierce, Intel Corp Designing a , bubble-system tradeoffs and other design considera tions and presents a specific design using Intel 's lM-bit bubble-memory device and family of support chips. Interface appears as a peripheral controller its way to


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PDF AR-272 Intel BUBBLE intel 8257 interrupt controller BPK72 intel 7242
intel 8273

Abstract: interfacing of 8257 with 8086 8086 8257 DMA controller interfacing interfacing of 8257 devices with 8085 8273 dma controller GA27-3093 8273 disk controller 8257 DMA controller 8086 8257 DMA controller intel 8257 interrupt controller
Text: controller such as the Intel 8257 . The function of the DMA controller is to provide sequential addresses and ,  intel 8273 PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER CCITT X.25 Compatible HDLC/SDLC , The Intel 8273 Programmable HDLC/SDLC Protocol Controller is a dedicated device designed to support , interface is optimized for the MCS-80/ 85™ bus with an 8257 DMA controller . However, the interface is , Result 2. A Non-Immediate Result intel . 8273 D7 d6 ds D4 d3 d2 Di Do Early transmit interrupt


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BPK72

Abstract: intel 7110 DMA Controller 8257 isbx-251
Text: transfer mode, the BMC operates in conjunction with a DMA controller (e.g., Intel 's 8257 or 8237) and uses , in conjunction with the DACK/ input from a DMA controller (e.g., in Intel 8257 or 8237) on the user , completed. In the interrupt-driven data transfer mode, the DRQ line is connected to an interrupt controller , single-chip LSI Bubble Memory Controller (BMC) that implements a bubble memory storage subsystem (with up to , your specific application requirements. Product Line Overview Intel offers a complete line of


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PDF AP-157 BPK72 intel 7110 DMA Controller 8257 isbx-251
8275 crt controller intel

Abstract: Intel 8275 block diagram of Intel 8275 8275 crt controller intel 8245 crt Intel 8245 ic 8275 intel d 8275 Intel 8275 Block diagram 8275
Text: line positions on the screen. DRQ 5 0 DMA Request: Output signal to the 8257 DMA controller requesting a DMA cycle. DACK 6 1 DMA Acknowledge: Input signal from the 8257 DM A controller acknowledging , detection. It is designed to interface with the 8257 DMA Controller and standard character generator ROMs , generate an interrupt request at the end of each frame. This can be used to reinitialize the DMA controller , intßl 8275 PROGRAMMABLE CRT CONTROLLER Programmable Screen and Character Format 6


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PDF MCS-80 MCS-85 40-Pln AFN-00224B AFN-00224B 8275 crt controller intel Intel 8275 block diagram of Intel 8275 8275 crt controller intel 8245 crt Intel 8245 ic 8275 intel d 8275 Intel 8275 Block diagram 8275
STR S 6307

Abstract: str 6307 uP 6308 AD STR 6309 uP 6308 AP str s 6309 STR 6307 POWER LT 7224 of str 6309 str 6308
Text: configuration is the Intel 8257 DMA controller . To support an interrupt-driven system an Intel 8259 Pro , bubble memory is performed through the controller . The BMC interfaces easily to any Intel microprocessor , , interrupt or polled mode. Data is transferred in and out of the bubble memory subsystem via the controller , capability; i.e., it has the ability to handshake with an 8257 or 9517/8237 DMA controller chip. (2) If the , the controller to support interrupt driven or polled data transfer. INTERRUPT ENABLE (ERROR) selects


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8086 8257 DMA controller interfacing

Abstract: interfacing of 8257 with 8086 8273 dma controller interfacing of 8257 devices with 8085 8086 8257 DMA controller intel 8257 intel 8080 architecture 82734 MCS-88 GA27-3093
Text: transfer. DMA transfers require the use of a DMA controller such as the Intel 8257 . The function of the ,  intel 8273, 8273-4, 8273-8 PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER ■CCITT X , -80/85™ bus with an 8257 DMA controller . However, the interface is flexible, and allows either DMA or , Controller is a dedicated device designed to support the ISO/ CCITT's HDLC and IBM's SDLC communication line protocols. It is fully compatible with Intel 's new high performance microcomputer systems such as the MCS


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PDF 150pF AFN-00743B AFN-00743B 8086 8257 DMA controller interfacing interfacing of 8257 with 8086 8273 dma controller interfacing of 8257 devices with 8085 8086 8257 DMA controller intel 8257 intel 8080 architecture 82734 MCS-88 GA27-3093
8294 intel

Abstract: intel 8294A 8257 DMA controller intel MCS4 kpe 353
Text: signal from the 8257 DMA Controller acknowledging that the requested DMA cycle has been granted. DMA REQUEST: Output signal to the 8257 DMA Controller requesting a DMA cycle. SERVICE REQUEST: Interrupt to , DMA Interface 3 Interrupt Outputs to Aid in Loading and Unloading Data 7-Bit User Output Port The Intel ® 8294A Data Encryption Unit (DEU) is a microprocessor peripheral device designed to encrypt and , interrupt outputs are available to minimize software overhead associated with data transfer. Also, by using


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PDF iAPX-86, MCS-80TM, 64-Bit 56-Bit 8294 intel intel 8294A 8257 DMA controller intel MCS4 kpe 353
8089 microprocessor block diagram

Abstract: 8089 intel microprocessor Architecture Diagram intel 8292 8089 microprocessor pin diagram intel 8089 microprocessor Features 8089 microprocessor Features intel d 8293 intel 8291A 8089 microprocessor architecture 8291 gpib
Text: . 2. The BO interrupt is not asserted until RFD is true. If the Controller asserts STfJ synchronously , . The SPASC Interrupt was ambiguous because a controller could enter SPAS and exit SPAS generating two , commands which may be passed to the microprocessor. 3. All Controller messages must be sent via Intel , requested service (asserted SRQ). The SPC interrupt occurs once after the controller reads the status byte , controller , rsv is automatically cleared by the 8291A and an SPC interrupt is generated. The CPU may request


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SPI to IEEE-488

Abstract: 8080 intel microprocessor pin diagram intel 8292 intel 8291A intel 8291 8291 gpib 8291A 8089 microprocessor pin diagram intel d 8293 8089 microprocessor architecture
Text: status byte after the 8291A requested service. The SPASC interrupt was ambiguous because a controller , commands which may be passed to the microprocessor. 3. All Controller messages must be sent via Intel , requested service (asserted SRQ). The SPC interrupt occurs once after the controller reads the status byte , controller , rsv is automatically cleared by the 8291A and an SPC interrupt is generated. The CPU may request ,  intel 8291A GPIB TALKER/LISTENER ■Designed to Interface Microprocessors (e.g., 8048/49


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intel 8259 programmable interrupt controller

Abstract: TCDF 1900 Memtech 7225 bubble d7225 Bubble Memory D7225-6 kz3C D7225-1 a7245
Text: implementations are possible, one common configuration is the Intel 8257 DMA controller . To support an interrupt-driven system an Intel 8259 Programmable Interrupt Controller is often used. The polled data transfer , through the controller . The BMC interfaces easily to any Intel microprocessor or other standard , , interrupt , or polled mode. Data is transferred in and out of the bubble memory subsystem to the controller , handshake with an 8257 or 9517/8237 DMA controller chip. The INT pin performs the task of interrupting the


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PDF D7225-1 D7225-6 SA/1187/5K/RJ/DT intel 8259 programmable interrupt controller TCDF 1900 Memtech 7225 bubble d7225 Bubble Memory D7225-6 kz3C a7245
RU 110012

Abstract: dma 8257 sdk 8085 microcomputer intel 8273 IC TL 0841 8273 dma controller DMA8257 oni 350 0836 sdk 8a5c
Text: controller , in this case the Intel 8257 , is required. T he D M A controller supplies th e tim ing an d , Controller JOHN BEASTON MICROCOMPUTER APPLICATIONS Order Number: 611001-001 U S IN G T H E 8 2 7 3 , he Intel 8273 is a D a ta C om m unications Protocol C o n tro ller designed for use in system s , controller statio n w ith one o r m ore dow n-loop second ary stations. C om m unications on a loop rely on , inserted, ones. A f ter the loop controller transm its a m essage, it idles the line (sends all Is). T he


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PDF AP-36 STAT57 PARM73 STAT73 0ft62 RU 110012 dma 8257 sdk 8085 microcomputer intel 8273 IC TL 0841 8273 dma controller DMA8257 oni 350 0836 sdk 8a5c
8089 microprocessor pin diagram

Abstract: 8089 microprocessor architecture intel 8291A 8089 microprocessor block diagram 8048 micro controller block diagram 8291 gpib SPI to IEEE-488 s3-via 140UD Pin Details of bus controller IC 8282
Text: the controller has read the bus status byte after the 8291A requested service. The SPASC interrupt was , which may be passed to the microprocessor. 3. All Controller messages must be sent via Intel 's 8292 , after the 8291A requested service (asserted SRQ). The SPC interrupt occurs once after the controller , controller , rsv is automatically cleared by the 8291A and an SPC interrupt is generated. The CPU may request , functions except for the controller . The controller function can be added with the 8292 GPIB Controller , and


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intel 8291

Abstract: intel 8297 intel 8295 Block diagram microprocessor 8085 microprocessor intel 8295 microprocessor 8279 intel microprocessor pin diagram 8291 gpib block diagram of intel 8279 chip intel 8276 microprocessors interface 8237
Text: ) UNL | Unlisten (via C) "All Controller messages must be sent via Intel 's 8292. 8-281 AFN , interrupt 8-284 AFN-00229B intel 8291 handling procedures. When an enabled interrupt bit is set in , output signal compatible with Intel 's MCS-48™. Interrupt registers are not affected by this bit , 's Interface functions except for the controller . T/Hic T/H2C CLOCKC RESETC tbigC dreqC dackC CSI rdC WKC 10 , Interrupt : Interrupt request to the microprocessor, set high for request and cleared when the appropriate


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PDF AFN-00229B AFN-00229B intel 8291 intel 8297 intel 8295 Block diagram microprocessor 8085 microprocessor intel 8295 microprocessor 8279 intel microprocessor pin diagram 8291 gpib block diagram of intel 8279 chip intel 8276 microprocessors interface 8237
D8742

Abstract: interfacing of 8257 with 8086 phoenix multikey 8086 8257 DMA controller interfacing 8255 interfacing with 8086 Peripheral interface 8279 notes 8242PC 8275 crt controller intel 82C42PC 82L42PC
Text: satisfied. W ith the introduction o f the U niversal P eripheral In terface (U P I ) m icrocom puter, Intel has taken the intel ligent peripheral concept a step fu rth er by providing an intelligent controller , (TIMER) 8257 (DMA) 8259 82077AA 8273 (SDLC) 8274 Programmable Peripheral Interface Programmable Communication Interface Programmable Interval Timer Programmable DMA Controller Programmable Interrupt , link controller (see Table 1-1) can preprocess serial d a ta and perform con trol tasks which off-load


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PDF UPI-41A/41AH/42/42AH D8742 interfacing of 8257 with 8086 phoenix multikey 8086 8257 DMA controller interfacing 8255 interfacing with 8086 Peripheral interface 8279 notes 8242PC 8275 crt controller intel 82C42PC 82L42PC
using the 8292 gpib controller

Abstract: 8089 microprocessor architecture 8089 microprocessor block diagram 110B8 intel 8291A 8089 microprocessor pin diagram 8291 intel 8089 microprocessor Features 8291 gpib SPI to IEEE-488
Text: . The BO interrupt is not asserted until RFD is true. If the Controller asserts ATN synchronously, the , . The SPASC interrupt was ambiguous because a controller could enter SPAS and exit SPAS generating two , to the microprocessor. 3. All Controller messages must be sent via Intel 's 8292. Table 3. IEEE 488 , requested service (asserted SRQ). The SPC interrupt occurs once after the controller reads the status byte , controller , rsv is automatically cleared by the 8291A and an SPC interrupt is generated. The CPU may request


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Not Available

Abstract: No abstract text available
Text: inU 8742 UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER ■DMA, Interrupt , or , 8741A ■Fully Compatible with all Intel and Most Other Microprocessor Families ■8-Bit CPU , and Two Data Registers for Asynchronous Slave-toMaster Interface The Intel 8742 is a , included to enable the UPI device to function as a peripheral controller in the MCS®-48, MCS-51, MCS , during PORT 4 - 7 access. The upper 4 bits (P24- P 27) can be programmed to provide interrupt Request


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PDF iUP-200/iUP-201 UP-F87/44 UPP-549 Mfl2bl75
intel 8218

Abstract: XSTR intel 8219 MCS "intel 8218" MCS 8085 intel 8219 8219 INTEL MCS-85 8218 8257 intel
Text:  intel ßtänoiMAGw 8218/8219 BIPOLAR MICROCOMPUTER BUS CONTROLLERS FOR MCS-80® AND MCS , 8219 can interface directly to the 8085A CPU and the 8218 interfaces to the8080A CPU chip and the 8257 DMA controller . - bus arbitration logic to the a_, bus < ~j xstr master n , be used for interrupt status from the 8085. Acts like a level sensitive asynchronous bus request—no , interface between a master device and the system Bus. (Master device: 8080, 8085, 8257 (DMA).) The 8218 and


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PDF MCS-80Â MCS-85Â inMCS-85Â AFN-00208B AFN-00208B intel 8218 XSTR intel 8219 MCS "intel 8218" MCS 8085 intel 8219 8219 INTEL MCS-85 8218 8257 intel
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