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CP3500AC52TEZ-FB GE Critical Power CP3500AC52TE-FB Global Platform High Efficiency Rectifier, Input: 100-120/200-240 Vac; 3500W capable; Default set: ±52 Vdc @; 5 Vdc @ 10W
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DEM-PCM1800 Texas Instruments DEM-PCM1800: Instruction Manual for the PCM1800
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instruction set of TMS320C5x Datasheets Context Search

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instruction set of TMS320C5x

Abstract: architecture of TMS320C5x TMS320C5X addressing modes tms320c5x on chip peripherals instruction set tms320c50 tms320c5x instruction set addressing modes of TMS320C50 TMS320C5x architecture TMS320c25 use ds-88
Text: Instruction Set C.3 Instruction Set The TMS320C5x instruction set is a superset of the TMS320C25 instruction set . The instruction set of the TMS320C25 is upward source-code compatible. This means that all of the , the instruction set , a number of different instructions are combined into single new instructions with , Instruction Set TMS320C5x does not automatically enable the interrupts globally with its IDLE instruction . If , exception of memory map; so within this appendix, any reference to TMS320C5x applies to both TMS320C50


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PDF TMS320C5X TMS320C25 TMS320 TMS320C50 TMS320C51 andTMS320C51 instruction set of TMS320C5x architecture of TMS320C5x TMS320C5X addressing modes tms320c5x on chip peripherals instruction set tms320c50 tms320c5x instruction set addressing modes of TMS320C50 TMS320C5x architecture use ds-88
1995 - block diagram of TMS320C5X starter kit

Abstract: PZ S-PQFP-G100 Package footprint BSDL tms320 instruction set of TMS320C5x abstract for wireless technology in ieee format TMS320C50PQ57 TMS320BC52PZ100 TMS320LBC53 TMS320C5x dsp XDS510 jtag ide tms320c50
Text: peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational , ) description The TMS320C5x generation of the Texas Instruments (TITM ) TMS320 digital signal processors (DSPs , (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal Interrupt , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal External


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns block diagram of TMS320C5X starter kit PZ S-PQFP-G100 Package footprint BSDL tms320 instruction set of TMS320C5x abstract for wireless technology in ieee format TMS320C50PQ57 TMS320BC52PZ100 TMS320LBC53 TMS320C5x dsp XDS510 jtag ide tms320c50
1997 - architecture of TMS320C5x

Abstract: DSP ARCHITECTURE TMS320C5x instruction set of TMS320C5x TMS320C5x architecture diagram TLC5510 dsp tms320c5x instruction set TMS320C5X addressing modes spra272 TMS320C2XX FF00H-FFFFH
Text: TMS320C5x DSP at a data rate of 20 MSPS. The 8-bit TLC5510 flash A/D converter can be directly interfaced , TMS320C2xx or TMS320C5x DSP at a data rate of 20 MSPS? Solution The 8-bit TLC5510 flash A/D converter can , TMS320C2xx and the TMS320C5x , respectively. The TLC5510 is connected to the lower 8 bits of the TMS320C2xx/ TMS320C5x data bus. The CLK signal is connected with the read signal /RD of the DSP and is active when , TMS320C2xx/ TMS320C5x timing requirements. Because the high data byte of the TMS320C2xx/ TMS320C5x data bus


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PDF TMS320 20-MSPS TLC5510 TMS320C2xx TMS320C5x SPRA272 0000h-FFFFh FF00h-FFFFh 0834h 0800h architecture of TMS320C5x DSP ARCHITECTURE TMS320C5x instruction set of TMS320C5x TMS320C5x architecture diagram dsp tms320c5x instruction set TMS320C5X addressing modes spra272 TMS320C2XX FF00H-FFFFH
1998 - TMS320C5X addressing modes

Abstract: Architecture of TMS320C54X tms320c54x MEMORY MAPPED REGISTERS ST0 ST1 TMS320C54X addressing modes TMS32050 addressing modes with examples TMS320C54X addressing modes with examples BPRA075 Architecture and features of TMS320C54X tms320c5x instruction set summary TMS320C54X FIXED POINT
Text: . 32 TMS320C5x to TMS320C54x Translation Utility ii Contents List of Tables Table 1 , instruction counts as well as cycles. This process is most easily performed when the target instruction set is closely matched to the primitive set , i.e. such as the 'C6x. The process of translating from , assembly (using . set or .equ). TMS320C5x to TMS320C54x Translation Utility 5 Table 6 , ) TMS320C5x to TMS320C54x Translation Utility 7 3.5 Conditional Code Mapping The combinations of


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PDF TMS320C5x TMS320C54x BPRA075 TMS320C54x TMS320C5X addressing modes Architecture of TMS320C54X tms320c54x MEMORY MAPPED REGISTERS ST0 ST1 TMS320C54X addressing modes TMS32050 addressing modes with examples TMS320C54X addressing modes with examples BPRA075 Architecture and features of TMS320C54X tms320c5x instruction set summary TMS320C54X FIXED POINT
1997 - architecture of TMS320C5X

Abstract: instruction set of TMS320C5x SPRA220 dsp processor Architecture of TMS320C5X Application TMS320C5x TMS320C5x TMS320
Text: . 6) Cycle 9 - Start of first instruction in the ISR. INTM is set to a 1 (INTM=1) and an IACK is , generate an interrupt at both the leading and trailing edges of the bar. The TMS320C5x context switches to , table, thus reducing the external interrupt capability of the TMS320C5x by one. 4) The interrupt latency of the TMS320C5x depends on the current contents of the pipeline. The device always completes all , RAM. This will minimize TMS320C5x Interrupt Response Time 9 the execution time of copying


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PDF TMS320 TMS320C5x SPRA220 architecture of TMS320C5X instruction set of TMS320C5x SPRA220 dsp processor Architecture of TMS320C5X Application TMS320C5x
1997 - instruction set of TMS320C5x

Abstract: TMS320C5x TMS320C5x dsp TMS320 TMS320C51 TMS320C52 tms320c5x user guide
Text: options and the fully static design of the TMS320C5x give the user a lot of flexibility. As can be seen in Appendix A-10 of the TMS320C5x User's Guide, two pins CLKMD1 and CLKMD2 select which clock mode , listed on Appendix A-13 of the TMS320C5x User's Guide. As you can see, minimum frequency is not 0 MHz , changed. In fact, the TMS320C5x 's clock generation circuitry should be thought of as an external module , Figure 1 shows a flexible design for a 25-ns device that uses all features of the TMS320C5x clock modes


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PDF TMS320 TMS320C5x SPRA243 25-ns TMS320C51 instruction set of TMS320C5x TMS320C5x dsp TMS320C52 tms320c5x user guide
1995 - tms320c5x instruction set

Abstract: TMS320C5X application notes block diagram of TMS320C5X starter kit PJ 976 instruction set of TMS320C5x TMS320LC51
Text: peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational , ) description The TMS320C5x generation of the Texas Instruments (TITM ) TMS320 digital signal processors (DSPs , (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal Interrupt , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal External


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns tms320c5x instruction set TMS320C5X application notes block diagram of TMS320C5X starter kit PJ 976 instruction set of TMS320C5x TMS320LC51
1998 - TMS320C5X addressing modes

Abstract: instruction set of TMS320C5x TMS320C5x dsp semiconductors replacement guide TMS320 load and store instructions of TMS320C5x
Text: and instruction set of the C2xx is similar to the C5x, porting of code from the C5x to the C2xx is fairly straightforward. The C2xx instruction set is fully capable of implementing the functionality of , . 39 Appendix A. Summary of Instruction Replacements , of a TMS320C5x (C5x) DSP. Although some code has been written for the C2xx, reuse of the large , effect on specific instruction replacements but is a major system level consideration: the use of


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PDF TMS320C5x TMS320C2xx SPRA293 TMS320C5X addressing modes instruction set of TMS320C5x TMS320C5x dsp semiconductors replacement guide TMS320 load and store instructions of TMS320C5x
1996 - disadvantage of crystal oscillator

Abstract: instruction set of TMS320C5x 40 MHZ OSCILLATOR TMS320 TMS320C52 TMS320C52-57 TMS320C52-80
Text: TMS320 DSP Number 47 DESIGNERS NOTEBOOK TMS320C5x Clock Modes Contributed by Joe George , (PLL). Solution The clock options and the fully-static design of the C5x give the user a lot of flexibility. As can be seen in Appendix A-10 of the C5x Users Guide, two pins CLKMD1 and CLKMD2 select which , reset ( 45 =0). A common mode is to run the CPU at a rate that is a divide-by-two of the input , frequency to instruction cycle frequency, it makes the most sense to refer to the instruction cycle time or


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PDF TMS320 TMS320C5x 25-ns 40-MHz 50-ns disadvantage of crystal oscillator instruction set of TMS320C5x 40 MHZ OSCILLATOR TMS320C52 TMS320C52-57 TMS320C52-80
1995 - Not Available

Abstract: No abstract text available
Text: peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational , ) description The TMS320C5x generation of the Texas Instruments (TITM ) TMS320 digital signal processors (DSPs , (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal Interrupt , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal External


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns
1995 - Not Available

Abstract: No abstract text available
Text: peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational , ) description The TMS320C5x generation of the Texas Instruments (TITM ) TMS320 digital signal processors (DSPs , (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal Interrupt , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal External


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns
1995 - Not Available

Abstract: No abstract text available
Text: peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational , ) description The TMS320C5x generation of the Texas Instruments (TITM ) TMS320 digital signal processors (DSPs , (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal Interrupt , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal External


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns
1996 - Not Available

Abstract: No abstract text available
Text: architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of , Port (JTAG) description The TMS320C5x generation of the Texas Instruments (TI™) TMS320 digital , €™C5x DSPs.) Enhanced TMS320 instruction set for faster algorithms and for optimized high-level , signal. Indicates output of internal timer IAQ O/Z Instruction acquisition signal INT1 â , count is specified by a constant embedded in the instruction word or by the value in TREG1. The LSBs of


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns
1996 - TMS320C5X addressing modes

Abstract: TMS320LC51
Text: architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of , Port (JTAG) description The TMS320C5x generation of the Texas Instruments (TI™) TMS320 digital , €™C5x DSPs.) Enhanced TMS320 instruction set for faster algorithms and for optimized high-level , signal. Indicates output of internal timer IAQ O/Z Instruction acquisition signal INT1 â , count is specified by a constant embedded in the instruction word or by the value in TREG1. The LSBs of


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns TMS320C5X addressing modes TMS320LC51
1995 - TMS320C5x architecture diagram

Abstract: TMS320LC51
Text: peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational , ) description The TMS320C5x generation of the Texas Instruments (TITM ) TMS320 digital signal processors (DSPs , (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal Interrupt , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal External


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns TMS320C5x architecture diagram TMS320LC51
1995 - 1AAA

Abstract: TMS320LC50 TMS320C52 TMS320C51 TMS320C50 TMS320C25 TMS320 TMS320C5x architecture diagram 320C5X TMS320LC51
Text: , on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and , TMS320C5x generation of the Texas Instruments (TITM) TMS320 digital signal processors (DSPs) is fabricated , 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set for faster , output of internal timer IAQ O/Z Instruction acquisition signal IACK O/Z Interrupt , output of internal timer IAQ O/Z Instruction acquisition signal INT1 ­ INT4 I External


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns 1AAA TMS320LC50 TMS320C52 TMS320C51 TMS320C50 TMS320C25 TMS320 TMS320C5x architecture diagram 320C5X TMS320LC51
1996 - instruction set of TMS320C5x

Abstract: TMS320
Text: pipeline. 24-3 6. Cycle 9 Start of first instruction in the ISR. INTM is set to a 1 (INTM=1) and , generate an interrupt at both the leading and trailing edges of the bar. The TMS320C5x context switches to , bit of Interrupt Flag Register (IFR) is set signifying an interrupt has occurred. 4. Cycle 5 I6 is , cycle 13). 9. Cycle 15 SACL instruction executes completing the write of the TIM Timer counter , SACL instruction executes completing the write of the TIM Timer counter register, corresponding to the


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PDF TMS320 TMS320C5x instruction set of TMS320C5x
1995 - Not Available

Abstract: No abstract text available
Text: peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational , ) description The TMS320C5x generation of the Texas Instruments (TITM ) TMS320 digital signal processors (DSPs , (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal Interrupt , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal External


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns
1995 - Not Available

Abstract: No abstract text available
Text: peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational , ) description The TMS320C5x generation of the Texas Instruments (TITM ) TMS320 digital signal processors (DSPs , (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal Interrupt , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal External


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns
1995 - Not Available

Abstract: No abstract text available
Text: peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational , ) description The TMS320C5x generation of the Texas Instruments (TITM ) TMS320 digital signal processors (DSPs , (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal Interrupt , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal External


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns
1995 - TMS320C5x architecture diagram

Abstract: linear convolution code in TMS320C50 TMS320LC51 TMS320LC50 TMS320C52 TMS320C51 TMS320C50 TMS320C25 TMS320 TMS320BC51PQ57
Text: , on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and , TMS320C5x generation of the Texas Instruments (TITM) TMS320 digital signal processors (DSPs) is fabricated , 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set for faster , output of internal timer IAQ O/Z Instruction acquisition signal IACK O/Z Interrupt , output of internal timer IAQ O/Z Instruction acquisition signal INT1 ­ INT4 I External


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns TMS320C5x architecture diagram linear convolution code in TMS320C50 TMS320LC51 TMS320LC50 TMS320C52 TMS320C51 TMS320C50 TMS320C25 TMS320 TMS320BC51PQ57
1995 - TMS320LC51

Abstract: No abstract text available
Text: peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational , ) description The TMS320C5x generation of the Texas Instruments (TITM ) TMS320 digital signal processors (DSPs , (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal Interrupt , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal External


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns TMS320LC51
1996 - instruction set of TMS320C5x

Abstract: TMS320 TMS320C52 TMS320C52-57 TMS320C52-80 dsp tms320c5x instruction set tms320 designers notebook disadvantage of crystal oscillator
Text: TMS320 DSP Number 47 DESIGNERS NOTEBOOK TMS320C5x Clock Modes Contributed by Joe George , (PLL). Solution The clock options and the fully-static design of the C5x give the user a lot of flexi bility. As can be seen in Appendix A-10 of the C5x Users Guide, two pins CLKMD1 and CLKMD2 , the part is in reset ( =0). A common mode is to run the CPU at a rate that is a divide-by-two of , clock mode input frequency to instruction cycle frequency, it makes the most sense to refer to the


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PDF TMS320 TMS320C5x 25-ns 40-MHz 50-ns instruction set of TMS320C5x TMS320C52 TMS320C52-57 TMS320C52-80 dsp tms320c5x instruction set tms320 designers notebook disadvantage of crystal oscillator
1995 - S-PQFP-G132 Package

Abstract: tms320bc53pq57 TMS320C50PQ57 TMS320LC51
Text: peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational , ) description The TMS320C5x generation of the Texas Instruments (TITM ) TMS320 digital signal processors (DSPs , (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal Interrupt , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal External


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns S-PQFP-G132 Package tms320bc53pq57 TMS320C50PQ57 TMS320LC51
1995 - TMS320LC51

Abstract: No abstract text available
Text: peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational , ) description The TMS320C5x generation of the Texas Instruments (TITM ) TMS320 digital signal processors (DSPs , (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal Interrupt , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal External


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns TMS320LC51
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