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LTC1706EMS-61 Linear Technology LTC1706-61 - 5-Bit VID Voltage Programmer for AMD Opteron CPUs; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LTC1753CSW Linear Technology LTC1753 - 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium® II Processor; Package: SO; Pins: 20; Temperature Range: 0°C to 70°C
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LTC1706EMS-63#PBF Linear Technology LTC1706-63 - 5-Bit VID Voltage Programmer for Sun CPUs; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LTC3733CG#TRPBF Linear Technology LTC3733 - 3-Phase, Buck Controllers for AMD CPUs; Package: SSOP; Pins: 36; Temperature Range: 0°C to 70°C
LTC3733CUHF-1#TR Linear Technology LTC3733 - 3-Phase, Buck Controllers for AMD CPUs; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C

instruction set of TMS320C50 DSP PROCESSOR Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1995 - addressing modes of TMS320C50

Abstract:
Text: architecture and the algebraic syntax of the instruction set for the ADSP-2115 processor allows the programmer , the instruction of one DSP device is not necessarily equivalent to that of another DSP device, a , simultaneous circular buffers of the ADSP-2115. Also, due to instruction pipelining of the TMS320C50 , the , implementation of many DSP algorithms as compared to the fixed sequence, end-toend architecture of the TMS320C50 , . Table II. Summary of Data Addressing Capabilities DSP Requirement ADSP-2115 TMS320C50


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PDF AN-393 ADSP-2115 TMS320C5x) TMS320C52 ADSP-2115, ADSP-2115 addressing modes of TMS320C50 instruction set of TMS320C50 DSP PROCESSOR architecture of TMS320C50 TMS320C50 C5257 TMS320C5x matrix multiplication adsp 21xx processor advantages architectural design of TMS320C50 instruction set of TMS320C50 32 BIT PROCESSOR TMS320C5x architecture diagram
addressing modes of TMS320C50

Abstract:
Text: , MASSACHUSETTS 02062-9106 • 617/329-4700 Considerations for Selecting a DSP Processor (ADSP-2101 vs. TMS320C50 , characterized mainly by its MIPS rate. Since the instruction of one DSP device is not necessarily equivalent to , to instruction pipelining of the TMS320C50 , the auxiliary registers cannot be used for as many as two , Diagram of TMS320C50 Address Generation Circuit TMS320C50 Addressing Instructions The instruction , processor can determine whether a loop hould terminate and address the next instruction (either the top of


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PDF AN-233 ADSP-2101 TMS320C50) TMS320C50. addressing modes of TMS320C50 architectural design of TMS320C50 instruction set tms320c50 block diagram of TMS320CSx tms320c50 mnemonic TMS320C50 architecture instruction set of TMS320C50 DSP PROCESSOR architecture of TMS320C50 architecture of TMS320C50 applications TMS320C50 addressing modes with examples
architecture of TMS320C50

Abstract:
Text: , MASSACHUSETTS 02062-9106 • 617/329-4700 Considerations For Selecting a DSP Processor (ADSP-2101 vs. TMS320C50 , speed or MIPS (Millions of instructions per second) rating alone. Many times a DSP processor is characterized mainly by its MIPS rate. Since the instruction of one DSP device is not necessarily equivalent to , implementation of many DSP algorithms as compared to the fixed sequence, end-to-end architecture of the TMS320C50 , simultaneous circular buffers of the ADSP-2101. Also, due to instruction pipelining of the TMS320C50 , the


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PDF AN-233 ADSP-2101 TMS320C50) architecture of TMS320C50 addressing modes of TMS320C50 architecture of TMS320C50 applications instruction set of TMS320C50 DSP PROCESSOR architectural design of TMS320C50 TMS320C50 instruction set tms320c50 TMS320C50 architecture PAER tms320c50 mnemonic description
1997 - instruction set of TMS320C50 DSP PROCESSOR

Abstract:
Text: = 10 MHz TMS320C50 Master Clock TMS320C50 Instruction Cycle = 20.000 MHz = 20 MHz AIC , TMS320C50 Instruction Cycles The maximum AIC conversion frequency is 25 kHz, which gives a minimum period of 40 µsec between data samples. When the Primary data word command bits are set to 11b, the , XINT signal occurs approximately 15 (TMS320C26) or 154 ( TMS320C50 ) instruction cycles before the FSX goes LOW to signal start of transmission (best case - assuming that the DSP and AIC Master Clocks are


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PDF TMS320 TMS320C2x/C5x SPRA221 instruction set of TMS320C50 DSP PROCESSOR instruction set tms320c50 TMS320C26 tms320c2x TMS320C50 tms320c50 application TMS320C50 specifications TLC32046
1997 - addressing modes of TMS320C50

Abstract:
Text: Analog-to-Digital Converter to the TMS320C50 DSP iii Figures List of Figures 1 2 3 4 5 6 7 8 , analog-to-digital converter (ADC) and the TMS320C50 digital signal processor ( DSP ). It also provides reference , instruction cycles of the load DXR command (See the ADC/ DSP section). This maximum time is shown as FSDmax in , Interfacing the TLV1544 Analog-to-Digital Converter to the TMS320C50 DSP Literature Number , . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TLV1544 to TMS320C50 DSP Interface


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PDF TLV1544 TMS320C50 SLAA025 TLV1544 0800h, 0030h 0830h, 0200h 0100h, addressing modes of TMS320C50 0834H instruction set of TMS320C50 DSP PROCESSOR TLV1548
1997 - LM093XMLN

Abstract:
Text: ) TMS320C50 digital signal processor ( DSP ). This can be seen in its I/O functions and adapters designed to , the TMS320C50 DSP SPRA302 Processing Parameters of Channels in the User Interface CHVOL , Wiring and Layout (2 of 3) Designing an Audioprocessor for Automobiles with the TMS320C50 DSP 31 , Disclaimer: This document was part of the DSP Solution Challenge 1995 European Team Papers. It , Audioprocessor for Automobiles with the TMS320C50 DSP Author: Piispala EFRIE, France December 1995


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PDF TMS320C50 SPRA302 warr10k LM093XMLN RG1 7805 7805 rg1 hitachi LM093XMLN zener diode 5v1 car battery charger test report PCB digital echo sound 1n4148 zener diode audioprocessor 74HC373 74hc374
1997 - LM093XMLN

Abstract:
Text: ) TMS320C50 digital signal processor ( DSP ). This can be seen in its I/O functions and adapters designed to , the TMS320C50 DSP SPRA302 Processing Parameters of Channels in the User Interface CHVOL , Wiring and Layout (2 of 3) Designing an Audioprocessor for Automobiles with the TMS320C50 DSP 31 , Disclaimer: This document was part of the DSP Solution Challenge 1995 European Team Papers. It , Audioprocessor for Automobiles with the TMS320C50 DSP Author: Piispala EFRIE, France December 1995


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PDF TMS320C50 SPRA302 warr10k LM093XMLN hitachi LM093XMLN RG1 7805 7805 rg1 tm5320 bc558b car battery charger D811 1n4148 zener diode LM093
1997 - instruction set of TMS320C50 DSP PROCESSOR

Abstract:
Text: Analog-to-Digital Converter to the TMS320C50 DSP iii Figures List of Figures 1 2 3 4 5 6 7 8 , analog-to-digital converter (ADC) and the TMS320C50 digital signal processor ( DSP ). It also provides reference , instruction cycles of the load DXR command (See the ADC/ DSP section). This maximum time is shown as FSDmax in , Interfacing the TLV1544 Analog-to-Digital Converter to the TMS320C50 DSP Literature Number , . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TLV1544 to TMS320C50 DSP Interface


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PDF TLV1544 TMS320C50 SLAA025 TLV1544 0800h, 0030h 0830h, 0200h 0100h, instruction set of TMS320C50 DSP PROCESSOR addressing modes of TMS320C50 adc mar TLV1544ADC TI AR7 TLV1548
1997 - FSK ask psk by matlab

Abstract:
Text: Instruments (TITM) TMS320C50 digital signal processor ( DSP ). The functions included /4 D-QPSK signal mapping , Disclaimer: This document was part of the First European DSP Education and Research Conference , the DSP program were derived using a Matlab program. This document was part of the first European , processing is advantageous as DSP techniques can then be applied. Baseband frequencies of up to a few , signalling set and this requires an increase in signal power at the transmitter. Classification of


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PDF TMS320C50 SPRA341 TM5320C50 FSK ask psk by matlab matlab ask fsk psk coherent digital modulation carrier ASK,PSK and FSK QPSK, FSK, ASK, PSK TMS320 matlab code for multipath channel implementation of qpsk modulator and demodulator FSK modulate by matlab book rAised cosine FILTER ASK modulator and demodulator circuit
1997 - pulse amplitude modulation matlab code

Abstract:
Text: Instruments (TITM) TMS320C50 digital signal processor ( DSP ). The functions included /4 D-QPSK signal mapping , Disclaimer: This document was part of the First European DSP Education and Research Conference , the DSP program were derived using a Matlab program. This document was part of the first European , processing is advantageous as DSP techniques can then be applied. Baseband frequencies of up to a few , signalling set and this requires an increase in signal power at the transmitter. Classification of


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PDF TMS320C50 SPRA341 TM5320C50 pulse amplitude modulation matlab code apsk matlab QPSK, FSK, ASK, PSK TMS320 matlab ask fsk psk coherent FSK ask psk by matlab low cost qpsk modulator instruction set of TMS320C50 DSP PROCESSOR modem interpolation timer filter FSK TMS320C50 specifications sampling code in tms320c50
1997 - Echo cancellation in tms320c50

Abstract:
Text: bounded by the available processor power. Designing an Echo Canceller System Using the TMS320C50 DSP , program modules were optimized to take advantage of the new facilities offered by the TMS320C50 DSP , from , Disclaimer: This document was part of the DSP Solution Challenge 1995 European Team Papers. It , Canceller System Using the TMS320C50 DSP Authors: Paulo Marques (pmarques@cc.isel.pt) Fernando Sousa , . 26 Designing an Echo Canceller System Using the TMS320C50 DSP Abstract This application


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PDF TMS320C50 SPRA322 TMS32020" Echo cancellation in tms320c50 addressing modes of TMS320C50 dsp based echo cancellation instruction set of TMS320C50 DSP PROCESSOR acoustic echo canceller using NLMS Algorithm adaptive FILTER implementation in c language Echo canceler adaptive filter algorithm TMS320C50 specifications
1998 - instruction set of TMS320C50 DSP PROCESSOR

Abstract:
Text: TMS320C50 DSP is a 16-bit fixed-point, static CMOS digital signal processor . The combination of an advanced , TMS320C50 DSP iii Figures List of Figures 1 Data Acquisition System Using the TLV1544 ADC . . . . , the timing diagram of a data transfer between the TLV1544 ADC and the TMS320C50 DSP through the DSP , Analog-to-Digital Converter to the TMS320C50 DSP 13 ADC Overview Table 4. Benefits of the Individual , memory, and a highly specialized instruction set is the basis of the operational flexibility of this


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PDF TLV1544 TMS320C50 SLAA025A instruction set of TMS320C50 DSP PROCESSOR architecture of TMS320C50 addressing modes of TMS320C50 instruction set of TMS320C5x architecture of TMS320C50 applications instruction set tms320c50 tms320c50 PIN CONFIGURATION TLV1544 TLV1548
1997 - dsp based echo cancellation

Abstract:
Text: bounded by the available processor power. Designing an Echo Canceller System Using the TMS320C50 DSP , program modules were optimized to take advantage of the new facilities offered by the TMS320C50 DSP , from , only a small fraction of the total length. The system is based on the Texas Instruments TMS320C50 DSP , Disclaimer: This document was part of the DSP Solution Challenge 1995 European Team Papers. It , Canceller System Using the TMS320C50 DSP Authors: Paulo Marques (pmarques@cc.isel.pt) Fernando Sousa


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PDF TMS320C50 SPRA322 TMS32020" dsp based echo cancellation Echo cancellation in tms320c50 instruction set of TMS320C50 DSP PROCESSOR adaptive FILTER implementation in c language addressing modes of TMS320C50 TMS32020 TMS320 NLMS Algorithm MAN29 TMS320C50 specifications
1998 - instruction set of TMS320C50 DSP PROCESSOR

Abstract:
Text: TMS320C50 DSP is a 16-bit fixed-point, static CMOS digital signal processor . The combination of an advanced , TMS320C50 DSP iii Figures List of Figures 1 Data Acquisition System Using the TLV1544 ADC . . . . , the timing diagram of a data transfer between the TLV1544 ADC and the TMS320C50 DSP through the DSP , Analog-to-Digital Converter to the TMS320C50 DSP 13 ADC Overview Table 4. Benefits of the Individual , memory, and a highly specialized instruction set is the basis of the operational flexibility of this


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PDF TLV1544 TMS320C50 SLAA025A instruction set of TMS320C50 DSP PROCESSOR addressing modes of TMS320C50 fxs 100 10 TLV1544 TLV1548
1997 - linear convolution code in TMS320C50

Abstract:
Text: Implementing a Single Channel Active Adaptive Noise Canceller with the TMS320C50 DSP Starter Kit , Control Phase, Executed After the Identification and Until a Reset of the DSP . 21 Implementing a Single Channel Active Adaptive Noise Canceller with the TMS320C50 DSP Starter , noise canceller with the low cost Texas Instruments (TITM) TMS320C50 (`C50) digital signal processor , generation of this acoustic interference wave that is processed by the DSP . The DSP performs the real-time


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PDF TMS320C50 SPRA285 1988a. TMS320C5x linear convolution code in TMS320C50 linear convolution in TMS320C50 sampling code in tms320c50 spra285 2448h adaptive noise cancellation IFR 6000 feedback LMS adaptive Filters TMS320C50 specifications TMS320C5x random noise generator
1997 - instruction set of TMS320C50 DSP PROCESSOR

Abstract:
Text: Implementing a Single Channel Active Adaptive Noise Canceller with the TMS320C50 DSP Starter Kit , Control Phase, Executed After the Identification and Until a Reset of the DSP . 21 Implementing a Single Channel Active Adaptive Noise Canceller with the TMS320C50 DSP Starter , noise canceller with the low cost Texas Instruments (TITM) TMS320C50 (`C50) digital signal processor , generation of this acoustic interference wave that is processed by the DSP . The DSP performs the real-time


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PDF TMS320C50 SPRA285 1988a. TMS320C5x instruction set of TMS320C50 DSP PROCESSOR 1C10H TMS320C50 specifications TMS320 TLC32040 sampling code in tms320c50 instruction set tms320c50 feedback LMS adaptive Filters D255
1995 - TMS320C5x random noise generator

Abstract:
Text: Hardware Design of TMS320C50 Based DSP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ) 10 VDD = 5 V 2.3 ns 4.4 ns 5.6 ns 4.2 Hardware Design of TMS320C50 Based DSP System A relatively simple yet powerful DSP system can be built using a TMS320C50 family digital signal processor and , . . . . . . . . 4.3.2 Interfacing to a 3-V DSP Processor . . . . . . . . . . . . . . . . . . . . . , designed for ease of connection to many DSP chips. The internal circuit configuration and the performance


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PDF TLC320AC01 SLAA006 TMS320C5x random noise generator TLC320AC01 operational amplifier discrete schematic TMS320C50 TLE2682 TLC2272 schematic diagram dc inverter N28F001BX-B120 MAX410 instruction set of TMS320C50 DSP PROCESSOR
1995 - N28F001BX-B120

Abstract:
Text: Hardware Design of TMS320C50 Based DSP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ) 10 VDD = 5 V 2.3 ns 4.4 ns 5.6 ns 4.2 Hardware Design of TMS320C50 Based DSP System A relatively simple yet powerful DSP system can be built using a TMS320C50 family digital signal processor and , . . . . . . . . 4.3.2 Interfacing to a 3-V DSP Processor . . . . . . . . . . . . . . . . . . . . . , designed for ease of connection to many DSP chips. The internal circuit configuration and the performance


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PDF TLC320AC01 SLAA006 14-bit TLC320AC01 SLAS057A TMS320C2x SPRU014C TMS320C5x SPRU056B TMS320 N28F001BX-B120 instruction set of TMS320C50 DSP PROCESSOR lm393 square wave operational amplifier discrete schematic TLC2272 SLAS057A TMS320C50 MAX410 ICL7660
1995 - TMS320C50 square wave generator routine

Abstract:
Text: Hardware Design of TMS320C50 Based DSP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ) 10 VDD = 5 V 2.3 ns 4.4 ns 5.6 ns 4.2 Hardware Design of TMS320C50 Based DSP System A relatively simple yet powerful DSP system can be built using a TMS320C50 family digital signal processor and , . . . . . . . . 4.3.2 Interfacing to a 3-V DSP Processor . . . . . . . . . . . . . . . . . . . . . , designed for ease of connection to many DSP chips. The internal circuit configuration and the performance


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PDF TLC320AC01 SLAA006 14-bit TLC320AC01 SLAS057A TMS320C2x SPRU014C TMS320C5x SPRU056B TMS320 TMS320C50 square wave generator routine instruction set of TMS320C50 DSP PROCESSOR TLC320AC TLC2272 SN74ACT Pulse width modulation TMS320C50 N28F001BX-B120 MAX410 white noise generator
1995 - addressing modes of TMS320C50

Abstract:
Text: . . . . . . . . . . . . 4.2 Hardware Design of TMS320C50 Based DSP System . . . . . . . . . . . . . , ) 10 VDD = 5 V 2.3 ns 4.4 ns 5.6 ns 4.2 Hardware Design of TMS320C50 Based DSP System A relatively simple yet powerful DSP system can be built using a TMS320C50 family digital signal processor and , . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Interfacing to a 3-V DSP Processor . . . , . It has a synchronous, serial, digital interface designed for ease of connection to many DSP chips


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PDF TLC320AC01 SLAA006 addressing modes of TMS320C50 TLC320AC01 N28F001BX-B120 operational amplifier discrete schematic TMS320C5x random noise generator circuit diagram of digital hearing aid hearing aid amplifiers loop instruction set of TMS320C50 DSP PROCESSOR TMS320C5x square wave pulse train MAX410
1995 - block diagram of TMS320C5X starter kit

Abstract:
Text: that of an earlier TI DSP , the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational , (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal Interrupt , branches Timer output signal. Indicates output of internal timer Instruction acquisition signal External


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PDF TMS320C5x, TMS320LC5x SPRS030A 16-Bit TMS320C5x 50-ns block diagram of TMS320C5X starter kit PZ S-PQFP-G100 Package footprint abstract for wireless technology in ieee format BSDL tms320 instruction set of TMS320C5x SPRA145 SPRA136 S-PQFP-G128 instructions rpt tms320c50 XDS510PP
1995 - dsp processor Architecture of TMS320C5X

Abstract:
Text: algorithms. Table I. Comparison of Fixed-Point DSP Costs and Features DSP Processor ADSP , systems-DSP instruction rate and decode logic. At DSP instruction rates of 25 MIPS and higher, SRAM with , TMS320C52 processor . One technique for reducing DSP overhead (the number of DSP cycles/access) related , comparison features for the ADSP-2181 processor . If you need to support any of the typical DSP algorithms , use the ADSP-2181 Digital Signal Processor for your high performance, fixed-point DSP applications


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PDF AN-400 ADSP-2181? ADSP-2181 ADSP-2181, TMS320C5x, DSP56000 ADSP-2171/81 DSP56000/DSP56001 dsp processor Architecture of TMS320C5X "analog devices" adsp 2181 and application notes architecture of TMS320C53 tms320c5x on chip peripherals "analog devices" adsp 2181 and byte DMA DSP56000UM gsm modem interfacing with dsp processor TMS320C53-Based AN-400
instruction set of TMS320C5x

Abstract:
Text: Instruction Set C.3 Instruction Set The TMS320C5x instruction set is a superset of the TMS320C25 instruction set . The instruction set of the TMS320C25 is upward source-code compatible. This means that all of the , the instruction set , a number of different instructions are combined into single new instructions with , TMS320 processor families. Note that the TMS320C50 and TMS320C51 have the same features with the exception of memory map; so within this appendix, any reference to TMS320C5x applies to both TMS320C50


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PDF TMS320C5X TMS320C25 TMS320 TMS320C50 TMS320C51 andTMS320C51 instruction set of TMS320C5x architecture of TMS320C5x TMS320C5X addressing modes tms320c5x on chip peripherals instruction set tms320c50 tms320c5x instruction set addressing modes of TMS320C50 addressing modes of TMS320C5X use ds-88 TMS320C5x architecture
1997 - tms320c50 application

Abstract:
Text: connected to the DSP through the TMS320C50 serial port as shown below in Figure 1. Figure 1. Hardware , The TMS320C50 serial port must be initialized by modifying the Serial-Port-Control register (SPC) of the DSP . The SPC is described on page 5-18 of the TMS320C5x Users Guide. In order to transmit and , the AIC is connected to the BR (Bus Request) pin of the TMS320C50 . The BR pin is driven low when , TMS320 DSP DESIGNER'S NOTEBOOK Initializing the TMS320C5x DSK Board APPLICATION BRIEF


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PDF TMS320 TMS320C5x SPRA253 tms320c50 application sampling code in tms320c50 instruction set tms320c50 TMS320C50 tms320c50 PIN CONFIGURATION spra253 TMS320C50 specifications
1997 - doppler radar

Abstract:
Text: in the TMS320C50 instruction set . This formula is computed on the 16 range cells * 2 ( Q and I parts , Disclaimer: This document was part of the DSP Solution Challenge 1995 European Team Papers. It , same real time specifications because of its improvements. This document was an entry in the 1995 DSP , concept of a low cost radar, specially designed for the TEXAS INSTRUMENTS DSP SOLUTIONS CHALLENGE. The , intelligent radar processing, made of multiprocessors DSP chips. The objective product cost is under 80.000


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PDF SPRA299 doppler radar pulse doppler radar Monopulse radar circuit component sensor doppler array radar dsp processor diagram radar circuit Ground Radar diagram AXIR RADAR Doppler radar dsp processor
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