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Part Manufacturer Description Datasheet Download Buy Part
LTC2656CIFE-L16#TRPBF Linear Technology LTC2656 - Octal 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C
LT1126CJ8 Linear Technology IC DUAL OP-AMP, 200 uV OFFSET-MAX, 65 MHz BAND WIDTH, CDIP8, 0.300 INCH, HERMETIC, CERAMIC, DIP-8, Operational Amplifier
LT1057CJ8 Linear Technology IC DUAL OP-AMP, 1400 uV OFFSET-MAX, 5 MHz BAND WIDTH, CDIP8, 0.300 INCH, HERMETIC SEALED, CERDIP-8, Operational Amplifier
DC1746A-B Linear Technology EVALUATION KIT LOW EM1 LTM2881-5
LT685CH Linear Technology IC COMPARATOR, 2500 uV OFFSET-MAX, 5.5 ns RESPONSE TIME, MBCY10, METAL CAN, TO-5, 10 PIN, Comparator
LTC2262CUJ-12#TRPBF Linear Technology LTC2262-12 - 12-Bit, 150Msps Ultralow Power 1.8V ADC; Package: QFN; Pins: 40; Temperature Range: 0°C to 70°C

ic hec 4xxx Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
16M X 32 SDR SDRAM

Abstract: SiliconTech SDR SDRAM CHIP ic 8 pin with number 1 is vss sdr sdram cmos 4XXX power 54pin TSOP SDRAM ic pin diagram
Text: T8S648- 4xxx 16M X 8 Bits x 4 Banks SDR SDRAM IC Tower FEATURES GENERAL DESCRIPTION · · The SiliconTech T8S648- 4xxx is a 16M x 8 bits x 4 banks Single Data Rate (SDR) Synchronous Dynamic RAM (SDRAM) IC Tower. The IC Tower consists of two 3.3V CMOS 16M x 4 bits x 4 banks SDRAMs in 54 , IC TOWER T8S648- 4xxx ORDERING INFORMATION Please check the current revision of the IC Tower , ) All inputs are sampled at the positive going edge of the system clock TSOP IC Tower Stack The two


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PDF T8S648-4xxx T8S648-4xxx 54-pin 400-mil cycles/64ms 61000-01093-xxx) A0-A12, 16M X 32 SDR SDRAM SiliconTech SDR SDRAM CHIP ic 8 pin with number 1 is vss sdr sdram cmos 4XXX power 54pin TSOP SDRAM ic pin diagram
PTD4061-4XXX

Abstract: HI-TECH c18 G957 IEC825
Text: www.neophotonics.com VER000/ 190307 PTD4061- 4XXX (+) 2.5Gbps DWDM SFP Transceiver 1 1.1 , : +86 755 26748186 Email: sales@neophotonics.com.cn PTD4061- 4XXX (+) 2.5Gbps DWDM SFP Transceiver , Tel: +86 755 26748283(7) Fax: +86 755 26748186 Email: sales@neophotonics.com.cn PTD4061- 4XXX (+ , Tel: +86 755 26748283(7) Fax: +86 755 26748186 Email: sales@neophotonics.com.cn PTD4061- 4XXX (+ , ) Fax: +86 755 26748186 Email: sales@neophotonics.com.cn PTD4061- 4XXX (+) 2.5Gbps DWDM SFP


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PDF VER000/ PTD4061-4XXX( 100GHz PTD4061-4XXX HI-TECH c18 G957 IEC825
4067B

Abstract: 4097B hcc4067b SS1G ci 4067
Text: voltage values are referred to Vss pin voltage ORDERING NUMBERS: HCC 4XXX BD for dual in—line ceramic package HCC 4XXX BF for dual in—line ceramic package, fritseal HCC 4XXX BK for ceramic flat package HCF 4XXX BF for dual in—line ceramic package, frit seal HCF 4XXX BE for dual in—line plastic package 17 , (dimensions in mm) Dual in-line ceramic package for HCC 4XXX BD 12.8 , X » co pj t Dual ¡ri-line ceramic frit-seal Dual in-line plastic package package for HCC/HCF 4XXX BF for HCF 4XXX BE 025


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PDF 4067B 4097B 4067B 16-CHANNEL 4097B 4067B, 4097B. hcc4067b SS1G ci 4067
Not Available

Abstract: No abstract text available
Text: TIN G A P P LIC A T IO N S F U L L Y S T A T IC O P E R A T IO N DC TO 10 MHz (TYP.) (® V DD= 10V , M E T R IC A L O UTPUT C H A R A C T E R IS T IC S Q U IESC ENT C U R R E N T SPECIFIED TO 20V FOR HCC DEVICE 5V, 10V, A N D 15V P A R A M E T R IC R A T IN G INPUT C U R R E N T OF 100 n A A T 18V , DESCRIPTIO N OF " B " SERIES CMOS D E V IC E S " The H C C /4 0 3 2 B /4038B (extended tem perature range) and HCF 4032B /4038B (interm ediate tempera­ tu re range) are m o n o lith ic integrated circuits


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PDF
Not Available

Abstract: No abstract text available
Text: ITH 8 DECODED OUTPUTS • • • • • • • • F U L L Y S T A T IC O PERATION M E D IU M SPEED O P E R A T IO N -1 2 MHz (TYP.) A T V DD= 10V S T A N D A R D IZ E D S Y M M E T R IC A L O UTPUT C H A R A C T E R IS T IC S Q UIESCEN T C U R R E N T SPECIFIED TO 20V FOR HCC D EVICE , R R E N T 5V, 10V, A N D 15V P A R A M E T R IC R A T IN G S MEETS A L L R EQ U IR E M E N TS OF , " B " SERIES CMOS D E V IC E S " The HCC 4017B /4022B (extended tem perature range) and HCF 4017B


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PDF 4017B 4017B 4022B
Not Available

Abstract: No abstract text available
Text: R D IZ E D S Y M M E T R IC A L O UTPUT C H A R A C T E R IS T IC S Q UIES C EN T C U R R E N T SPECIFIED TO 2 0 V FOR HCC DEVICE 5V , 10V, A N D 15V P A R A M E T R IC R ATIN G S IN PU T C U R R E N T , IFIC ATIO N S FOR DESCRIPTION OF " B " SERIES CMOS D E V IC E S " The HCC 4000B, HCC 4 0 0 1 B, HCC , (interm ediate tem perature range) are m o n o lith ic inte­ grated c irc u it, available in 14 , HCC HCC HCF HCF HCF 4XXX BD fo r dual in -lin e ceramic package 4XXX BF fo r dual in -lin e


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PDF 4000B 4001B 4002B 4025B
Not Available

Abstract: No abstract text available
Text: ro e le c tro n ic s Phoenix, A Z * (602)437-1520 WHITE /MICROELECTRONICS W M D4M 4-XXX , Connected M s CAS Vcc GND NC J a n u a ry 1998 1 W h ite M ic ro e le c tro n ic s Phoenix, A , capacitance. W h ile M ic ro e le c tro n ic s Phoenix, A Z * (602)437-1520 2 a WHITE MICROELECTRONICS W M D4M 4-XXX DC CHARACTERISTICS (VCC= 5.0V, T a = -55°C to +125°C) Parameter High Level , V o l. (max). 3 W h ite M ic ro e le c tro n ic s Phoenix, A Z * (602)437-1520 a


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PDF 100ns
Not Available

Abstract: No abstract text available
Text: a typical resistive load circuit. ATE tester includes jig capacitance. W h ile M ic ro e le c tro n ic s Phoenix, A Z * (602)437-1520 2 a WHITE MICROELECTRONICS WM DE4M 4-XXX DC , ic ro e le c tro n ic s Phoenix, A Z * (602)437-1520 a WHITE /MICROELECTRONICS WM DE4 M 4-XXX , h ite M ic ro e le c tro n ic s Phoenix, A Z * (602)437-1520 a Param eter Power Dissipation , V o l. (max). 3 W h ite M ic ro e le c tro n ic s Phoenix, A Z * (602)437-1520 a Param


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PDF 100ns
4032B

Abstract: ic 4038
Text: M C O M P L E M E N T IN G A P P L IC A T IO N S F U L L Y S T A T IC O P E R A T IO N DC TO 10 MHz , IN G S T A N D A R D IZ E D S Y M M E T R IC A L O U T P U T C H A R A C T E R IS T IC S Q U IE S C E N T C U R R E N T S P E C IF IE D TO 20V FO R HCC D E V IC E 5V, 10V, A N D 15V P A R A M E T R IC R A T IN G IN P U T C U R R E N T O F 100 nA A T 18V and 2 5 °C F O R HCC D E V IC E 100% T E S T E D , IV E S T A N D A R D No. 13A, "S T A N D A R D S P E C IF IC A T IO N S F O R D E S C R IP T IO N O F


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PDF 403SB 4032B ic 4038
1996 - 7824 n3

Abstract: UC 3854 digital power ATM25 PE-67588 TLA-6M102 4-12PHY PHA50
Text: .35 3.2.6 HEC .36 9 3.2.7 .36 .37 3.3 ATM UTOPIA. . 3.3.1 .37 3.3.2 .38 , .41 3.5 CPU.42 3.5.1 .43 3.5.2 .44 3.6 .45 3.7 .45 3.7.1 LOS.45 3.7.2 HEC 4B5B , , Maintenance, HEC 4B5B JTAGIEEE1149.1- 3.3 V±5% 1.2 µPD98408GD-LML 208 QFP28mm , 4B/5B ( ) CPU TC CPU NRZI NRZI HEC HEC ATM , IC /RCLK5 IC /TDATA0 IC /RDATA4 IC /RDATA5 IC /TDATA1 IC /TDATA2 IC /TDATA3 IC /TDATA4 PMDONLY 8


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PDF PD98408 T20TM S11409JJ3V0UM00 NEASCOT-T20 24NEC 7824 n3 UC 3854 digital power ATM25 PE-67588 TLA-6M102 4-12PHY PHA50
Not Available

Abstract: No abstract text available
Text: TO ORDER CODE: 571 - 4XXX - 01 - XX - XX C O D E D D A S H No. -011 Silver -051 Electro-Solder In su la to r C o lo u r -19 I White FLA S H O VER B A S IC P A R T No. O.A. FO R PAN , T H IC K N E S S 571 -4 1 4 0 571 - 4281 -01 .421 -01 (10,69) .125 (0,79) to 2,77


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2002 - t6634

Abstract: atm receiver multi-bit error header XRT73L00 XRT7300 XRT72L71IQ XRT72L71 GR-499-CORE CRC-10 0X00 SEM t11
Text: 160 PQFP -40°C to +85°C 3 XRT72L71 DS3 ATM UNI/CLEAR CHANNEL FRAMER IC áç REV , . 40 I áç DS3 ATM UNI/CLEAR CHANNEL FRAMER IC XRT72L71 REV. 1.1.0 CLEAR CHANNEL , /CLEAR CHANNEL FRAMER IC áç REV. 1.1.0 TABLE 40: PMON FEBE EVENT COUNT REGISTER - LSB , . TABLE 47: PMON SINGLE-BIT HEC ERROR COUNT - MSB . TABLE 48: PMON SINGLE-BIT HEC ERROR COUNT - LSB


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PDF XRT72L71 XRT72L71 t6634 atm receiver multi-bit error header XRT73L00 XRT7300 XRT72L71IQ GR-499-CORE CRC-10 0X00 SEM t11
VNE-50

Abstract: VIT-75
Text: Incoming & Outgoing Telco Circuits A L L E N A V IO N IC S , IN C 224 East Second Street. Mmpohi. NY 1150* · rFL i 5 16 12A8-8080 · f~AX :516 > ,'4/-6724 - ^ f ELIMINATOR MODii HEC , e l im in a t o r vnD rlH tC ALLEN AVIONICS,INC. A! HUM ELIM INATOR S HEC -500 50 Unbalanced HEC -1000 75 Unbalanced HEC -2000 75 Unbalanced HEC -2000H 75 Unbalanced HEC -3000 75 Unbalanced IM , HEC -1000, HEC -2000, HEC -2000H. VNE-75 and VIT-75. (Left) Rack Card with two units moun 11 IH


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PDF 12A8-8080nduce HEC-2000 HEC-2000H VNE-50 VIT-75
2007 - 0x1758

Abstract: dmo 365 r dmo 365 CIRCUIT DIAGRAM UPS XRT79L71IB XRT79L71 GR-499-CORE GR-253 17X17 775 intel
Text: XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC JUNE 2007 GENERAL DESCRIPTION , -CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION · Supports ATM cell payload , _8 P R XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP , (TOP VIEW) XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP , IC - REGISTER/MAP DESCRIPTION TABLE OF CONTENTS GENERAL DESCRIPTION


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PDF XRT79L71 XRT79L71 0x1758 dmo 365 r dmo 365 CIRCUIT DIAGRAM UPS XRT79L71IB GR-499-CORE GR-253 17X17 775 intel
2000 - AA23

Abstract: CRC-10 GR-499-CORE XRT72L73IB XRT73L03 XRT73L04 prbs pattern generator
Text: áç XRT72L73 PRELIMINARY THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER IC DECEMBER 2000 , www.exar.com áç XRT72L73 THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER IC PRELIMINARY REV. P1.0.1 FIGURE 2. BLOCK DIAGRAM OF THE XRT72L73 DS3 UNI IC A[10:0] WR_RW RD_DS CS ALE_AS Reset Int D[15:0 , XRT72L73 THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER IC PRELIMINARY REV. P1.0.1 SYSTEM , . FUNCTIONAL DESCRIPTION The XRT72L73 DS3 ATM UNI/Framer IC can be configured to operate in either the "ATM


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PDF XRT72L73 XRT72L73 AA23 CRC-10 GR-499-CORE XRT72L73IB XRT73L03 XRT73L04 prbs pattern generator
A2H1

Abstract: No abstract text available
Text: . Specifically, cell delineation is performed by means of a Header Error Control ( HEC ) byte search. Cell rate , SIDE RTD(17-0) RCF1/RxCLAV R C F 2/R x E N B R C A V /R xS O C R IC LK RXF1 RXF2 RLOF Receive , searching for a valid Header Error Control ( HEC ) sequence. The extracted cells are optionally descrambled , cell rate to the line interface. The 48-byte cell payload may optionally be scrambled and a HEC byte , C H A R A C T E R IS T IC S Param eter Min Typ Max Unit Test Conditions Thermal resistance


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PDF TXC-051 144-pin TXC-05150-MB A2H1
1997 - atml

Abstract: PE-67588 TLA-6M102
Text: Command-Byte Insertion and Detection 4B5B Block Encoding and Decoding Cell Scrambling and Descrambling HEC , -32 3.7.1 LOS (Loss of Signal) Detection Function 3.7.2 HEC Error/4B5B Code Error Detection Function 3.7.3 , ) - 54 4.2.20 Self Test 1 (Internal HEC Error) Register (SELFTST1 , HEC generation/verification · CPU interface: Intel / Motorola selectable · STP and UTP (categories , OAM functions: Detection of Loss of Signal, detection of HEC error and 4B/5B code error · Test


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PDF S11409EJ2V0UMJ1 atml PE-67588 TLA-6M102
2005 - 0X1F65

Abstract: 0X1121
Text: .0.9 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION GENERAL , ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION PLCP frame and mapping of ATM cell , IC - REGISTER/MAP DESCRIPTION xr FIGURE 1. BLOCK DIAGRAM OF THE XRT79L71 PLCP & Overhead , _3 RXOHFRAME PRELIMINARY 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION , /PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION xr GENERAL DESCRIPTION


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PDF XRT79L71 XRT79L71 0X1F65 0X1121
T 3105 001

Abstract: N2364 1H21 b2x48 invc 303 AC03 nec STM-16 S3044 S3043 BA 2H22
Text: .59 3-16.61 3-17.62 3-18.65 3-19 HEC .66 3-20.82 3-21.85 3-22.90 3-23.90 , Scramble Cell Mapping HEC Generation Cell Processor Block Idle Cell Drop Cell Descramble Cell Synchronization HEC Compare/Control Cell Processor Block Tx OAM Processor Frame , ] 5 3 JCK JTAG Interface JDI JRST_B JDO TLAIS TPAIS GND TLRDI TPRDI IC , GND 3 C01 IC 38 AF13 GND 73 D26 POUT0 4 D01 IC 39 AF14


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PDF PD98414 NEASCOT-P70TM) S14166JJ4V0UM00 S14166JJ4V0UM FAX044435-9608 T 3105 001 N2364 1H21 b2x48 invc 303 AC03 nec STM-16 S3044 S3043 BA 2H22
2000 - 0X00

Abstract: CRC-10 GR-499-CORE XRT72L71 XRT72L71IQ XRT7300 XRT73L00
Text: DESCRIPTION The XRT72L71 DS3 ATM UNI/Framer IC can be configured to operate in either the "ATM UNI" or in the , Delineation · Receive UTOPIA Interface Block ­ HEC Byte Verification of incoming cells (optional , Framer Block ­ User and OAM Cell Filtering (optional) · Capable of receiving data, from the LIU IC , of HEC Byte errors", "Change in LCD (Loss of Cell Delineation) condition" and "Receipt of OAM Cell , ) compute and insert the HEC (Header Error Check) byte. This HEC byte will be inserted into the fifth


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PDF XRT72L71 XRT72L71 0X00 CRC-10 GR-499-CORE XRT72L71IQ XRT7300 XRT73L00
NEC 08F

Abstract: d98411 5-2P65 MSP 044 K1T MOS IC TX RX 12d 12e h110d1 DLR30 ALP 102 B6 ALP 102 B4
Text: . 46 3-11 . 48 3-12 . 49 3-13 HEC . 50 3-14 HEC . 65 3-15 DCHPR DCHPMR , 205 8- 1 . 207 S12736JJ4V1UM 13 3- 1 . 47 3- 2 HEC . 51 , FIFO Overflow HEC Line AIS/Path AIS FIFO Line RDI/Path RDI APS 0.35 m CMOS , Block Tx Rx ATM Rx Block Rx Tx FIFO (8 cells) Tx ATM HEC Tx Tx BIP P/S P/S S/P Rx FIFO (8 cells) Rx ATM HEC Rx Rx BIP


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PDF PD98411 NEASCOT-P40 S12736JJ4V1UM00 S12736JJ4V1UM S12736JJ4V1UM FAX044435-9608 NEC 08F d98411 5-2P65 MSP 044 K1T MOS IC TX RX 12d 12e h110d1 DLR30 ALP 102 B6 ALP 102 B4
2000 - AA23

Abstract: CRC-10 GR-499-CORE XRT72L74IQ XRT73L04 2X54 ami c21
Text: . FUNCTIONAL DESCRIPTION The XRT72L74 DS3 ATM UNI/Framer IC can be configured to operate in either the "ATM , Cell Processor Block ­ Cell Delineation · Receive UTOPIA Interface Block ­ HEC Byte , Capable of receiving data, from the LIU IC , in either the "Single-Rail" or "Dual-Rail" mode. ­ OAM , upon "Detection of HEC Byte errors", "Change in LCD (Loss of Cell Delineation) condition" and , ) scramble the Cell Payload bytes and (optionally) compute and insert the HEC (Header Error Check) byte


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PDF XRT72L74 XRT72L74 AA23 CRC-10 GR-499-CORE XRT72L74IQ XRT73L04 2X54 ami c21
2003 - dmo 365 r

Abstract: RUR 117-5 E1 HDB3 GR-499-CORE GR-253 17X17 XRT79L71IB XRT79L71 PC403 0X1157
Text: áç PRELIMINARY XRT79L71 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC JUNE 2003 REV. P1 , ) 668-7017 · www.exar.com áç PRELIMINARY XRT79L71 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC REV , CHANNEL DS3/E3 ATM UNI/PPP COMBO IC áç XRT79L71 REV. P1.0.3 TABLE 1: PIN OUT OF THE XRT79L71 (TOP VIEW) XRT79L71 PRELIMINARY áç 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC REV. P1 , PRELIMINARY 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC XRT79L71 REV. P1.0.3 E3 LINE SIDE PARAMETERS


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PDF XRT79L71 XRT79L71 dmo 365 r RUR 117-5 E1 HDB3 GR-499-CORE GR-253 17X17 XRT79L71IB PC403 0X1157
1997 - HT-241

Abstract: BGA45 VCI-0-127 cen 496
Text: 0018h.146 4.3.9 HEC /CRC 001Ah.148 4.3.10001Ch.149 4.3.110020h.150 4.3.120024h. 151 4.3.13HEC , Buffer Memory Address RESET_B : Hardware Reset CBD87-CBD0 : Cell Buffer Memory Data Bus IC , I/O 73 RXDATA05 I 2 GND 38 CBD69 I/O 74 VDD 3 IC O 39 CBD66 I/O 75 GND 4 IC O 40 CBD63 I/O 76 RXCLAV0 5 CG I 41 IC O 77 VDD 6 IC O 42 CBD58 I/O 78 TXADDR01 O 7 JRST_B I


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PDF PD98410 X10TM S12523JJ2V1UM00 HT-241 BGA45 VCI-0-127 cen 496
1997 - D78 NEC

Abstract: PE-67588 TLA-6M102
Text: Command-Byte Insertion and Detection 4B5B Block Encoding and Decoding Cell Scrambling and Descrambling HEC , -32 3.7.1 LOS (Loss of Signal) Detection Function 3.7.2 HEC Error/4B5B Code Error Detection Function 3.7.3 , ) - 54 4.2.20 Self Test 1 (Internal HEC Error) Register (SELFTST1 , HEC generation/verification · CPU interface: Intel / Motorola selectable · STP and UTP (categories , OAM functions: Detection of Loss of Signal, detection of HEC error and 4B/5B code error · Test


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PDF d88-6130 D78 NEC PE-67588 TLA-6M102
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