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LTC2938CMS#PBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: 0°C to 70°C
LTC2939CMS#PBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C
LTC2938CMS#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: 0°C to 70°C
LTC2939CMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C
LTC2938HDE#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: DFN; Pins: 12; Temperature Range: -40°C to 125°C
LTC2939HMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C

ic 7483 pin configuration Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
7483N

Abstract:
Text: carry lookahead · See '283 for corner power pin version TYPE 7483 7 4LS 83A T Y P IC A L A D D T IM E S (T W O 8 - B IT WORDS) 23ns 25ns T Y P IC A L SU PP LY C U R R E N T (T O T A L ) 66 , 74LS ul ' 1 ul 2LS ul 1LSul 10 ul 10LSul 10LSul 5ul PIN CONFIGURATION LOGIC , Signelics Logic Products Adders 7483 , LS83A 4-Bit Full Adder Product Specification , LS05700S V cc = Pin 5 G N D -P in 12 December 4, 1985 5-120 853-0569 81501 Signetics Logic


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PDF LS83A LS83A 500ns 500ns 7483N ic 7483 pin configuration diagram 74LS83AN circuit diagram for IC 7483 full adder INTERNAL DIAGRAM OF IC 7483 ic 7483 ic 7483 full adder 7483 IC pin diagram for IC 7483 LSE B3
1995 - 7483 IC

Abstract:
Text: matched against any given application (see table) shift configuration and oscillates at about 12 kHz , amplitude stabilized phase shift sine wave oscillator which requires one IC package three transistors and , Sine Wave Generation Techniques Sine Wave Generation Techniques TL H 7483 ­ 1 FIGURE 1 , 7483 RRD-B30M115 Printed in U S A Sine-Wave-Generation Techniques Typical Amplitude Stability , circuit of Figure 4 Although complex in appearance this circuit requires just 3 IC packages Here a


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circuit diagram for IC 7483 full adder

Abstract:
Text: carry lookahead · See '283 for comer power pin version TYPE 7483 74LS83A TYPICAL ADD TIMES (TWO 8 - , -1.6m A I il. and a 74LS unit load (LSul) is 20 mA l|H and -0.4m A In. PIN CONFIGURATION LOGIC , S ignelics 7483 , LS83A Adders 4-Bit Full Adder Product Specification Logic Products , Signetics Logic Products P roduct S p ecification Adders 7483 , LS83A LOGIC DIAGRAM 7483 (13) L002B10S V cc " Pin 5 GND - Pin 12 { ) - Pin numbers LOGIC DIAGRAM December 4, 1985 5-121


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PDF LS83A LS83A 74LS83A 1N916, 1N3064, 500ns 500ns circuit diagram for IC 7483 full adder ic 7483 pin configuration diagram ic 7483 pin diagram ic 7483 full adder INTERNAL DIAGRAM OF IC 7483 pin configuration of ic 7483 pin diagram for IC 7483 for ic 7483 ic 7483 pin configuration 7483 IC
1995 - 7483 parallel adder

Abstract:
Text: the I/O pin to the PIA. t PIA Altera Corporation Dedicated input pad and buffer delay. t IN represents the time required for a dedicated input pin to drive the input signal into the programmable , delay. The delay from a dedicated input pin to any global control function in a macrocell or I/O , as preset, clear, and output enable. MAX 7000 devices only. t IC Array clock delay. The delay , Fast input delay. The delay from the I/O pin to the macrocell register when fast input registers are


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PDF 7000E, 7000S, 7483 parallel adder ic 7483 full adder 7483 IC 7483 4-bits parallel adder ttl 7483 of IC 7483 ic 7483 adder application of ic 7483 7483 IC APPLICATIONS X030
1995 - pin diagram for IC 7483

Abstract:
Text: is the delay from the I/O pin to the PIA. t PIA Altera Corporation Dedicated input pad and buffer delay. t IN represents the time required for a dedicated input pin to drive the input signal into , GLOB Global control delay. The delay from a dedicated input pin to any global control function in a , enable. t IC Array clock delay. The delay through a macrocell's clock product term to the register , input delay. The delay from the I/O pin to the macrocell register when fast input registers are used


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PDF 7000E, 7000S, 7000AE, 7000B pin diagram for IC 7483 data sheet ic 7483 ic 7483 ttl 7483 FULL ADDER 7483 IC 7483 parallel adder 7483 full adder application notes ic 7483 pin diagram 7483 logic diagram ic 7483 full adder
1995 - ic 7483 full adder

Abstract:
Text: from the I/O pin to the PIA. In MAX 5000 devices with a single logic array block (LAB), t IO is the delay from the I/O pin to the logic arrays. In Classic devices, t IO is the delay added to t IN. t PIA Altera Corporation The time required for a dedicated input pin to drive the true and , dedicated clock pin to a register's clock input. t LAC Logic array control delay. The AND array delay , IC Array clock delay. The delay through a macrocell's clock product term to the register's clock


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1995 - ic 7483 full adder

Abstract:
Text: IN t IO The time required for a dedicated input pin to drive the true and complement data input , as inputs. In multi-LAB MAX 5000 devices, t IO is the delay from the I/O pin to the PIA. In MAX 5000 devices with a single logic array block (LAB), t IO is the delay from the I/O pin to the logic arrays. In , from the dedicated clock pin to a register's clock input. Logic array control delay. The AND array , at the macrocell output. MAX 5000 devices only. t ICS t LAC t IC t CLR t PRE t LAD t RD


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1998 - ic 7483

Abstract:
Text: Timing 3/3 t ASU = ( t IN + t PIA + t LAD ) ­ ( t IN + t PIA + t IC ) + t SU t AH = ( t IN + t PIA + t IC ) ­ ( t IN + t PIA + t LAD ) + t H Clock-to-Output t CO1 , t IN + t PIA + t IC + t RD + ( t OD1 or t OD2 or t OD3 ) Altera Corporation AN94: Understanding MAX 7000 Timing 7483 TTL MAX+PLUS II .rpt 7483 TTL s1 s1 = OUTPUT , : Understanding MAX 7000 Timing 7483 TTL _X tSEXP 7483 s2 s2 _LC019 _EQ023 _X029 _X030


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PDF 7000EMAX 7000S -AN-094-01/J 7000E UnderstandX030 7483s2 ic 7483 7483 IC 7483 ttl data sheet ic 7483 application of ic 7483 ttl 7483 Datasheet of IC 7483 data sheet 7483 application of 7483 altera An94
1995 - application of ic 7483

Abstract:
Text: delay. In MAX 7000 devices, t IN represents the time required for a dedicated input pin to drive the , 5000 and Classic devices, t IN represents the time required for a dedicated input pin to drive the , the delay from the I/O pin to the PIA. In MAX 5000 devices with a single logic array block (LAB), t IO is the delay from the I/O pin to the logic arrays. In Classic devices, t IO is the delay added , . The delay from the dedicated clock pin to a register's clock input. MAX 5000 and Classic devices only


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PDF 7000E 7000S application of ic 7483 ic 7483 full adder ic 7483 7483 IC 4 bit full adder EPM5128 EPM5064 EPM5032 EP610I EP610 7483 IC APPLICATIONS
1995 - 7483 IC APPLICATIONS

Abstract:
Text: pin to drive the input signal into the programmable interconnect array (PIA) or into the global , pin to drive the true and complement data input signal into the logic array(s). I/O input pad and , devices, t IO is the delay from the I/O pin to the PIA. In MAX 5000 devices with a single logic array block (LAB), t IO is the delay from the I/O pin to the logic arrays. In Classic devices, t IO is the , dedicated clock pin to a register's clock input. MAX 5000 and Classic devices only. Global control delay


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PDF 7000E 7000S 7483 IC APPLICATIONS 7483 full adder 7483 IC 4 bit full adder EP610I
ic 7483 block diagram

Abstract:
Text: represents the time required for a dedicated input pin to drive the input signal into the programmable , time required for a dedicated input pin to drive the true and com plem ent data input signal into the , . In MAX 7000 and multi-LAB MAX 5000 devices, t j 0 is the delay from the I / O pin to the PIA. In MAX 5000 devices w ith a single logic array block (LAB), tjQ is the delay from the I / O pin to the logic , clock delay. The delay from the dedicated clock pin to a register's clock input. MAX 5000 and Classic


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PDF 7000E 7000S 500nd ic 7483 block diagram pin diagram for IC 7483 xor INTERNAL DIAGRAM OF IC 7483 pin diagram for IC 7483 7483 parallel adder pin diagram application of ic 7483 ic 7483 pin diagram pin diagram of ic 7483
ic 7483 full adder

Abstract:
Text: pad and buffer delay. f;\ r represents the time required for a dedicated input pin to drive the input , buffer delay. The f io delay applies to I/O pins used as inputs. t[Q is the delay from the I/O pin to the , path. Global control delay. The delay from a dedicated input pin to any global control function in a , ensure that the register correctly stores the input data. Fast input delay. The delay from the I/O pin to , output pin after the output buffer's enable control is disabled. Output buffer enable delay with the slow


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PDF 7000E, 7000S, ic 7483 full adder 7483 parallel adder application of ic 7483 ttl 7483 FULL ADDER
7483 adder/subtractor

Abstract:
Text: The time required for a dedicated input pin to drive the true and complement data input signal into , . In multi-LAB MAX 5000 devices, t K) is the delay from the I/O pin to the PI A. In MAX 5000 devices with a single logic array block (LAB), t]0 is the delay from the I/O pin to the logic arrays. In , delay. The delay from the dedicated clock pin to a register's clock input. Logic array control delay , . The delay required for high impedance to appear at the output pin after the output buffer's enable


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ic 7483 full adder

Abstract:
Text: dedicated input pin to drive the true and complement data input signal into the logic array(s). I/O input , , i/o is the delay from the I/O pin to the PIA. In MAX 5000 devices with a single logic array block (LAB), tjo is the delay from the I/O pin to the logic arrays. In Classic devices, tj0 is the delay , clock pin to a register's clock input. Logic array control delay. The AND array delay for register , impedance to appear at the output pin after the output buffer's enable control is disabled. Output buffer


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PDF
Not Available

Abstract:
Text: - ~ Housing and Strain Relief Clip— t h e r m o p la s t ic (b la c k ) Terminals— g o ld o v e r n ic k , v e r n ic k e l p la te o n t e r m in a t in g s id e 1 ,_ c .830 [21 0 8 ] I EMI Shield— n ic k e l p la te d d ie c a s tin g Loose Piece Preassembled Preassembled , 2.352 59.74 554350-1 2.946 74.83 B 2.205 56.01 554348-1 2.352 59.74 6-32 Hole , 3.20 52.96 2.700 2.946 .149 2.946 .126 74.83 3.78 74.83 3.20 68.58 R et : .014 [ar0


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PDF IEEE-488
7483 a

Abstract:
Text: fOD7 O p e r a tio n D e v ic e Example 3: Second Bit of 7483 TTL Macrofunction with Parallel , tio n D e v ic e Introduction A ltera d evices p ro v id e p red ictab le device perform an ce , in p ut p a d a n d bu ffer delay. This d elay a p p lie s to I /O pin s u sed a s in p uts, an d represen ts the tim e required for a sign al on an I / O pin to reach a row or colum n interconnect on the , u sed a s in p uts, an d represents the tim e required for a sign al on an I / O pin to reach the


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PDF
Not Available

Abstract:
Text: required for a signal on an I/O pin to reach a row or column interconnect on the FastTrackTM Interconnect , represents the time required for a signal on an I / O pin to reach the data input of an I / O register. f , dedicated input pin and used as a data input to a macrocell to reach a row interconnect on the FastTrack Interconnect. Dedicated input clock delay. The delay for a signal that originates from a dedicated input pin , originates from a dedicated input pin and is used as a macrocell register clear. Dedicated input I / O


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Not Available

Abstract:
Text: 0 0 0 5 ] MINIMUM THICK GOLD ON ACTION PIN AR EA OVER 1 .2 7 ¡jurr\[.0 0 0 0 5 0 ] MINIMUM THICK N IC K E L U N D E R P L A T E OVER ENTIRE TERMINAL. RETAINER - P O LYETHYLEN E, NATURAL , 13.59 [ . 535 ] [ 2.54/^m —4 . 5 7 /4n[.0 0 0 1 0 0 —. 0 0 0 1 8 0 ] PIN AREA , SHALL BE PER AMP SPEC THRU HOLE ON HOUSING P O S IT IO N 1 LO CATION. A S E LF- T A P PIN G , 553443-8 74.83 [2.946 8 3 .3 1 [3 .2 8 0] 50 553443-6 31 A 3 4- 40 UNC-2B 74.83


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PDF 31MAR2000
7483 parallel adder pin diagram

Abstract:
Text: the time required for a signal on an I/O pin to reach a row or column interconnect on the FastTrack , represents the time required for a signal on an I/O pin to reach the data input of an I/O register. tiNREG , input pin and used as a data input to a macrocell to reach a row interconnect on the FastTrack Interconnect. Dedicated input clock delay. The delay for a signal that originates from a dedicated input pin , originates from a dedicated input pin and is used as a macrocell register clear. Dedicated input I /O control


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ic 7483 BCD adder

Abstract:
Text: operation is perform ed on the negative going edge o f the clock pulse. LOG IC SY M B O L 4 10 3 11 LOG IC D IA G R A M 93176/54176, 74176 Pin nu m b ers are show n fo r D IP o n ly . CO , divide-by-tw o and divide-by-five configuration , or in the bi-quinary mode. The 9 3 1 77/54177, 74177 can be , N T IF IC A T IO N T E M P E R A T U R E ^ D E V ^ E ^ PACKAGE RANGE TYPE TYPE PACKAGE CROSS , 7400 8200 8210 8211 8213 8220 8223 8280 8281 8283 i i FAIRCHILD PIN FOR PIN REPLACEMENT FAIRCHILD


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PDF 93H183 93S41 93S42 93L24 93S62 93H87 8-20LENT 9N107, FJH101 FJH111 ic 7483 BCD adder 9N01 ic 7483 full adder IC 7490 pin configuration function of ic 7490 9N03 TIC 8213 7401 ic configuration pin configuration of ic 7492 Fairchild 9311
altera ep910i

Abstract:
Text: you can quickly determ ine the logic configuration . For exam ple, Figure 6 shows part of a 7483 TTL m , input pin to drive the true and com plem ent data input signal into the logic array(s). In M A X 7000 devices, it is the time required for a dedicated input pin to drive the input signal into the Program , 5000 devices w ith a single Logic Array Block (LAB), it is the delay from the I / O pin to the logic arrays. In M A X 7000 and multi-LAB MAX 5000 devices, it is the delay from the I / O pin to the PIA


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PDF
1995 - data sheet ic 7483

Abstract:
Text: buffer delay. The delay from the I/O pin to the PIA when the I/O pin is used as an input. t PIA Altera Corporation Input pad and buffer delay. The time required for a dedicated input and clock pin , dedicated clock pin to a register's clock input. t DGLOB Delayed global clock delay. The delay from the dedicated clock pin to a register's clock input through the delayed global clock path. t LAC Logic , propagates through the identity comparator in an LAB. t IC t CLR Register clear time. The delay from the


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1995 - pin DIAGRAM OF IC 7486

Abstract:
Text: Pin Configuration Pin ­ Function 1 14 2 13 3 12 4 11 Pin Symbol 1 , V 4.7 kW 93 7483 Figure 3. Pin 1 ,2 ­ Sound carrier input 5 6 5.6 kW 5.6 kW , into a 3-stage, gain controlled, IF amplifier ( pin 1 and 2). The following two mixer stages operate , case of AM the audio frequency at pin 12. Furthermore, the first mixer supplies a regulation voltage , intercarrier mixer in FM/NICAM mode and supplies at pin 8 the intercarrier signal (difference signal between


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PDF TDA4483 D-74025 pin DIAGRAM OF IC 7486 pin diagram for IC 7483 pin configuration OF IC 7486 pin diagram for IC 7485 internal pin diagram for IC 7485 ic 7483 pin diagram pin configuration of 7486 IC IC 7486 pin diagram ic 7483 pin configuration diagram U2829B
NEC uPA 63 H

Abstract:
Text: chosen from adjacent locations on the wafer. These features combined with the pin configuration make this , 0.6 ± 0.1 1 0 ~ 0.1 0.13 + 0.05 PIN CONFIGURATION B1 E2 B2 (Top View) PIN CO , - 74.83 -95.23 -118.13 Q2 V c e = 3 V , Ic = 1 m A , Zo = 5 0 Q , NOISE: NF = 1.2 dB TYP at f = 1 GHz, V c e = 3 V, Ic = 7 mA OUTLINE DIMENSIONS (Units in mm) P , = 3 V, Ic = 7 mA - 1 . 2 5 + 0 .1 - SMALL PACKAGE STYLE: 2 NE856 die in a 2 mm x 1.25 mm x


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PDF UPA821TF NE856 UPA821TF mirrored72 UPA821TF-T1 24-Hour NEC uPA 63 H NEC uPA 63 4017 ic operation CL 2183 ic E 13009 L NEC uPA 63 a transistor d 13009
full adder using ic 74138

Abstract:
Text: Advanced CHMOS circuitry features low power, high performance, and high noise immunity · Includes 68- pin , as special processors, dedicated peripheral controllers and intelligent support chips. IC count can be reduced by an order of magnitude depending on the system configuration . Power requirements can be , contains some 17 logic func tions most of which are MacroFunctions. The overall configuration of the chip , /checker 7483 - 4 bit full adder 74190 - up/down decade counter 7449 - BCD to 7 segment decoder 7474 -


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PDF EP1800JC-EV1 EPt800 68-pin EP1800JC-EV1 0UT20 0UT21 OUT22 0UT23 full adder using ic 74138 full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 IC 74138 Application of Multiplexer IC 74151 74138 IC decoder Multiplexer IC 74151
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