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Part Manufacturer Description Datasheet Download Buy Part
LTC2938CMS#PBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: 0°C to 70°C
LTC2939CMS#PBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C
LTC2938CMS#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: 0°C to 70°C
LTC2939CMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C
LTC2938HDE#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: DFN; Pins: 12; Temperature Range: -40°C to 125°C
LTC2939HMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C

ic 74194 pin configuration Datasheets Context Search

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IC 74194

Abstract: 74194 ic pin diagram Pin configuration of IC 74194 IC 74194 logic diagram IC 74194 pin diagram ic 74194 pin configuration 74194 shift register SL74194 74194 circuit 74194 design and application shift register
Text: .4 m A l|_. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) MR [ T °S R C l D0 U , S ig n e t ic s 7 4 1 9 4 , LS 1 9 4 A , S 1 9 4 Shift Registers 4-Bit Bidirectional Universal , both serial and parallel operation · Asynchronous Master Reset · Hold (do nothing) mode TYPE 74194 , pecification Shift Registers 74194 , LS194A, S194 MODE SELECT - FUNCTION TABLE INPUTS OPERATING MODE , on the 74194 should o nly take place while CP is HIGH fo r conventional operation. The '194 design


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PDF 74LS194A 74S194 36MHz 105MHz SO-16 N74194N, N74LS194AN, N74S194N N74LS194AD, IC 74194 74194 ic pin diagram Pin configuration of IC 74194 IC 74194 logic diagram IC 74194 pin diagram ic 74194 pin configuration 74194 shift register SL74194 74194 circuit 74194 design and application shift register
ic 74194

Abstract: pin diagram of ic 74195 ic 74194 pin configuration 74194 ic pin diagram Pin configuration of IC 74194 IC 74194 logic diagram IC 74195 ml741 74194 shift register 74194 function table
Text: ) A m 54/ Amb4/ 74195 74194 Input/Outpul input/Output Pin No input Output Output Unit Load HIGH LOW , testing in compliance with MIL-STD-883. functional description The Am54/ 74194 features four separate , ■«put. LOGIC SYMBOLS logic diagrams Am54/ 74194 ? \ Clear a fïf nji TOMO, parallel outputs ORDERING INFORMATION Am 54/ Am 54/ Package 74194 74195 Temperature Order Order Type Range , to+IE Temperature (Ambient) Under Bias -55°C to+U Supply Voltage to Ground Potential ( Pin 16 to Pin


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PDF Am54/74194 Am54/74195 MIL-STD-883. ic 74194 pin diagram of ic 74195 ic 74194 pin configuration 74194 ic pin diagram Pin configuration of IC 74194 IC 74194 logic diagram IC 74195 ml741 74194 shift register 74194 function table
full adder using ic 74138

Abstract: full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 Application of Multiplexer IC 74151 IC 74138 74138 IC decoder Multiplexer IC 74151
Text: Advanced CHMOS circuitry features low power, high performance, and high noise immunity · Includes 68- pin , as special processors, dedicated peripheral controllers and intelligent support chips. IC count can be reduced by an order of magnitude depending on the system configuration . Power requirements can be , contains some 17 logic func tions most of which are MacroFunctions. The overall configuration of the chip , input multiplexer 74194 - universal bidirectional shift register 74180 - 8 bit parity generator


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PDF EP1800JC-EV1 EPt800 68-pin EP1800JC-EV1 0UT20 0UT21 OUT22 0UT23 full adder using ic 74138 full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 Application of Multiplexer IC 74151 IC 74138 74138 IC decoder Multiplexer IC 74151
74LS194APC

Abstract: No abstract text available
Text: 194 CO NN ECTIO N DIAGRAM PINO UT A JJS4/ 74194 J/S4S/74S194 o // v 2 0 /54LS/74LS194A 4 , nothing) modes of operation. LO G IC SYMBOL • GUARANTEED SHIFT FREQUENCY OF 30 MHz ( LS194A) OR 70 , SERIAL OR PARALLEL DATA TRANSFERS 2 ORDERING CODE: See Section 9 PIN PKGS OUT 9 - So , ±10%, T a = -55° C to +125° C PKG TYPE Plastic DIP (P) A 74194 PC 74S194PC, 74LS194APC , 54S194FM, 54LS194AFM 4L 1 Vcc = Pin 16 GND = Pin 8 INPUT LO ADING /FAN -O U T: See Section 3


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PDF JJS4/74194 J/S4S/74S194 /54LS/74LS194A LS194A) 54/74S 54/74LS 74LS194APC
74194 truth table

Abstract: IC 74194 HD14194B
Text: transition. PIN A R R A N G E M E N T · · · · · · Quiescent Current = 5nA/pkg typ. @5V Typical , Asynchronous Hold (Do Nothing) Mode Functional Pin-for-Pin Equivalent of 74194 TRU TH TABLE FEATURES L O G IC D IA G R A M Outputs Operating Inputs(Reset = 1) (@ t,*l) Mode Si S« DSR DSL Dpo- j Q« Qi , C T R IC A L C H A R A C T E R I S T I C S Characteristic Symbol VOL Output Voltage VOH , - - HD1 41 94B S W IT C H IN G C H A R A C T E R IC S (C l = 50PF, Ta = 25°C) Symbol


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PDF HD14194B HD14194B 14194B 74194 truth table IC 74194
IC 74194

Abstract: No abstract text available
Text: ift L e ft S hift D o Nothing Positive Edge-Triggered Clocking D irect Overriding Clear T Y P IC A L M A X IM U M CLOCK D IS S IP A T IO N FR EQ U EN C Y T Y P IC A L POW ER S N 5 4 1 9 4 , S N 5 4 , ia IEC P u b lic a tio n 6 1 7 - 1 2 ` Pin n u m b e rs s h o w n a re for D . J . N , and W p a c , . or r e s p e c t i v e ly , b e f o r e t h e in d ic a te d s te a d y s ta te in p u t c o n d itio , U T T Y P IC A L O F A L L O U T P U T S 2 TTL Devices vc c 15 k f i N O M $ IN P U T - C L


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PDF SN54194, SN54LS194A, SN54S194, SN74194, SN74LS194A, 74S194 IC 74194
Truth Table 74194

Abstract: IC 74194 pin diagram 74194 ic pin diagram
Text: . Clearing the register is accom plished by a Low applied to the Master Reset (MR) pin . The CD 54H C /H CT194 , Propagation Delay and Transition Times Significant Power Reduction Compared to L S T T L Logic IC s m , transition. NOTE: b. The HIGH-to-LOW transition of the So, and S-] inputs on the 54/ 74194 should only take , are referenced to Ground. Technical Data CD54/74HC194 CD54/74HCT194 STA TIC E LE C T R IC A L CH A RA CTERISTICS CD 74H C/S4H C194 TEST C O N D IT IO N S C H A R A C T E R IS T IC -40/ V, V lo


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PDF CD54/74HC194 CD54/74HCT194 54/74HC194 CD54/74HCT194 flip-50 S4/74HCT S4/74HC 54/74H 584IOHI 54/74HC Truth Table 74194 IC 74194 pin diagram 74194 ic pin diagram
74194 truth table

Abstract: LS 74194 74194 ic pin diagram
Text: Low applied to the Master Reset (MR) pin . T h e C D 54H C /H C T194 devices are sup plied In 16-lead herm etic du al-in-lin e ceram ic packages (F suffix). The C D 74H C /H C T194 devices are supplied In , inputs on the 54/ 74194 should only take place while CP is HIGH for conventional operation. 280 - , BHAS CD54/74HC194 CD54/74HCT194 S TA TIC E LE C TR IC AL C H AR A C TE R IS TIC S CD74HC/54HC194


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PDF CD54/74HC194 CD54/74HCT194 -CD54/74HC194 D54/74HCT194 54/74HC 54/74HCT 37I28RI 74194 truth table LS 74194 74194 ic pin diagram
truth table for ic 74138

Abstract: ALU IC 74183 16CUDSLR IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
Text: cycles Elim ination of un u sed gates A utom atic pin and p art assignm ents SALSA logic m inim ization , , 74280 7491, 7494, 7496, 7499, 74164, 74165, 74166, 74178, 74179, 74194 , 74198, BARRELST, UNICNT2 SSI , . If a pin assignm ent is specified, the Fitter m atches the request. If no pin assignm ents are , achieved, the Fitter generates a U tilization R eport (.RPT) that d ocum ents macrocell and pin assignm ents, in p u t and o u tp u t pin nam es, and buried registers, as well as any u n u sed resources. At


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PDF 44-Mbyte, 386-based truth table for ic 74138 ALU IC 74183 16CUDSLR IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
Not Available

Abstract: No abstract text available
Text: h ift Left, H o ld a n d Reset ■S ynchronou s p a ra lle l o r seria l operatio n ■T y p ic , Reset (MR) pin . T h e C D 5 4 H C /H C T 194 devices are sup plied in 16-lead herm etic du al-in-lin e ceram ic packages (F suffix). The C D 74H C /H C T194 devices are supplied in 16-lead dual-in­ line , - L o g ic d ia g ra m fo r th e C D 5 4 /7 4 H C 1 9 4 a n d C D 54/74H C T 19 4. CL Q Q , . The H IG H -to -L O W transition of the So, and S i inputs on the 54/ 74194 should only take place w


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PDF CD54/74HC194 CD54/74HCT194 54/74H CD54/74HCT194 54/74HC 54/74HCT 92CS-3
up down counter using IC 7476

Abstract: 74154 shift register IC full adder using Multiplexer IC 74151 full adder circuit using ic 74153 multiplexer sk 7443 DN 74352 74183 adder full adder using ic 74138 pin function of ic 74390 function of latch ic 74138
Text: C H IP C A RRIERS (LCC) C ER A M IC J- LEA D ED C H IP C A R R IER S (JL C C ) C ER A M IC PIN GRID , have up to 2304 bits cf RAM organized In an optional by-nlne memory configuration that Is system , 0 volts, « = 1 MHz.) Param eter Input Capacitance Output Capacitance I/O Pin Capacitance Sym bol C , , VD0" V, = 0 volta, f - 1 MHz.) Param eter Input Capacitance Output Capacitance I/O Pin Capacitance Sym , Is determined by the location on the chip of the associated circuitry and any pin looatlon


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PDF 37417bH 0010S MB65XXXX MB66XXXX MB67XXXX MB65xxxx/MB66xxxx/MB67xxxx MB65xxxx) MB67xxxx) 350AVB S40AVB up down counter using IC 7476 74154 shift register IC full adder using Multiplexer IC 74151 full adder circuit using ic 74153 multiplexer sk 7443 DN 74352 74183 adder full adder using ic 74138 pin function of ic 74390 function of latch ic 74138
ic 74226

Abstract: jk flip flop 74103 ic D flip flop 7474 7471 rs flip flop 4011 flip flop IC 7400 SERIES list 7414 NOT gate ic IC LA 74141 Ic ttl 7490, 7493, 7495 ci 74386
Text: N T h e R P 3 G 01 and R P 3 G 0 2 a r e A n a lo g /D ig ita l se m ic u s to m g a te a r r a y s fa b r ic a te d w ith m e ta l g a te B i-C M O S p ro cess. T h e R P 3 G 0 1 and R P 3 G 0 2 c o n , in g th e C M O S l o g i c , b o t h o f w h ic h a r e in te g r a te d o n o n e c h ip . A s t h , s: ( 1) (2) (3) B ip o la r a n a lo g circu it C M O S log ic g a te a rra y a re a In p u t/O u tp , eters hFE hFE V be V be B V ceo BV C B O B V ebo Satu ration R esistance (@ Ic = lm A , I B= 1 0 0 M


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PDF RP3G01 RP3G01 ic 74226 jk flip flop 74103 ic D flip flop 7474 7471 rs flip flop 4011 flip flop IC 7400 SERIES list 7414 NOT gate ic IC LA 74141 Ic ttl 7490, 7493, 7495 ci 74386
IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Text: file. For each C N F , a Ffierarchy Inte rconnect File (.HIF) and a G raph ic Design File (.GDF) are , logic schem atic in the M A X + P L U S Graph ic Editor. Altera Corporation Page 320 Data Sheet , |d create an ED IF file with V iew log ic softw are, the fo llow ing a pplicatio ns are required: LI , IF netlist writer) version 4.0 o r higher Viewloaic T ab le 3 lists the V ie w lo g ic B U IL T , 74194 74195 74196 74197 74240 74241 74244 74251 74253 74257 74258 74259 Mentor Graphics 74LS114A 74LS133


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1998 - LEAPER-3

Abstract: 74189 7489 sram 89C51 interfacing with lcd display 4N34 ic 74192 pin configuration interfacing 20x4 LCD with 89c51 IC 74189 DATA LEAP-U1 LEAPER-10 driver
Text: matrix LCD display *Test Socket:One position for 28- pin IC socket *Operating Key: (1) 6 Function keys , hook x 1 40- pin IC socket x 1 DC power supply x 1 EXT CRYSTAL adaptor x1 System software disk User , x1 *16-bit 40- pin module + flat cable x1 *4 signal line hook x1 *28- pin IC socket x2 *System , IC socket X2 * DC adaptor * 16-bit 40- pin module + flat cable X1 * 4 signal line hook X1 , environment of development. Additional, the Company has been qualified by major IC manufacturer such as ATMEL


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PDF PIC16C52/54/54A PIC16C55/56/57/57A/58A PIC12C508/509 PIC16C61 PIC16C620/621/622 PIC16C71/710 PIC16C62/63/64/65 PICC16C72/73/74/74A PIC16C83/84 PIC17C42/42A/43/44 LEAPER-3 74189 7489 sram 89C51 interfacing with lcd display 4N34 ic 74192 pin configuration interfacing 20x4 LCD with 89c51 IC 74189 DATA LEAP-U1 LEAPER-10 driver
IC 3-8 decoder 74138 pin diagram

Abstract: binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 7444 series Excess-3-gray code to Decimal decoder full adder using Multiplexer IC 74151 ic 74151 MSI IC 74138 decoder ic 74148 block diagram
Text: Note: Terminal capacities are average values and include package pin capacities and chip internal pad , Configuration of oscillation circuits CMOS standardcell LSI External parts • OSC (crystal, ceramic , ) b-68 b-75 b-81 (1) ^ 1 ! io PN! !a) ¿.J I (C) b-76 (11 b-69 Z2> (2) I IC , 74194 * 33 <0195> 4-BIT PARALLEL-ACCESS SHIFT REGISTER 74195 * 34 <0259> 8-BIT ADDRESSABLE LATCHES , in the Comments column, the addition of a terminal for each bit of an internal flip-flop makes the IC


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PDF MSM91H000 b72MS40 DQQ023b t-42-41 b724240 IC 3-8 decoder 74138 pin diagram binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 7444 series Excess-3-gray code to Decimal decoder full adder using Multiplexer IC 74151 ic 74151 MSI IC 74138 decoder ic 74148 block diagram
sn 74373

Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor ic 74148 block diagram IC 74374
Text: graphic and text designs S chem atic captu re with Valid Logic's V alidG KD or V iew log ic 's V iew d ra w , relational operations Full A lte ra /V a lid Logic and A l te r a /V ie w lo g ic cro ss-com patibility via , V ie w log ic V iew sim chip- and board-level sim ulators or with Logic A u to m a tio n 's S m artM , are entered either with V a lid G E D by Valid Logic or with V ie w d raw by V iew log ic (see Figure , schem atics are converted into F D IF 2 0 0 netlist files with V ie w lo g ic 's E D IF N E T O netlist


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74191, 74192, 74193 circuit diagram

Abstract: Truth Table 74161 IC 7402, 7404, 7408, 7432, 7400 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions 74191, 74192, 74193 counter 74168 truth table of ic 7495 A schematic diagram for the IC of 7411
Text: MAX+PLUSIITTL Macrofunction 74190 74191 74192 74193 74194 74195 74196 74197 74240 74241 74244 74251 74253 74257 , Q u arter-in ch c a rtrid g e tape (Q IC -24, 9 tra ck ) c o n ta in in g all P L S - W S / H P


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PDF HP400 QIC-24, 60-Mbytetape 74191, 74192, 74193 circuit diagram Truth Table 74161 IC 7402, 7404, 7408, 7432, 7400 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions 74191, 74192, 74193 counter 74168 truth table of ic 7495 A schematic diagram for the IC of 7411
74LS82

Abstract: 74245 BIDIRECTIONAL BUFFER IC ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 advantages for ic 7473 la 4508 ic schematic diagram 4 BIT COUNTER 74669 XF107 random number generator by using ic 4011 and 4017 74295
Text: design soft ware). An example configuration for a 2-input NAND gate is shown in figure 2. The complexity , for most requirements. Output drive may be increased from the basic 1mA to a maximum of 48mA per pin , is 4.5 Kbits Access time 12 ns (typical) depending on configuration . For a triple port RAM the , time 9 ns (typ) depending on configuration . In order to access the feasability of integrating a given , to discuss your requirements and to supply data sheets for the exact RAM configuration required


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16CUDSLR

Abstract: 7474 D flip flop free alu 74382 sn 74373 counter schematic diagram 74161 pin diagram of ic 74190 ALU IC 74381 HFJV1 MUX 74151 IC 74373 truth table
Text: PL D s H ierarch ical d esig n entry m eth o d s for b oth g rap h ic and text d esig n s M u , , arithm etic and relational op eration s D elay p red iction and tim ing an aly sis fo r g ra p h ic an d , rap h ic D esign Files (.G D F) w ith the M A X + P L U S G ra p h ic Editor, and T ext D esign Files , Editor. T h e G ra p h ic E d itor offers ad van ced featu res such as m u ltiple h ierarchy lev els, sy , G rap h ic and T ext E d ito rs w ith the d elay p red ictio n featu re. A fter the so u rce and d


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PDF 7400-series 486-b 16CUDSLR 7474 D flip flop free alu 74382 sn 74373 counter schematic diagram 74161 pin diagram of ic 74190 ALU IC 74381 HFJV1 MUX 74151 IC 74373 truth table
74194 shift register

Abstract: 74S1M SN84LS SM74S194 SN74S184
Text: Overriding Clear TY P IC A L M A X IM U M CLOCK FREQUENCY 194 'LS194A 'S194 36 MHz 36 MHz 105 MHz T Y PIC AL , mode controls of the S N 54194/SN 74194 should be changed only while the clock input is high , ic a te d ste a d y -s ta te in p u t c o n d itio n s w e re established. Q A n . ° B n . Q Cn. Q , R P O R A T E D P O S T O F F IC E B O X »013 · D A L L A S . T E X A S 7522a TYPES SN54t94 , OF f t , L. A« B, C, AN D D INPUTS E Q U IV A LE N T OF CLEAR , CLOCK, SO, A N D SI INPUTS TY P IC A


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PDF SMS4S194, SK74194, SKMLS194A, SN74S194 1874--REVISED SN64194, SN74LS1S4A, 74S1M LS194A 74194 shift register 74S1M SN84LS SM74S194 SN74S184
IC 3-8 decoder 74138 pin diagram

Abstract: full adder using Multiplexer IC 74151 full adder using ic 74138 pin diagram for IC 7483 for 4 bit adder chip and pin diagram of IC 7491 circuit diagram for IC 7483 full adder DN 74352 application of ic 74153 74171 74191, 74192, 74193 circuit diagram
Text: CARRIERS (LCC) C E R A M IC J -L E A D E D CHIP CARRIERS (JLCC) C E R A M IC PIN GRID ARR AY (PGA) PACKAGE , configuration that is system compatible with most modern designs. The 2301 has 1024 bits of RAM that may be , common logic Macros. FEATURES · · · · · · 1.4 ns g a te d e la y ty p ic a l. (2 -in p u t N A N D g a te ,F .O .= 2 ) S ta tic R A M or RO M on c h ip . S ilic o n -g a te 1.8 m ic ro n d ual m e ta l , s s -0 .5 -80 -40 -65 Ceramic T y p ic a l - M a x im u m 6.0 VDD + 0.5 VDD + 0.5 140 70 150


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PDF MB65XXXX MB66XXXX MB67XXXX MB65xxxx/MB66xxxx/MB67xxxx MB65xxxx) MB67xxxx) MB66xxxx) IC 3-8 decoder 74138 pin diagram full adder using Multiplexer IC 74151 full adder using ic 74138 pin diagram for IC 7483 for 4 bit adder chip and pin diagram of IC 7491 circuit diagram for IC 7483 full adder DN 74352 application of ic 74153 74171 74191, 74192, 74193 circuit diagram
ALU IC 74381

Abstract: encoder IC 74147 16CUDSLR 74139 truth table ic 7447 truth table alu 74382 truth table for 7446 from IC 74373 truth table pin diagram of ic 74190 truth table for ic 74138
Text: hierarch ical g raphic, text, and w a v e fo rm design entry: G ra p h ic E d ito r for schem atic designs , background. A u to m a tic erro r location is p ro v id e d for the G ra p h ic , Text, and W a v e fo rm , Data Sheet .and More Features IJ IJ IJ J IJ J Log ic synthesis and m in im iza tio n su p p , accessible w ith on-line, contextsensitive help. T he W in d o w s C lip b o a rd q u ic k ly m oves design , d e v ic e p ro g ra m m in g support. It runs un d er the W in d o w s 3.0 g rap h ical e n viro n


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PDF 486-based 12-ms 44-Mbyte, ALU IC 74381 encoder IC 74147 16CUDSLR 74139 truth table ic 7447 truth table alu 74382 truth table for 7446 from IC 74373 truth table pin diagram of ic 74190 truth table for ic 74138
74ls82

Abstract: 74245 BIDIRECTIONAL BUFFER IC 74ls150 ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 74245 BUFFER IC ic 7483 BCD adder Quad 2 input nand gate cd 4093 data sheet ic 74139
Text: example configuration for a 2-input NAND gate is shown in figure 2. The complexity of logic functions made , 48mA per pin by means of parallel bond wires within the package. It should be remembered that an I/O , any single RAM block is 4.5 Kbits Access time 12 ns (typical) depending on configuration . For a , is 2.3 Kbits Accesse time 9 ns (typ) depending on configuration . In order to access the feasability , control logic etc. This overhead is dependent upon the exact configuration of the memory in question


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AMD K6

Abstract: 74147 decimal to binary encoder
Text: commercial products - 50, 70 MHz military products ■Selectable configuration modes 100 , workstations. The final configuration of the three main programmable elements is determined by the user and , Plastic Leaded Chip Carrier G = Pin Grid Array b. SPEED OPTION -50 (50 MHz toggle rate) -70 (70 MHz , TYPE Z = 84- pin PGA (Am3020) Z = 84- pin PGA (Am3030) Z = 132- pin PGA (Am3042)* Z = 132- pin PGA (Am3064)* Z = 175- pin PGA (Am3090) c. DEVICE CLASS /B = Class B b. SPEED/POWER OPTION -50 = 50 MHz


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PDF Am3020/3030/3042/3064/3090 Am3000 AMD K6 74147 decimal to binary encoder
MH 74141

Abstract: Tesla katalog MH74S04 MH74188 information applikation MH74S287 mikroelektronik RFT CDB404E ucy 74132 MZH 115
Text: (bidixecliioßal) DL 295 D X 555 1816 74194 FC UCY 74194 DL 194 D ODE 4104 S X 555 3B111 K 531 IR11P , PIN 8 herausgeführt wird» Am Knotenpunkt X i3t dvrch Anschaltung eir.er Integrierkaparität die , s i c h t 1 6 w ir d d i e f ü r d e n T e m p e ra tu ra n w e n d u n g sb e r e ic h 10 7 0 °C v , ä u s e v a ria n te n , I N e b en T jp e n b e z e ic h n u n g und F u n k t i o n e r f o , ta ll - K eram ik : - F la c h g e h ä u s e D ie i n d e r S p a l t e s ic h in D ual - o


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Supplyframe Tracking Pixel