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LTC1290DCSW Linear Technology LTC1290 - Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 20; Temperature Range: 0°C to 70°C
LTC1290DISW Linear Technology LTC1290 - Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 20; Temperature Range: -40°C to 85°C
LTC1290BISW#PBF Linear Technology LTC1290 - Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 20; Temperature Range: -40°C to 85°C
LTC1290DCSW#TRPBF Linear Technology LTC1290 - Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 20; Temperature Range: 0°C to 70°C
LTC1293DCSW#PBF Linear Technology LTC1293 - Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C
LTC1294DCSW#TRPBF Linear Technology LTC1294 - Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 20; Temperature Range: 0°C to 70°C

ic 74164 data sheet Datasheets Context Search

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74164 with ic PIN DIAGRAM

Abstract:
Text: Specification Logic Products FEATURES · · · · Gated serial Data inputs Typical shift frequency of 36MHz Asynchronous Master Reset Fully buffered Clock and Data inputs TYPE 74164 74LS164 TYPICAL fMAx 36MHz 36MHz , rm itte d to c h a n g e fo r p re d ic ta b le o u tp u t p e rfo rm a n ce . Waveform 3. Data , -bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (Dsa or DSb); either input can be used as an active HIGH enable for data


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PDF LS164 36MHz 74LS164 36MHz LS164 1N916, 1N3064, 500ns 74164 with ic PIN DIAGRAM IC 74164 ic 74ls164 AND SPECIFICATIONS pin diagram of ic 74164
IC 74164

Abstract:
Text: Specification 74164 , Logic Products FEATURES · · · · Gated serial Data inputs Typical shift frequency of 36MHz Asynchronous Master Reset Fully buffered Clock and Data inputs TYPE 74164 74LS164 TYPICAL f , Signetics Military Products Data Manual. DESCRIPTION The '164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (Dsa or Dsb); either input can be used as an active HIGH enable for data entry


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PDF 36MHz 74LS164 36MHz 1N916, 1N3064, 500ns 500ns IC 74164 74164 with ic PIN DIAGRAM pin diagram of ic 74164 ic 74ls164 AND SPECIFICATIONS 74164 truth table and pin diagram of IC 74164 74164 shift register IC LS164 74164 14 PIN DIAGRAM IC 74164 PIN DIAGRAM
ic 74ls164 AND SPECIFICATIONS

Abstract:
Text: .5 3.2 2,4 SN 74164 U N IT TYP* M AX V 0 .8 - 1 .5 3 .2 V V V V ql. l| l|H l|t_ *O S IC C , Inputs Asynchronous Clear T Y P IC A L TYPE M A X IM U M Ç LO C K FR EQ U EN CY '164 'L S 1 6 4 36 MH2 3 6 MHz T Y P IC A L P O W E R D I S S IP A T IO N 21 m W per bit 10 m W per bit SN54164, SN54LS164 . J P A C K A G E SN 74164 . N P A C K A G E SN 74LS 16 4. D O R N P A C K A G E (TOP VIEW) C 1 U , an asynchronous clear. The gated serial inputs (A and B) permit complete control over incoming data


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PDF SN74164, SN74LS164, SN54164, SN54LS164 SN54LS164 LS164, ic 74ls164 AND SPECIFICATIONS IC 74164 54164 74LS164M
IC 74164

Abstract:
Text: SN 74164 5 V 8 -B IT -S C H IE B E R E G IS T E R o I 14 I H aus 113 I I 12 I Gaus Faus I 11 1 110 I -aus Reset Takt elektor IC -K artei © Serielle Eingabe: A e in, Bein Parallele Ausgabe: A aUs · . .H aus Reset = " 1 " : Register ist betriebsbereit Bei Bein = " 1 " w ird die Eingangsinform ation an A e in m it der nächsten positiven T a k tim p u lsfla n , : N 74164 : S F .C 4 1 6 4 A J ü J J iä lJ lT lJ iö U T l. r · CM 0 0 1 1 0, a


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54164

Abstract:
Text: Serial Inputs Asynchronous Clear T Y P IC A L " TY P E '1 6 4 'L 1 6 4 'L S 1 6 4 SN 54 164, S N 54LS 16 4 . . . J OR W PACKAGE SN 54L1 64 . . . J PACKAGE SN 74164 . . . J OR N PACKAGE S N 74LS 16 4 . , asynchronous clear. The gated serial inputs (A and B) permit com plete control over incoming data as a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next , first flip-flop. Data at the serial inputs may be changed w hile the clock is high or low , but only


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PDF SN54164, SN54L164, SN54LS164, SN74164, SN74LS164 54164 IC 74164 3624m 74LS164 74LS164M sn54164
54164

Abstract:
Text: PACKAGE · Fully Buffered Clock and Serial Inputs · Asynchronous Clear T Y P IC A L TYPE M A X IM U M CLOCK FREQ UENCY '1 6 4 'L S 1 6 4 36 MHz 36 M Hz T Y P IC A L P O W E R D IS S IP A T IO N 21 m W per , asynchronous clear. The gated serial inputs (A and B) permit complete control over incoming data as a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next , flip-flop. Data at the serial inputs may be changed while the clock is high or low , but only information


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PDF SN54164, 54LS164, SN74164, 74LS164 54164 IC 74164
1999 - 2SC4416

Abstract:
Text: Storage temperature Symbol VCBO VCEO VEBO IC PC Tj Tstg Ratings 25 13 3 50 150 150 ­55 to +150 Unit V V V , V, IE = 0 VCB = 13 V, RBE = VEB = 3 V, IC = 0 I C = 20 mA, IB = 4 mA VCE = 5 V, IC = 5 mA VCB = 10 V, IE = 0, f = 1 MHz VCE = 5 V, IC = 20 mA VCC = 5 V, IC = 0.8 mA, f in = 900 MHz, f OSC = 930 MHz , Common) Test Condition VCE = 5 V, IC = 5 mA, ZO = 50 Freq. (MHz) 100 200 300 400 500 600 700 800 900 , ­39.9 ­41.3 ­43.4 ­45.0 Test Condition VCE = 5 V, IC = 10 mA, ZO = 50 Freq. (MHz) 100 200 300 400


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PDF 2SC4416 2SC4416 Hitachi DSA002755 IC 7486
2003 - ic 74163

Abstract:
Text: Voltage VCEO 800 V Emitter-to-Base Voltage VEBO 5 V IC 20 A ICP PC 40 , =1600V, RBE=0 IC =10mA, RBE= Ratings min typ max Unit 10 µA 1.0 mA 1.0 mA 800 V VEB=4V, IC =0 Continued on next page. Any and all SANYO products described or , Base-to-Emitter Saturation Voltage VBE(sat) 4 7 IC =13.5A, IB=3.4A IC =13.5A, IB=3.4A tstg tf Unit max 10 VCE=5V, IC =15A VCE(sat) Fall Time min VCE=5V, IC


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PDF ENN7416 2SC5932 2048B 2SC5932] ic 74163 IC 74164 IC 74161 IC 7416 2SC593 2SC5932
1998 - IC 74161

Abstract:
Text: .7 No.2 74164 No.3 No.8 l 74161(1) QC 74161(2) QB QA 74164 QB QC QH PCM 7 , /6996V/6997H/6997V/6998/6999 l n l IC l AGDG l IC IC l IC l VDD-0.3VVSS0.3V l LSI


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PDF J2U0010-28-61 MSM6996H/6996V/6997H/6997V/6998/6999 MSM6996H/6996V/6997H/6997V/6998/6999 SM6997H/MSM6997V/MSM6998/MSM69993003400Hz MSM6996H/MSM6996V/MSM6998 MSM6997H/MSM6997V/MSM6999 HD44200C MSM6996H HD44233CHD44237CHD44277P MSM6997H IC 74161 IC 74164 PLL 02 AG HD44277P HD44248C hd44247 HD44237C HD44233C HD44233 74164 pll
IC 74164

Abstract:
Text: Emitter-to-Base Voltage VEBO 5 V IC 20 A Collector Current Collector Current (Pulse) 1600 , VCB=800V, IE=0 VCE=1600V, RBE=0 IC =10mA, RBE= Unit 10 A 1.0 mA 1.0 mA 800 V VEB=4V, IC =0 Continued on next page. Any and all SANYO products described or contained , Saturation Voltage Storage Time typ 10 4 7 3 V 1.5 V 3.0 s 0.2 IC =10A, IB1=1.6A, IB2=-5A IC =10A, IB1=1.6A, IB2=-5A tf Unit max IC =13.5A, IB=3.4A IC =13.5A, IB


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PDF ENN7416 2SC5932 2048B 2SC5932] IC 74164 ic 74163 IC 74161 2SC5932
54164

Abstract:
Text: REVISED M AR CH 1988 • Gated Serial Inputs SN 54164, SN 54LS164 . . . J OR W PACKAG E SN 74164 . , Inputs • Asynchronous Clear (TOP VIEW) T Y P IC A L TYPE T Y P IC A L M A X IM U M C LO , B) pe rm it c o m p le te c o n tro l over in c o m in g data as a lo w S N 5 4 L S 1 6 4 . . . FK P A C K A G E at e ithe r in p u t in h ib its e ntry o f th e n e w data and resets (TOP , -level in p u t ena b le s th e o th e r in p u t w h ic h w ill th e n d e te rm ine th e sta te o f th


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PDF SN54164, SN54LS164. SN74164, SN74LS164 54LS164 LS164 54164
IC 74166

Abstract:
Text: ) is used to clock the SIPOs. As the AD1847 data sheet explains, the SDFS output indicates the start , enabled. Consult the AD1847 data sheet for details. Configuring the AD1847 for Two Wire, 16 Slots per , parallel data bus utilizing interrupt driven data transfers. While simple, this design can serve as a , issue a bus interrupt when data and control information can be read/written. 4. Control data needs only , registers. Three of these are dedicated to sending data to the AD1847 (PISO, Parallel-ln-Serial-Out


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PDF AN-387 AD1847 16-bit 100nF1~ 100nF 100nFJ^ C11-L IC 74166 pins and their function in ic 74163 epm7160lc84 AN214 IC ic 74163 16- bit up counter H222 IC 74273 ic 74163 74166 shift register IC 74166 applications
IC AND GATE 7408 specification sheet

Abstract:
Text: logic schem atic in the M A X + P L U S Graph ic Editor. Altera Corporation Page 320 Data Sheet , Programming Altera Corporation Page 319 PLS-EDIF Data Sheet P L S -E D IF (Bidirectional ED IF , Corporation Page 321 PLS-EDIF Data Sheet To design logic and create an ED IF file w ith M e n to r G , Data Sheet PLS-EDIF T o design logic and create an ED1F file with Valid Logic softw are, the follow , t o f m a p p in g s . Altera Corporation Page 323 PLS-EDIF Data Sheet design logic ar


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IC 3-8 decoder 74138 pin diagram

Abstract:
Text: ultiple Data Channel C ontroller. F9444 Memory Management Unit and F9470 Console C ontroller. It is also , Data Multi-Processing Capabilities Flexible Operator-Control Functions and Self-Test Static Operation , Architecture The F9445 m icroprocessor com prises three main blocks: the data path, the co n tro l unit, and the tim ing generator. Data Path The data path is 16 bits wide and is responsible fo r all the processing of data and address in the system. In many cases, data and address may be processed sim


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PDF F9445 16-Bit F9444 -Hi25 40-Pln 40-pin IC 3-8 decoder 74138 pin diagram 74874 74164 counter pin diagram of ic 74164 Fairchild 9445 F9444 power control decoder 74138 have three enabled pin 74164 with ic PIN DIAGRAM power control F9444
sn 74373

Abstract:
Text: Data Sheet J J Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S , Development Products Altera Corporation Page 341 PLS-WS/SN Data Sheet supp ort, ad vanced logic , Corporation Data Sheet PLS-WS/SN co m piled. Sy m b ols from the Valid Logic LSTTL library can be m , . Altera Corporation Page 343 PLS-WS/SN Data Sheet Table 2. Viewlogic Library Mapping , t o - d a t e lis t o f m a p p in g s . Page 344 Altera Corporation Data Sheet PLS-WS


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f9454

Abstract:
Text: address reg ister, data b u ffer and address decoder are required fo r any memory, static o r dynam ic , Fairchild's Isoplanar Integrated Inje ctio n'L o g ic (l3La ) technology. This bipolar technology and a , M ultipo rt Interface, F9449 M ultiple Data Channel Controller, F9454 M em ory Management Unit and , -Blt Byte, 16-Blt Word or 32-Blt Double-Word Data Multi-Processing Capabilities Flexible Operator-Control , rdering Inform ation Page 1 2 2 4 5 15 19 30 31 36 Pin Functions C LK _ F 9445 HR 16-B IT M IC R O P


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PDF F9445 16-Bit F9454 F9445-24 74l93 9347S F9448 IC 3-8 decoder 74138 pin diagram
74191, 74192, 74193 circuit diagram

Abstract:
Text: , ver. 3 Data Sheet LI Software support for Classic, M A X 5000, M A X 7000, and ST G E P L D s , Netlist Interface PLS-WS/HP Data Sheet Description Language (A H D L ) design entry, bidirectional , Page 332 Altera Corporation Data Sheet PLS-WS/HP Table 1. Mentor Graphics Library Mapping , /HP Data Sheet Table 2. Mentor Graphics Library Mapping File-Macrofunctions (Part 2 of 3 , 74169 74173 74174 74175 74181 74183 Page 334 Altera Corporation Data Sheet PLS-WS/HP


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PDF HP400 QIC-24, 60-Mbytetape 74191, 74192, 74193 circuit diagram Truth Table 74161 IC 7402, 7404, 7408, 7432, 7400 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 truth table of ic 7495 A 74191, 74192, 74193 schematic diagram for the IC of 7411
1998 - MSM6999

Abstract:
Text: to analog, synchronizing with the synchronous signal RSYNC and clock signal RCLOCK. The data rate , clock signal and latched into the internal register when finished to read eight bits data . The top of the PCM data is specified by RSYNC pulse timing. RCLOCK Receive clock pulse input. The frequency of this clock pulse should be identified with the data rate of PCM input signal at the PCMIN pin. This , PCM output data rate from the PCMOUT pin is set by this clock frequency. The applicable clock


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PDF E2U0010-28-81 MSM6996H/6996V/6997H/6997V/6998/6999 SM6996V/MSM6997H/MSM6997V/MSM6998/MSM6999 MSM6996H/MSM6996V/MSM6998 MSM6997H/MSM6997V/MSM6999 MSM6996H/MSM6996V/MSM699 OP24-P-430-1 MSM6999 74164 with ic PIN DIAGRAM IC 74164 IC 74161 ic 74164 data sheet pin diagram of ic 74164 V74161 MSM6999AS PLL 4049
1998 - MSM6999

Abstract:
Text: to analog, synchronizing with the synchronous signal RSYNC and clock signal RCLOCK. The data rate , clock signal and latched into the internal register when finished to read eight bits data . The top of the PCM data is specified by RSYNC pulse timing. RCLOCK Receive clock pulse input. The frequency of this clock pulse should be identified with the data rate of PCM input signal at the PCMIN pin. This , PCM output data rate from the PCMOUT pin is set by this clock frequency. The applicable clock


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PDF E2U0010-28-81 MSM6996H/6996V/6997H/6997V/6998/6999 SM6996V/MSM6997H/MSM6997V/MSM6998/MSM6999 MSM6996H/MSM6996V/MSM6998 MSM6997H/MSM6997V/MSM6999 MSM6996H/MSM6996V/MSM699 OP24-P-430-1 MSM6999 IC 74164 pin diagram of ic 74164 74161 MSM6999AS MSM6997 M4520 IC 74161 74164 with ic PIN DIAGRAM V74161
1999 - 1sv188

Abstract:
Text: current IC 50 mA Collector power dissipation PC 150 mW Junction temperature Tj , Emitter cutoff current I EBO - - 0.3 µA VEB = 3 V, IC = 0 Collector to emitter , , IC = 20 mA Conversion gain CG 15 19 - dB VCC = 5 V, IC = 0.8 mA, f in = 900 , : Marking is "XB­". 2 VCE = 5 V, IC = 5 mA 2SC4416 DC Current Transfer Ratio vs. Collector , ) 5 VCE = 5 V 4 3 2 1 0 2 5 10 20 Collector Current IC (mA) 50 Collector


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PDF 2SC4416 1sv188 ferrite core bobin 2SC4416 Hitachi DSA00234 IC 7486 pc 817
IC 3-8 decoder 74138 pin diagram

Abstract:
Text: FAI RC HI LP A Schlumberger Company F9445 16-Bit Bipolar Microprocessor Preliminary Data Sheet , Controller, F9447 I/O Controller, F9448 Programmable Multiport Interface, F9449 Multiple Data Channel , /Normalize) Instructions with 8-Bit Byte, 16-Bit Word or 32-Bit Double-Word Data • Multi-Processing , blocks: the data path, the control unit, and the timing generator. Data Path The data path is 16 bits wide and is responsible for all the processing of data and address in the system. In many cases, data


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PDF F9445 16-Bit F9444 F9445-24 IC 3-8 decoder 74138 pin diagram MSI IC 74138 decoder power control F9444 F9445 self-test 74138 FAIRCHILD F9445-16DM 74ls240 bus transfer switch Fairchild 9445
truth table for ic 74138

Abstract:
Text: 1991, ver. 1 Data Sheet H igh-level su p p o rt for A ltera's general-purpose Classic EPLDs M , Products Altera Corporation Page 299 PLCAD-SUPREME & PLS-SUPREME Data Sheet General , . PLS-SUPREME is a softw are-only package. See "Package C ontents" later in this data sheet for m ore inform , Data Sheet PLCAD-SUPREME & PLS-SUPREME D e S IO n E n trv A+PLUS provides the follow ing , high-level lan g u ag e descrip tio n features Page 302 Altera Corporation Data Sheet PLCAD-SUPREME &


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PDF 44-Mbyte, 386-based truth table for ic 74138 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
1997 - HD -1553 CMOS manchester encoder-decoder

Abstract:
Text: serial data protocols. This LSI chip is divided into two sections, an Encoder and a Decoder. These , parity bit as well as the encoding of the data bits. The Decoder recognizes the sync pulse and identifies it as well as decoding the data bits and checking parity. · Data Rate (15531B) . . . . . . . . . . . . . . . 2.5 Megabit/Sec · Data Rate (15531) . . . . . . . . . . . . . . . . 1.25 Megabit/Sec , MILSTD-1553 by allowing the word length to be programmable (from 2 to 28 data bits). A frame consists of


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PDF HD-15531 MIL-STD-1553 HD-15531 MIL-STD-1553 MIL-STD-1553. HD -1553 CMOS manchester encoder-decoder 15531 TDR 5160 HD3-15531B-9 HD1-15531B-9 HD1-15531B-8 HD1-15531-9 HD1-15531 decoder 74165
2000 - 1sv188

Abstract:
Text: 13 V Emitter to base voltage VEBO 3 V Collector current IC 50 mA , EBO - - 0.3 µA VEB = 3 V, IC = 0 Collector to emitter saturation voltage VCE , Gain bandwidth product fT 3.0 3.8 - GHz VCE = 5 V, IC = 20 mA Conversion gain CG 15 19 - dB VCC = 5 V, IC = 0.8 mA, f in = 900 MHz, f OSC = 930 MHz (­5dBm), f out = 30 MHz Noise figure NF - 8 1.2 dB 2 VCE = 5 V, IC = 5 mA 2SC4416


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PDF 2SC4416 ADE-208-1106A 1sv188 Hitachi DSA0076 IC 74164 2SC4416
IC 7402, 7404, 7408, 7432, 7400

Abstract:
Text: 54/7411 74 0.8 2 -1.5 0.22 0.4 2.4 3.3 -1.6 IOH=-800 mA 5 4/7413 Ì* 74 See Data Sheet -1.5 0.22 0.4 2.4 3.3 -1 -1.6 Iq H =-800 hA 54/7414 74 See Data Sheet -1.5 0.22 0.4 2.4 , -1.6 A 1 of A 2 -1 -1.6 B 2 Io h =~80 Data inputs -1.6 Clear , Data inputs -1.6 Clear Inputs -3.2 IO H ='2m<54) l0 H=-52m(74) 54/74125 74 0.8 2 -1.5 0.4 2.4 l0 H " , -20 -18 -25 -25 -55 -55 Quiescent state 13 25 Fired state 23 40 54/74122 54 74 Data


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