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i960 Cx Processor Instruction Set Quick Reference Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1998 - va80960ca25

Abstract:
Text: 270710 i960 ® Cx Microprocessor User's Manual - Instruction Set Quick Reference 272220 , Instruction Issue changed in Quick Reference 12 10 270710-003 11 272220-002 31 modac Instruction Issue changed in Quick Reference 80960CA/CF Processor Specification Update Identification , i960 ® Cx Microprocessor User's Manual. DMA and Instruction Scheduler Interaction Under very , instruction (RET) does not perform as documented in the i960 ® Cx Microprocessor User's Manual. At the end of


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PDF 80960Cx 80960CA/CF va80960ca25 va80960 80960CA 80960CF 80960CF-40 A20A de sw033
1998 - i960 Cx Instruction Set Quick Reference

Abstract:
Text: i960 ® Cx Microprocessor User's Manual - Instruction Set Quick Reference 272220 Nomenclature , 270710-003 30 2 270710-003 30 Chapter 9 - Instruction Set Reference 3 270710-003 30 , Register and Data Structures 272220-002 31 divi Instruction Issue changed in Quick Reference 12 10 270710-003 11 272220-002 31 modac Instruction Issue changed in Quick Reference , i960 ® Cx Microprocessor User's Manual. DMA and Instruction Scheduler Interaction Under very


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PDF 80960Cx 80960CA/CF i960 Cx Instruction Set Quick Reference i960 Cx Processor Instruction Set Quick Reference 80960CA SV908 de sw033 A20A 80960CF-40 80960CF 80960CA-33 SV914
1988 - i960CA

Abstract:
Text: i960 Processor Sample Programs . 7-2 i960 Cx Processor Fault Types and Subtypes , new i960 processor family members. About This Manual This manual is the only reference that you , example programs provided for evaluating the i960 Jx processor and CTOOLS. Chapter 7, The i960 Cx CPU Example Programs Describes the example programs provided for evaluating the i960 Cx processor , . i960 Rx Processor Program Command Prompt Window


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PDF 80960Hx PCI80960DP 80960RP, IQ80960RP i960CA ka 20885 D 80960 EP80960BB i960 Cx Processor GDB960 flightcontrol FF90FF 80960RP
1998 - VA80960CA25

Abstract:
Text: i960 ® Cx Microprocessor User's Manual - Instruction Set Quick Reference 272220 Nomenclature , Instruction Issue changed in Quick Reference 12 6 270710-003 7 272220-002 27 modac Instruction Issue changed in Quick Reference 80960CA/CF Processor Specification Update Identification , 270710-003 26 Chapter 9 - Instruction Set Reference 3 270710-003 26 Chapter 11 - External , i960 ® Cx Microprocessor User's Manual. DMA and Instruction Scheduler Interaction Under very


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PDF 80960Cx 272220-002i 80960CA/CF VA80960CA25 i960 Cx Instruction Set Quick Reference SV914 272875 80960CA 80960CF 80960CF-40 A20A
1994 - 80960CA

Abstract:
Text: . 8-5 8-5 8-7 8-8 8-8 8-9 8-9 8-9 8-9 CHAPTER 9 INSTRUCTION SET REFERENCE 9.1 , 1.1.3 Versatile Instruction Set and Addressing , . 3-1 3-2 3-3 3-3 3-4 3-4 3-4 3-5 3-6 3-6 3-7 3-7 3-7 CHAPTER 4 INSTRUCTION SET , ) . 13-21 13.10.2 Set Up DMA Instruction (sdma , i960 ® CA/CF Microprocessor User's Manual March 1994 Order Number: 270710-003 Intel


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PDF
1994 - intel i960 series

Abstract:
Text: accesses to the external bus. The instruction cache for the i960 Hx processor series is 16 Kbytes, 4 , the i960 ® Cx processors, at a low system cost. i960 ® KB Processor ® i960 KA Processor · 32 , their total embedded system cost. The i960 Hx processor series is the latest generation of the i960 , relationship of the core clock speed to the external bus speed. The i960 HA processor core speed is equal to the external bus speed, the i960 HD processor core speed is double that of the external bus speed


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PDF /0994/15K/IL intel i960 series i960 microprocessor control unit I960 hx intel i960 RISC i960 KB Processor I960 i960HD 3.3-MHz Ultrasound u.s. robotics Modem Specifications Intel i960
1998 - i960 Cx Instruction Set Quick Reference

Abstract:
Text: external bus. The instruction cache for the i960 Hx processor series is 16 Kbytes, 4-way set associative , designed to accept i960 ® Cx and Hx processor2 Quick migration to higher performance with low design , 16 Kbyte four-way set associative instruction cache s 8 Kbyte four-way set associative data , Guarded memory unit (GMU) s Object-code compatible with i960 CA/CF processor family s 3.3 V , performance while containing their total embedded system cost. The i960 Hx processor series has the highest


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PDF 32-bit /0698/5K/IL0983 i960 Cx Instruction Set Quick Reference I960 hx i960 Cx Processor Instruction Set Quick Reference 80960HD 80960HT 80960HA 80960JD 80960JF 80960JT I960HX
1995 - GCC960

Abstract:
Text: . Figure 2. If You Have an i960 Hx, Jx, Cx , Sx Processor QUICKval Kit Install QUICKval See CH21 , 80960 QUICKval Quick Reference Card Order Number: 649788-003 Copyright © 1995, 1998. Intel Corporation. All rights reserved. Where Do I Start? Figure 1. If You Have an i960 ® Rx Processor QUICKval , Strategy From the QUICKval Program Group, choose i960 ® Hx, Jx, Cx , Sx QUICKval Kit From the QUICKval Program Group, choose i960 ® Rx processor QUICKval Kit Run system check and tutorials. For


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PDF A4541-01 32-Bit 352Ball-Grid GCC960 i960 Cx Instruction Set Quick Reference a4542 i960 Cx Processor Instruction Set Quick Reference I960 hx 36 80960JF A4541-01 80960RP 80960RD
1996 - VA80960CA-16

Abstract:
Text: F - Register and Data Structures 011 272220-002 30 Instruction Set Quick Reference - Page 9 012 272220-002 31 Instruction Set Quick Reference - Page 11 6 of 31 , ® Cx Microprocessor User's Manual 270710-003 i960 ® Cx Microprocessor User's Manual - Instruction Set Quick Reference 272220-002 Nomenclature Errata are design defects or errors. These may , Chapter 4 - Instruction Set Summary 002 270710-003 29 Chapter 9 - Instruction Set Reference


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PDF 80960CA/CF 80960CA/CF VA80960CA-16 VA80960CA25 va80960 VA80960CA16 80960CA a2610 80960CF i960 Cx Instruction Set Quick Reference Multi-Channel DMA Controller TA80960
1997 - ASM960

Abstract:
Text: initially disabled. Expansion: Processor Cx , Jx, Hx Set Instruction Trace Mode Output 1,src , 's are stored in dst and condition code is set to 0002. Expansion: Processor Cx , Jx, Hx Scan , . Expansion: Enable Instruction Cache Processor Cx Output Jx, Hx icctl icctl ldconst , . Expansion: Invalidate Instruction Cache Output Jx, Hx Page 22 of 26 Processor Cx icctl , instruction trace mode is disabled. Expansion: Processor Cx , Jx, Hx Read Instruction Trace Mode


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PDF xlate960, gas960/asm960 i960Rx 0x0300 ASM960 processor atom
1996 - VA80960CA25

Abstract:
Text: Instruction Set Quick Reference (272220-002) i960 ® Cx Microprocessor Users Guide Instruction Set Quick , datasheet i960 ® Cx Microprocessor User's Manual i960 ® Cx Microprocessor User's Manual - Instruction Set Quick Reference 272886 270710 272220 Nomenclature Errata are design defects or errors. These , 270710-003 34 34 34 34 34 34 8 of 36 DOCUMENTATION CHANGES Chapter 4 - Instruction Set Summary Chapter 9 - Instruction Set Reference Chapter 11 - External Bus Description Chapter 12 - Interrupt


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PDF 80960CA/CF 80960CA/CF VA80960CA25 80960CA i960 Cx Instruction Set Quick Reference a2610 intel DOC i960 Cx Processor Instruction Set Quick Reference A20A 80960CF 80960CA-33 80960CA-25
1988 - HX 830

Abstract:
Text: , CORE3, or ANY. Discussion To select your i960 ® processor instruction set , specify the A option. The , manual set . See Getting Started with the i960 ® Processor Software Development Tools for a list of all , invoking the CTOOLS utilities. (You can also set 2-1 2 i960 ® Processor Assembler User's Guide , architecture options have been redefined in CTOOLS to represent a subset of the i960 Jx processor instruction , instruction , a no-op instruction , whose 2-6 Writing Assembly Language Code for the i960 ® Rx Processor


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PDF CTOOLS960 GNU/960 HX 830 4x4 keyboard intel i960 batch MARKING intel CORE i3 instruction format intel atom microprocessor I960 hx I960 G960 bge 1,5 Applications of IC 8259
1988 - intel i960 batch MARKING

Abstract:
Text: options have been redefined in CTOOLS to represent a subset of the i960 Jx processor instruction set , , HT, CORE0, CORE1, CORE2, CORE3, or ANY. Discussion To select your i960 processor instruction set , Processor Assembler User's Guide Chapter 9 Example Programs Examples Using the Core Instruction Set , development tools manual set . See Getting Started with the i960 Processor Software Development Tools for a , source text that is not valid for your target processor instruction set . To assemble for a specific


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PDF CTOOLS960 GNU/960 xlate960 intel i960 batch MARKING 80960 G960 I960 marking R810
1998 - micro instruction set of I960 hx

Abstract:
Text: i960 JA processor has a 2-Kbyte instruction cache; the JF and JD have a 4-Kbyte instruction cache; the , Considerations for Writing Portable Code 1.5 Instruction Set The i960 architecture defines a comprehensive , depends on instruction execution times, therefore, is not portable to all i960 processor architecture implementations. 1.5.2 Implementation-Specific Instructions Most of the processor 's instruction set is , implementation-specific functions. Section 1, " Instruction Set Reference " denotes each implementation-specific


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PDF 80960Jx micro instruction set of I960 hx I960 80960JT microprocessor architecture programming
1996 - applications of microprocessor in printer

Abstract:
Text: Performance with i960 33-MHz i960 2716 HA/HD/HT Superscalar ® Cx Processor AP-712 DRAM , rearrangement case of the i960 Cx and Hx processors, the compiler uses advanced code scheduling algorithms , libraries s Low-level libraries supporting i960 processor evaluation PROCESSORS ® i960 , FaxBack Order # Document # ® Processor Product Line Card ® i960 2033 Processor , 272505 80960HA/HD/HT 32-Bit High- i960 ® Performance Superscalar Processor Microprocessor


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PDF D-85622 BP543 /0596/3K/IL applications of microprocessor in printer embedded dram ibm 272221 MON960 Microprocessor intel Programmers Reference Manual IEEE-695 EV80960SX AB42 272238
1996 - list of Applications of microprocessor

Abstract:
Text: Performance with i960 33-MHz i960 2716 HA/HD/HT Superscalar ® Cx Processor AP-712 DRAM , rearrangement case of the i960 Cx and Hx processors, the compiler uses advanced code scheduling algorithms , libraries s Low-level libraries supporting i960 processor evaluation PROCESSORS ® i960 , FaxBack Order # Document # ® Processor Product Line Card ® i960 2033 Processor , 272505 80960HA/HD/HT 32-Bit High- i960 ® Performance Superscalar Processor Microprocessor


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PDF D-85622 BP543 /0596/3K/IL list of Applications of microprocessor applications of microprocessor in printer intel Programmers Reference Manual PC 80960 embedded dram ibm INTEL application notes 272495 IEEE-695 QIC-24 Intel i960 features
1998 - applications of microprocessor in printer

Abstract:
Text: the i960 Cx Processor Using Flexlogic AP-706 DRAM Controller for the ® 40-MHz i960 CA/CF , Code ® Generation for the i960 Rx, Jx and Hx Processor Families s Easy-to-Use Whole- Program , features. For instance, in the case of the i960 Cx and Hx processors, the compiler uses advanced code scheduling algorithms to modify instruction sequences, taking advantage of the processor 's parallel , load time, and in big-endian form for applications that use i960 processor big-endian memory regions


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PDF IEEE-754 /0398/5K/IL0261 applications of microprocessor in printer 272238 hp 2731 80960KB Programmer Reference manual 80960CA embedded dram ibm EP80960 embedded microprocessors 80960 Reference Manual types of microprocessor in printer
1998 - 80960JA

Abstract:
Text: 's Manual · i960 ® KA/KB Microprocessor Programmers Reference Manual · i960 ® KB Hardware Designers Reference Manual 2.0 Hardware Considerations 2.1 Bus Organization Like the 80960KA/KB processor , end of a bus access. This pin functions like BLAST# on the i960 Sx and i960 Cx microprocessors. The , processor 's Interrupt/Interrupt Acknowledge protocol, as this model is not supported in the i960 Jx , processors are completely different. 80960Jx initialization is much more closely related to the CX processor


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PDF 80960Jx 80960KA/KB 80960KA/KB 80960JA/JF/JD/JS/JC/JT 80960JA, 80960JF/JD, 80960JS/JC/JT. 80960Kx 80960JA 80960JD 80960JT 80960KA 80960KB i960 KA/KB Programmers Reference Manual i960 KA/KB Reference Manual Intel 80960kb programmers reference
1993 - MC 9080

Abstract:
Text: conventions are used throughout this manual: i960 Cx /Jx/Hx/Rx processor refers generically to the , Breakpoints. You can set two instruction breakpoints with most i960 processors. In addition, you can set two , at address 80000040H: =>break 80000040 You can set up to two instruction breakpoints on the i960 , only to the i960 Jx/ Cx /Rx processors, which have two hardware data breakpoints. The i960 Hx processor , Interrupts While Executing . 7-19 i960 Processor Cache Invalidation by MON960


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PDF MON960 MON960 Index-15 MC 9080 hp image point hx 210830 EP80960 auto changing in/out indicator doorbell project i960 MC Programmers Reference Manual seven segment quad digit display red input pci9080 8086 hex code sheet
1997 - 272484-001

Abstract:
Text: 32-Bit High Performance Superscalar Processor Data Sheet i960 ® Hx Microprocessor User's Manual i960 ® Hx Microprocessor Instruction Set and Register Quick Reference Reduced Power Options for the , Burst Accesses on 8- and 16-Bit Buses Do Not Behave Like the Cx Processor Instruction Breakpoints Are , Low, and #17 Burst Accesses on 8- and 16-Bit Buses Do Not Behave Like the Cx Processor January , set on a stack location and a call, callx, or calls instruction causes a flush to that stack location


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PDF 80960HA/HD/HT 80960HA/HD/HT 272484-001 272495 80960HA 80960HD 80960HT E-41 intel DOC
1995 - MON960

Abstract:
Text: Multi-Window, Easy-To-Use Graphical User Interface Supports Microtec C/C+ and Intel C i960 ® Processor , for breaking on instruction addresses, XRAY Monitor allows you to set breakpoints in ROMed code. Additionally, embedded i960 CA processor development benefits from the ability to break in real-time on read , final production system. With support of all on-chip i960 processor debug registers, XRAY Monitor , SPARCstations, MS Windows, RISC System 6000, and HP9000 Series 700. PROCESSORS SUPPORTED: i960 Sx, Kx, Cx


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PDF EP80960Jx EP80960Cx MON960 MON960 HP9000 EP80960CX
1993 - Automatic Doorbell with Object Detection Circuit

Abstract:
Text: breakpoints on the i960 Sx, Kx, Cx , Jx, and RP processors. The Hx processor supports six instruction , instruction with the fmark instruction again. If you are using the i960 Cx , Jx, or RP processor , up to two , with most i960 processors. In addition, you can set two data breakpoints for the i960 Cx , Jx, and RP , Interrupts While Executing.7-16 i960 Processor Cache Invalidation by MON960 , .2-3 TCP/IP Server/Workstation Communication.2-8 Memory Map for Cyclone i960 Sx/Kx/ Cx /Jx/Hx


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PDF MON960 MON960 documentat40 Index-15 Automatic Doorbell with Object Detection Circuit i960 MC Programmers Reference Manual IQ80960RP
1997 - ROM960

Abstract:
Text: Release Notes · i960 RD Processor Support · Compatibility Note · Summary of Changes and Known Problems , Started with the i960 ® Processor Development Tools 4. i960 ® Processor Compiler User's Guide 5. i960 ® Processor Assembler User's Guide 6. i960 ® Processor Software Utilities User's Guide 7. i960 ® Processor Library Supplement 8. gdb960 User's Manual 9. i960 ® Processor Tools License , i960 RP processor , and improves the program development process in several ways. · Code generation


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PDF gdb960 ROM960 dmp960 80960RP G960 GCOV960 gstrip960 I960 i960RP
1995 - intel atom microprocessor

Abstract:
Text: Instruction Set and Register Quick Reference , Order #272792. (This is included with the user's manual.) Introducing the i960 ® Hx Processor to Current i960 ® Cx Processor Users 80960 Processor Initialization: IBR , Literature Center. FROM/TO REFERENCE : Table 4. 80960Hx Instruction Set , page 4, bottom column 1,2 labeled , . If an instruction breakpoint is set on an address containing an invalid opcode, the processor , 8- and 16-Bit Buses Do Not Behave Like the Cx Processor 272830-001 July, 1996 1 of 33


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PDF 80960HA/HD/HT 80960HA/HD/HT intel atom microprocessor 001-page 272495 PC 80960 dcct 8448H S-809 80960HD66 80960HD 80960HA
1998 - 272484

Abstract:
Text: Instruction Set and Register Quick Reference 272792 AP-506: Designing for 80960Cx and 80960Hx , -Bit Buses Do Not Behave Like the Cx Processor 2 30 Instruction Breakpoints Are Superseded by , TC Register Event Flags Problem: The modtc instruction can be used to set event flags in the , processor , the bit never gets set . The timer expires and halts as normal. Implication: This errata , . It guarantees the processor will not service any masked interrupts after the intdis instruction is


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PDF 80960HA/HD/HT 80960HA/HD/HT 32-Bit 272484 i960 Cx Processor Instruction Set Quick Reference E-41 80960HT 80960HD 80960HA 74FCT245 AP 272792 272556 272495
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