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i960 Cx Instruction Set Quick Reference Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1998 - va80960ca25

Abstract: va80960 de sw033 80960CA 80960CF 80960CF-40 A20A
Text: 270710 i960 ® Cx Microprocessor User's Manual - Instruction Set Quick Reference 272220 , Instruction Issue changed in Quick Reference 12 10 270710-003 11 272220-002 31 modac Instruction Issue changed in Quick Reference 80960CA/CF Processor Specification Update Identification , i960 ® Cx Microprocessor User's Manual. DMA and Instruction Scheduler Interaction Under very , instruction (RET) does not perform as documented in the i960 ® Cx Microprocessor User's Manual. At the end of


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PDF 80960Cx 80960CA/CF va80960ca25 va80960 de sw033 80960CA 80960CF 80960CF-40 A20A
1988 - i960CA

Abstract: ka 20885 D 80960 EP80960BB i960 Cx Processor GDB960 PCI80960DP flightcontrol FF90FF 80960RP
Text: QUICKval Kit Chapter 7 The i960 Cx CPU Example Programs System Validation , i960 Processor Sample Programs . 7-2 i960 Cx Processor Fault Types and Subtypes , assembly language code from 80960 core processors (e.g., i960 Cx , Jx, and Hx processors) to its CORE0 , new i960 processor family members. About This Manual This manual is the only reference that you , example programs provided for evaluating the i960 Jx processor and CTOOLS. Chapter 7, The i960 Cx


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PDF 80960Hx PCI80960DP 80960RP, IQ80960RP i960CA ka 20885 D 80960 EP80960BB i960 Cx Processor GDB960 flightcontrol FF90FF 80960RP
1998 - i960 Cx Instruction Set Quick Reference

Abstract: i960 Cx Processor Instruction Set Quick Reference 80960CA de sw033 SV908 SW147 A20A 80960CF-40 80960CF 80960CA-33
Text: i960 ® Cx Microprocessor User's Manual - Instruction Set Quick Reference 272220 Nomenclature , 270710-003 30 2 270710-003 30 Chapter 9 - Instruction Set Reference 3 270710-003 30 , Register and Data Structures 272220-002 31 divi Instruction Issue changed in Quick Reference 12 10 270710-003 11 272220-002 31 modac Instruction Issue changed in Quick Reference , i960 ® Cx Microprocessor User's Manual. DMA and Instruction Scheduler Interaction Under very


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PDF 80960Cx 80960CA/CF i960 Cx Instruction Set Quick Reference i960 Cx Processor Instruction Set Quick Reference 80960CA de sw033 SV908 SW147 A20A 80960CF-40 80960CF 80960CA-33
1998 - VA80960CA25

Abstract: i960 Cx Instruction Set Quick Reference SV914 80960CA 80960CF 80960CF-40 A20A 272875
Text: i960 ® Cx Microprocessor User's Manual - Instruction Set Quick Reference 272220 Nomenclature , 270710-003 26 Chapter 9 - Instruction Set Reference 3 270710-003 26 Chapter 11 - External , Instruction Issue changed in Quick Reference 12 6 270710-003 7 272220-002 27 modac Instruction Issue changed in Quick Reference 80960CA/CF Processor Specification Update Identification , i960 ® Cx Microprocessor User's Manual. DMA and Instruction Scheduler Interaction Under very


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PDF 80960Cx 272220-002i 80960CA/CF VA80960CA25 i960 Cx Instruction Set Quick Reference SV914 80960CA 80960CF 80960CF-40 A20A 272875
1994 - 80960CA

Abstract: RT-1112 CX 879 i960 Cx Processor TTL catalog solutions960 catalog A-18 128 bit processor schematic i960 Cx Processor Instruction Set Quick Reference 80960CF
Text: . 8-5 8-5 8-7 8-8 8-8 8-9 8-9 8-9 8-9 CHAPTER 9 INSTRUCTION SET REFERENCE 9.1 , 1.1.3 Versatile Instruction Set and Addressing , . 3-1 3-2 3-3 3-3 3-4 3-4 3-4 3-5 3-6 3-6 3-7 3-7 3-7 CHAPTER 4 INSTRUCTION SET , ) . 13-21 13.10.2 Set Up DMA Instruction (sdma , i960 ® CA/CF Microprocessor User's Manual March 1994 Order Number: 270710-003 Intel


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PDF
1994 - intel i960 series

Abstract: i960 microprocessor control unit I960 hx intel i960 RISC I960 i960HD i960 KB Processor 3.3-MHz Ultrasound u.s. robotics Modem Specifications I960HX
Text: accesses to the external bus. The instruction cache for the i960 Hx processor series is 16 Kbytes, 4 , the i960 ® Cx processors, at a low system cost. i960 ® KB Processor ® i960 KA Processor · 32 , associative instruction cache 8 Kbyte four-way set associative data cache 2 Kbyte on-chip data RAM On-chip , vendors One PGA socket may be designed to accept i960 Cx and Hx processor2 Guarded Memory Unit 32 , /cycle @ 75 MHz) s Clock multiplied core s Large instruction cache on-chip 16 Kbyte four-way set


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PDF /0994/15K/IL intel i960 series i960 microprocessor control unit I960 hx intel i960 RISC I960 i960HD i960 KB Processor 3.3-MHz Ultrasound u.s. robotics Modem Specifications I960HX
1998 - i960 Cx Instruction Set Quick Reference

Abstract: I960 hx i960 Cx Processor Instruction Set Quick Reference 80960HD 80960HT 80960HA 80960JD 80960JF 80960JT 80960CF
Text: external bus. The instruction cache for the i960 Hx processor series is 16 Kbytes, 4-way set associative , designed to accept i960 ® Cx and Hx processor2 Quick migration to higher performance with low design , ® i960 HA/HD/HT Superscalar Microprocessors PRODUCT HIGHLIGHTS s Superscalar RISC core s 16 Kbyte four-way set associative instruction cache s 8 Kbyte four-way set associative data , Kbyte fourway set associative 128-bit path to instruction sequencer Cache-lock, cache-off mode


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PDF 32-bit /0698/5K/IL0983 i960 Cx Instruction Set Quick Reference I960 hx i960 Cx Processor Instruction Set Quick Reference 80960HD 80960HT 80960HA 80960JD 80960JF 80960JT 80960CF
1995 - GCC960

Abstract: i960 Cx Instruction Set Quick Reference a4542 hx 36 A4541-01 MON960 I960 80960RP 80960RD 80960JF
Text: 80960 QUICKval Quick Reference Card Order Number: 649788-003 Copyright © 1995, 1998. Intel , Strategy From the QUICKval Program Group, choose i960 ® Hx, Jx, Cx , Sx QUICKval Kit From the , . Figure 2. If You Have an i960 Hx, Jx, Cx , Sx Processor QUICKval Kit Install QUICKval See CH21 , the QUICKval Program Group, choose i960 ® Hx, Jx, Cx , Sx QUICKval Kit Run system check and , I960 core processors (e.g., Kx, Cx , Jx)? If you have legacy code that you wish to use with the I960


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PDF A4541-01 32-Bit 352Ball-Grid GCC960 i960 Cx Instruction Set Quick Reference a4542 hx 36 A4541-01 MON960 I960 80960RP 80960RD 80960JF
1996 - VA80960CA25

Abstract: 80960CA i960 Cx Instruction Set Quick Reference a2610 A20A 80960CF intel DOC 80960CA-33 i960 Cx Processor Instruction Set Quick Reference VA80960CA-25
Text: Instruction Set Quick Reference (272220-002) i960 ® Cx Microprocessor Users Guide Instruction Set Quick , datasheet i960 ® Cx Microprocessor User's Manual i960 ® Cx Microprocessor User's Manual - Instruction Set Quick Reference 272886 270710 272220 Nomenclature Errata are design defects or errors. These , 270710-003 34 34 34 34 34 34 8 of 36 DOCUMENTATION CHANGES Chapter 4 - Instruction Set Summary Chapter 9 - Instruction Set Reference Chapter 11 - External Bus Description Chapter 12 - Interrupt


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PDF 80960CA/CF 80960CA/CF VA80960CA25 80960CA i960 Cx Instruction Set Quick Reference a2610 A20A 80960CF intel DOC 80960CA-33 i960 Cx Processor Instruction Set Quick Reference VA80960CA-25
1996 - VA80960CA-16

Abstract: VA80960CA25 80960CA VA80960CA16 va80960 272875 A20A 80960CF Multi-Channel DMA Controller i960 Cx Instruction Set Quick Reference
Text: F - Register and Data Structures 011 272220-002 30 Instruction Set Quick Reference - Page 9 012 272220-002 31 Instruction Set Quick Reference - Page 11 6 of 31 , ® Cx Microprocessor User's Manual 270710-003 i960 ® Cx Microprocessor User's Manual - Instruction Set Quick Reference 272220-002 Nomenclature Errata are design defects or errors. These may , Chapter 4 - Instruction Set Summary 002 270710-003 29 Chapter 9 - Instruction Set Reference


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PDF 80960CA/CF 80960CA/CF VA80960CA-16 VA80960CA25 80960CA VA80960CA16 va80960 272875 A20A 80960CF Multi-Channel DMA Controller i960 Cx Instruction Set Quick Reference
1997 - processor atom

Abstract: ASM960
Text: initially disabled. Expansion: Processor Cx , Jx, Hx Set Instruction Trace Mode Output 1,src , set of CTOOLS enhancements implemented to help you move from existing i960 RP and RD processors to , running it on i960 Rx processors that are not based on the i960 JF core. This is because the instruction , without excluding use of JF-specific constructs. Details of the Rx Strategy 80960 Instruction Set , subset of the 80960 Jx instruction set chosen for performance and future compatibility reasons. These


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PDF xlate960, gas960/asm960 i960Rx 0x0300 processor atom ASM960
1988 - HX 830

Abstract: 4x4 keyboard intel CORE i3 instruction format I960 hx I960 G960 st stt 128 intel atom microprocessor bge 1,5 Applications of IC 8259
Text: assembler. 4 Option Reference A: Architecture Select the architecture ( instruction set ) A arch , , CORE3, or ANY. Discussion To select your i960 ® processor instruction set , specify the A option. The , Details of the Rx Strategy . 2-4 80960 Instruction Set , . 3-6 Selecting the Instruction Set and Libraries . 3-7 Defining a Base , Programs Examples Using the Core Instruction Set . 9-1 Enable and Count


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PDF CTOOLS960 GNU/960 HX 830 4x4 keyboard intel CORE i3 instruction format I960 hx I960 G960 st stt 128 intel atom microprocessor bge 1,5 Applications of IC 8259
1988 - intel i960 batch MARKING

Abstract: G960 I960 marking R810 80960
Text: options have been redefined in CTOOLS to represent a subset of the i960 Jx processor instruction set , , HT, CORE0, CORE1, CORE2, CORE3, or ANY. Discussion To select your i960 processor instruction set , Details of the Rx Strategy . 2-4 80960 Instruction Set , . 3-6 Selecting the Instruction Set and Libraries . 3-7 Defining a Base , . 8-4 Pseudo-instructions Reference . 8-7 vii i960


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PDF CTOOLS960 GNU/960 xlate960 intel i960 batch MARKING G960 I960 marking R810 80960
1996 - applications of microprocessor in printer

Abstract: embedded dram ibm 272238 EV80960SX AB42 Microprocessor intel Programmers Reference Manual QIC-24 MON960 IEEE-695
Text: rearrangement case of the i960 Cx and Hx processors, the compiler uses advanced code scheduling algorithms , Performance with i960 33-MHz i960 2716 HA/HD/HT Superscalar ® Cx Processor AP-712 DRAM , ® i960 Cx Microprocessor Users Manual ® i960 272206 80960SB Embedded 32-Bit Microprocessor , ® 270567 Reference Manual ® 272392 i960 272601 ® 2515 2359 i960 272602 , -MHz i960 Intel CA/CF Microprocessor Reference 272627 Numbers World Wide Web Address


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PDF D-85622 BP543 /0596/3K/IL applications of microprocessor in printer embedded dram ibm 272238 EV80960SX AB42 Microprocessor intel Programmers Reference Manual QIC-24 MON960 IEEE-695
1998 - micro instruction set of I960 hx

Abstract: I960 microprocessor architecture programming 80960JT
Text: Considerations for Writing Portable Code 1.5 Instruction Set The i960 architecture defines a comprehensive , implementation-specific functions. Section 1, " Instruction Set Reference " denotes each implementation-specific , modes, etc. · · · · Implementation-independent instruction set . Procedure call mechanism , are one or all of: · Additions to the instruction set beyond the instructions defined by the core , implementations. 1.2.4 Instruction Cache The i960 architecture allows instructions to be cached on-chip in


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PDF 80960Jx micro instruction set of I960 hx I960 microprocessor architecture programming 80960JT
1996 - list of Applications of microprocessor

Abstract: applications of microprocessor in printer intel Programmers Reference Manual PC 80960 INTEL application notes embedded dram ibm i960 compiler ctools 272495 QIC-24 272456
Text: rearrangement case of the i960 Cx and Hx processors, the compiler uses advanced code scheduling algorithms , Performance with i960 33-MHz i960 2716 HA/HD/HT Superscalar ® Cx Processor AP-712 DRAM , ® i960 Cx Microprocessor Users Manual ® i960 272206 80960SB Embedded 32-Bit Microprocessor , ® 270567 Reference Manual ® 272392 i960 272601 ® 2515 2359 i960 272602 , -MHz i960 Intel CA/CF Microprocessor Reference 272627 Numbers World Wide Web Address


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PDF D-85622 BP543 /0596/3K/IL list of Applications of microprocessor applications of microprocessor in printer intel Programmers Reference Manual PC 80960 INTEL application notes embedded dram ibm i960 compiler ctools 272495 QIC-24 272456
1998 - applications of microprocessor in printer

Abstract: 272238 hp 2731 80960CA embedded microprocessors embedded dram ibm 80960KB Programmer Reference manual EP80960 272495 QIC-24
Text: features. For instance, in the case of the i960 Cx and Hx processors, the compiler uses advanced code , /HP-UX, *IBM RS6000/AIX, Sun-4 PROCESSORS SUPPORTED: i960 ® Sx, Kx, Cx , Jx, Rx, and Hx Processors , the i960 Cx Processor Using Flexlogic AP-706 DRAM Controller for the ® 40-MHz i960 CA/CF , Microprocessor User's Manual ® i960 Cx Microprocessor User's Manual ® i960 KB Microprocessor Programmer's Reference Manual ® i960 SA/SB Microprocessor Reference Manual 82961KD Printer Coprocessor Reference


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PDF IEEE-754 /0398/5K/IL0261 applications of microprocessor in printer 272238 hp 2731 80960CA embedded microprocessors embedded dram ibm 80960KB Programmer Reference manual EP80960 272495 QIC-24
1995 - MON960

Abstract: EP80960CX
Text: . The combination of XRAY Monitor and MON960 ROM monitor allow you to use all variants of the i960 microprocessor, including i960 Jx and Hx processors. By taking full advantage of the on-chip hardware support for breaking on instruction addresses, XRAY Monitor allows you to set breakpoints in ROMed code , SPARCstations, MS Windows, RISC System 6000, and HP9000 Series 700. PROCESSORS SUPPORTED: i960 Sx, Kx, Cx , Multi-Window, Easy-To-Use Graphical User Interface Supports Microtec C/C+ and Intel C i960 ® Processor


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PDF EP80960Jx EP80960Cx MON960 MON960 HP9000 EP80960CX
1998 - i960 KA/KB Programmers Reference Manual

Abstract: i960 KA/KB Reference Manual 80960JA 80960JD 80960JT 80960KA 80960KB 80960KX Intel 80960kb programmers reference
Text: 's Manual · i960 ® KA/KB Microprocessor Programmers Reference Manual · i960 ® KB Hardware Designers , end of a bus access. This pin functions like BLAST# on the i960 Sx and i960 Cx microprocessors. The , contain the same basic instruction set with the following exceptions: 8 Technical Note , on the 80960Kx is only 512 bytes. All 80960Jx instruction caches are two-way set associative. The , Upgrading System Designs from i960 ® Kx to the i960 Jx Processors Upgrading System Designs from


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PDF 80960Jx 80960KA/KB 80960KA/KB 80960JA/JF/JD/JS/JC/JT 80960JA, 80960JF/JD, 80960JS/JC/JT. 80960Kx i960 KA/KB Programmers Reference Manual i960 KA/KB Reference Manual 80960JA 80960JD 80960JT 80960KA 80960KB Intel 80960kb programmers reference
1993 - MC 9080

Abstract: hp image point hx 210830 MON960 seven segment quad digit display red input auto changing in/out indicator doorbell project EP80960 i960 MC Programmers Reference Manual pci9080 interface 8254 with 8086
Text: Breakpoints. You can set two instruction breakpoints with most i960 processors. In addition, you can set two data breakpoints for the i960 Cx , Jx, and Rx series processors. The i960 Hx series processors , at address 80000040H: =>break 80000040 You can set up to two instruction breakpoints on the i960 , conventions are used throughout this manual: i960 Cx /Jx/Hx/Rx processor refers generically to the , Cx I/O Microprocessor User's Manual Intel Order # 270710-003 i960 Hx I/O Microprocessor User


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PDF MON960 MON960 Index-15 MC 9080 hp image point hx 210830 seven segment quad digit display red input auto changing in/out indicator doorbell project EP80960 i960 MC Programmers Reference Manual pci9080 interface 8254 with 8086
1993 - MON960

Abstract: Automatic Doorbell with Object Detection Circuit i960 MC Programmers Reference Manual IQ80960RP
Text: with most i960 processors. In addition, you can set two data breakpoints for the i960 Cx , Jx, and RP , breakpoints on the i960 Sx, Kx, Cx , Jx, and RP processors. The Hx processor supports six instruction , instruction with the fmark instruction again. If you are using the i960 Cx , Jx, or RP processor, up to two , .2-3 TCP/IP Server/Workstation Communication.2-8 Memory Map for Cyclone i960 Sx/Kx/ Cx /Jx/Hx , Conventions The following notational and terminology conventions are used throughout this manual: i960 Cx


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PDF MON960 MON960 documentat40 Index-15 Automatic Doorbell with Object Detection Circuit i960 MC Programmers Reference Manual IQ80960RP
1997 - 80960HA

Abstract: 80960HD 80960HT E-41 272484-001 272495 intel DOC
Text: i960 ® Hx Microprocessor Instruction Set and Register Quick Reference Reduced Power Options for the , Burst Accesses on 8- and 16-Bit Buses Do Not Behave Like the Cx Processor Instruction Breakpoints Are , set on a stack location and a call, callx, or calls instruction causes a flush to that stack location , ). 7. MODTC Command Can Set TC Register Event Flags PROBLEM: The modtc instruction can be , all identified errata published prior to this date. Add errata item #22 Instruction Breakpoints Are


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PDF 80960HA/HD/HT 80960HA/HD/HT 80960HA 80960HD 80960HT E-41 272484-001 272495 intel DOC
1997 - ROM960

Abstract: dmp960 80960RP G960 I960 GCOV960 gstrip960 GDB960 i960RP
Text: option has been redefined in CTOOLS to represent a subset of the 80960 Jx instruction set chosen for , , Hx CORE3 Cx , Jx, Hx Environment Variables The assembler now supports all I960 and G960 , directory. Branch Prediction Bits Ignored for i960 RP Architecture The assembler no longer lets you set , i960 RP Architecture The syntax for using the modpc instruction with any i960 architecture other than RP is: modpc src, mask, src/dst When using a modpc instruction with the i960 RP architecture, the


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PDF gdb960 ROM960 dmp960 80960RP G960 I960 GCOV960 gstrip960 i960RP
1995 - intel atom microprocessor

Abstract: 272495 001-page PC 80960 E-41 80960HT 8448H 80960HA S-809 i960 Cx Instruction Set Quick Reference
Text: Instruction Set and Register Quick Reference , Order #272792. (This is included with the user's manual.) Introducing the i960 ® Hx Processor to Current i960 ® Cx Processor Users 80960 Processor Initialization: IBR , Literature Center. FROM/TO REFERENCE : Table 4. 80960Hx Instruction Set , page 4, bottom column 1,2 labeled , is set on a stack location and a call, callx, or calls instruction causes a flush to that stack , . MODTC COMMAND CAN SET TC REGISTER EVENT FLAGS PROBLEM: The modtc instruction can be used to set event


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PDF 80960HA/HD/HT 80960HA/HD/HT intel atom microprocessor 272495 001-page PC 80960 E-41 80960HT 8448H 80960HA S-809 i960 Cx Instruction Set Quick Reference
1993 - 8c603

Abstract: MCS-86 001f0003 MCS-86 Users Manual 7 SEGMENT DISPLAY PARA LIGHT interface 8254 with 8086 Transistor Substitution Data Book 1993 fst 172 auto changing in/out indicator doorbell project sxse
Text: through program execution. · Breakpoints. You can set two instruction breakpoints with most i960 processors. In addition, you can set two data breakpoints for the i960 Cx and Jx series processors. The i960 , to two instruction breakpoints on the i960 processors Sx, Kx, Cx , and Jx. The Hx processor supports , must be on an instruction boundary. You can set up to two instruction breakpoints on the i960 Kx, Sx, Cx , and Jx processors. You can set up to six instruction breakpoints on the Hx processor. Enter br


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PDF MON960 MON960 Index-14 Index-15 8c603 MCS-86 001f0003 MCS-86 Users Manual 7 SEGMENT DISPLAY PARA LIGHT interface 8254 with 8086 Transistor Substitution Data Book 1993 fst 172 auto changing in/out indicator doorbell project sxse
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