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Part Manufacturer Description Datasheet Download Buy Part
ISL76671AROZ-T7A Intersil Corporation Low Power, 100 Lux Optimized, Analog Output Ambient Light Sensor; ODFN6; Temp Range: -40° to 105°C
ICL7667CBA Intersil Corporation Dual Power MOSFET Driver; PDIP8, SOIC8; Temp Range: 0° to 70°
ICL7667CBA-T Intersil Corporation Dual Power MOSFET Driver; PDIP8, SOIC8; Temp Range: 0° to 70°
ICL7667CPAZ Intersil Corporation Dual Power MOSFET Driver; PDIP8, SOIC8; Temp Range: 0° to 70°
ICL7667CBAZA Intersil Corporation Dual Power MOSFET Driver; PDIP8, SOIC8; Temp Range: 0° to 70°

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1997 - DM74ALS373WM

Abstract:
Text: www.national.com DS006220 PrintDate=1997/08/15 PrintTime=13:36:55 7667 ds006220 Rev. No. 1 cmserv Proof , PrintDate=1997/08/15 PrintTime=13:36:57 7667 ds006220 Rev. No. 1 2 cmserv Proof 2 Switching , load. Function Table Output Enable Control G D Output L H H L H L L L L X Q0 H X X Z Q H L = Low State, H = High State, X = Don't Care , =1997/08/15 PrintTime=13:36:59 7667 ds006220 Rev. No. 1 www.national.com cmserv Proof 3


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PDF ALS373 ds006220 DM74ALS373WM DM74ALS373 DM74ALS373N DM74ALS373SJ h 7667 LS373 M20D
AV033

Abstract:
Text: d>busy high_active f>led 6hz (flash at mute) h >led 1.5hz (flash at mute) j>led 6hz (off at mute , * STS2 a>pwm1 b>stop high_pulse d>busy high_active f>led 6hz (flash at mute) h >led 1.5hz (flash at , high_active e>busy low_active f>led 6hz (flash at mute) g>led 3hz (flash at mute) h >led 1.5hz (flash at , (flash at mute) h >led 1.5hz (flash at mute) j>led 6hz (on at mute) l>led 1.5hz (on at mute) n>led 6hz , >13.5k ; g>12.5k ; m>8.3k hz . ( Vdd=3v ) h >5.1k ; h >5.9k ; h >7.1k ; h >8.9k ; ; h >11.8k ; 2002


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PDF AV0332C, AV0632E, AV0932B, AV0932C, AV1232D, AV1832C, AV2432B, AV3032, AV4232 AV3032 AV033 t 9436 A8M16 AV0332C Aplus Flash 8*8 led matrix 24 pin AV0632E AV0932B AV0932C AV1232D
2000 - 200MHZ

Abstract:
Text: operation. Latched input for FS0 at initial power up for H /W selecting the output frequency of CPU, SDRAM , power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=0). Low skew , buffer for ISA bus loads. Latched input for FS4 at initial power up for H /W selecting the output , clock. Default is 24MHz. Latched input for FS2 at initial power up for H /W selecting the output , FS3 at initial power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks (Default


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PDF W83195AR-25 200MHZ W83195AR-25 SEL24
2000 - ICS9250-25

Abstract:
Text: internal load cap (33pF) Ground pins for 3.3V supply 3V66 [2:0] OUT 3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B PCICLK01 FS0 OUT IN 3.3V PCI clock outputs, with , i xe d 4 8 M H z c l o c k o u t p u t f o r U S B Logic input frequency select bit. Input latched , SDRAM outputs can be turned off t h r o u g h I 2C GNDL PWR Ground for 2.5V power supply for , 72.00 75.00 77.00 55.53 60.00 66.87 68.67 75.00 76.67 80.00 83.33 64.00 65.00 66.85 68.50


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PDF ICS9250-25 GND3V66 3V66-0 3V66-1 3V66-2 VDD3V66 SDRAM11 SDRAM10 33MHz. ICS9250-25 intel 8250
200MHZ

Abstract:
Text: . Latched input for FS0 at initial power up for H /W selecting the output frequency of CPU, SDRAM and PCI , H /W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=0). Low skew (< 250ps , loads. Latched input for FS4 at initial power up for H /W selecting the output frequency of CPU, SDRAM , 24MHz. Latched input for FS2 at initial power up for H /W selecting the output frequency of CPU, SDRAM , power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=1). 4.5 Power


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PDF W83195AR-25 200MHZ 02/Apr SEL24 W83195AR-25
2005 - Not Available

Abstract:
Text: . Latched input for FS0 at initial power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=0). Low skew (< 250ps) PCI clock outputs. Latched input for FS1 at initial power up for H , input for FS4 at initial power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=0). 24MHz or 48MHz output clock. Default is 24MHz. Latched input for FS2 at initial power up for H , . Latched input for FS3 at initial power up for H /W selecting the output frequency of CPU, SDRAM and PCI


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PDF W83195BR-25 200MHZ W83195BR-25
2007 - W83195BG-25

Abstract:
Text: normal operation. Latched input for FS0 at initial power up for H /W selecting the output frequency of CPU , power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=1). 38,48,47,46 , buffer for ISA bus loads. Latched input for FS4 at initial power up for H /W selecting the output , input for FS2 at initial power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=0). 48MHz output clock. Latched input for FS3 at initial power up for H /W selecting the output


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PDF W83195BR-25 W83195BG-25 W83195BR-25/W83195BG-25 200MHZ W83195BR-25/W83195BG-25 02/Apr W83195BG-25
2003 - Not Available

Abstract:
Text: at initial power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=0). Low skew (< 250ps) PCI clock outputs. Latched input for FS1 at initial power up for H /W , at initial power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=0). 24MHz or 48MHz output clock. Default is 24MHz. Latched input for FS2 at initial power up for H /W , input for FS3 at initial power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks


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PDF W83195BR-25 W83195BR-25 02/Apr
2002 - 200MHZ

Abstract:
Text: clock during normal operation. Latched input for FS0 at initial power up for H /W selecting the output , for FS1 at initial power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks , power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=0). 24_48MHz , power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=0). 48MHz/ FS3* 34 I/O 48MHz / Latched input for FS3 at initial power up for H /W selecting the output


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PDF W83195BR-25 200MHZ 02/Apr SEL24 W83195BR-25
2000 - 200MHZ

Abstract:
Text: clock during normal operation. Latched input for FS0 at initial power up for H /W selecting the output , for FS1 at initial power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks , initial power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=0). , initial power up for H /W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=0). 48MHz/ FS3* 34 I/O 48MHz / Latched input for FS3 at initial power up for H /W selecting the


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PDF W83195BR-25 200MHZ W83195BR-25 SEL24
VM776CT

Abstract:
Text: /knockouts CLEAR COVER w/o knockouts w/knockouts h INSIDE DIMENSION w d H OUTSIDE DIMENSION W D , 5.03 127.83 5.03 127.83 5.03 127.83 7.00 177.83 7.00 177.83 7.00 177.83 3.02 76.67 ) 4.02 102.02) 3.02 76.67 ) VM SERIES 4.02 102.02) 3.02 76.62) 4.02 102.02) 5.02 127.42) 3.02 76.72) 5.02 127.42 , VM933-PBM4 VM755-PBM6 VM775-PBM9 Outside Dimensions d H (in) 3.31 3.31 3.31 3.31 3.31 3.31 4.72 3.31 2.72 , MINIATURE MINIATURE MINIATURE MINIATURE MINIATURE h Holes 0 0 0 1 2 3 4 1 2 3 4 6 9 w (in) 4.02 6.38


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1999 - H 7667 CBA

Abstract:
Text: Supplies ICL7667CBAZA 7667 CBAZ 0 to 70 8 Ld SOIC (N) M8.15 (Pb-Free) • DC/DC Converters ICL7667CPA* 7667 CPA 0 to 70 8 Ld PDIP E8.3 ICL7667CPAZ 7667 CPAZ 0 to 70 8 Ld PDIP* (Pb-Free) E8.3 ICL7667CBA* 7667 CBA • Motor Controllers Pinout ICL7667 (8 LD PDIP, SOIC , SMALL OUTLINE PLASTIC PACKAGE INDEX AREA 0.25(0.010) M H B M INCHES E SYMBOL , 0.1497 0.1574 3.80 4.00 4 0.050 BSC 1.27 BSC - H C 0.10(0.004) C A M


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PDF ICL7667 FN2853 ICL7667 ICL7667â H 7667 CBA 7667 CPA h 7667 cpa IC 7667
2008 - 1456CE3

Abstract:
Text: ] C R6.35 mm [0.250 in] 76.67 mm [3.019 in] 31.92 mm [1.257 in] 61.14 mm [2.407 in] R4.76 mm , in] 1456C E 3 B e ig e Top, B lue C as e - 1456C E3W H B U B la ck Top, B lue C as e - 1456C E3B , elf A dhes ive R ubber F eet Inc luded R eguired H ardw are Inc luded R eplac em ent S c rew s - 1421


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PDF 1456C 1421-J6 1456CE3 1456CE3
Not Available

Abstract:
Text: CALLOUTS OR 205 766-7 S H E L L M A T 'L THIS P L U G IS D E S I G N E D TO C O N F O R M TO , A. A A P J5 - R V 3 0 H 763 E -7 INCLUDED AMP P A R T NO. S T A M P E D ON C O N N E C T , FOR PIN C O N T A C T S H i - D E N S ITV ~HD-20~ C ON N E C T O R SIZE 3 D SCALE FSCM NO


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PDF HD-20~
1999 - h 7667 cpa

Abstract:
Text: ICL7667CBAZA 7667 CBAZ 0 to 70 8 Ld SOIC (N) M8.15 (Pb-Free) · DC/DC Converters ICL7667CPA* 7667 CPA 0 to 70 8 Ld PDIP E8.3 ICL7667CPAZ 7667 CPAZ 0 to 70 8 Ld PDIP* (Pb-Free) E8.3 ICL7667CBA* 7667 CBA · Motor Controllers Pinout ICL7667 (8 LD PDIP, SOIC) TOP , NARROW BODY SMALL OUTLINE PLASTIC PACKAGE 0.25(0.010) M H B M INCHES E SYMBOL , 0.1497 0.1574 3.80 4.00 4 0.050 BSC 1.27 BSC - H C 0.10(0.004) C A M


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PDF ICL7667 FN2853 ICL7667 h 7667 cpa H 7667 CBA CPAZ driver circuit for MOSFET IC L 7667 cpa 7667 tl494 dc to ac inverters 7667 cpa 7667 cbaz tl494 dc to ac inverter h 7667 cpaZ
2007 - Not Available

Abstract:
Text: 27.24 16.05 8.01 3.93 1.86 1.15 1.84 3.85 7.85 15.13 28.98 41.02 76.67 70.80 RBP-400+ INSERTION LOSS , 69.49 86.86 62.05 RBP-400+ VSWR Outline Dimensions (inch mm ) A B C D E F G H J .350 .350 .100 .175


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PDF -55oC 100oC RBP-400+ GP731 2002/95/EC) M104389 EDR-7836AU
2008 - Not Available

Abstract:
Text: 1.86 1.15 1.84 3.85 7.85 15.13 28.98 41.02 76.67 70.80 RBP-400+ INSERTION LOSS 110 .100 TYP. VSWR , -400+ VSWR Outline Dimensions (inch mm ) A B C D E F G H J .350 .350 .100 .175 .075 .100 .090 .040 .080


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PDF -55oC 100oC RBP-400+ GP731 2002/95/EC) M104389 EDR-7836AU
2006 - Not Available

Abstract:
Text: Typical Performance Data Outline Dimensions ( A B .770 .800 19.56 20.32 G H .200 .20 5.08 5.08 C D .385 , Insertion Loss (dB) _ x 69.97 79.30 76.67 76.75 74.46 64.87 51.59 49.50 45.90 43.94 40.15 32.96 29.32


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PDF PHP-700 TB-305 DC-400 M97270 PHP-700
Not Available

Abstract:
Text: 76.67 76.67 76.66 76.67 66.66 66.66 66.66 71.43 66.66 66.66 66.66 66.66 69.99 69.99 69.99 , . Controller (host) sends the write address D2 ( H ) ICS clock will acknowledge Controller (host) sends the , €¢ • • Controller (host) will send start bit. Controller (host) sends the write address D2 ( H , acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 ( H , ICS clock sends Byte 0 through byte X (if X( H ) was written to byte 8). Controller (host) will need


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PDF ICS952906A VN800/CN700/P4M800 33MHz 318MHz 66MHz 48MHz 24/48MHz 25MHz O-153 ICS952906AGLFT
2007 - via p4M800

Abstract:
Text: 66.67 67.33 67.33 67.33 67.32 76.67 76.67 76.66 76.67 66.66 66.66 66.66 71.43 66.66 66.66 , the write address D2 ( H ) ICS clock will acknowledge Controller (host) sends the begining byte , the write address D2 ( H ) ICS clock will acknowledge Controller (host) sends the begining byte , (host) sends the read address D3 ( H ) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X( H ) was written to


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PDF ICS952906A VN800/CN700/P4M800 33MHz 318MHz 66MHz 48MHz 24/48MHz 25MHz O-153 ICS952906AGLFT via p4M800 P4M800 via vn800 B4-8D via datasheet p4m800 p4m80 cn700 ICS952906A VN800
1997 - Not Available

Abstract:
Text: t c h e d a t p ow e r o n . 3.3V PCI clock outputs, with Synchronous CPUCLKS L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V PCI clock , latency of the p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s. Clock input of I2C input , n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V fixed 24MHz output 3.3V


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PDF ICS9248-112 810/810E to150MHz 3V66MHz 48MHz, 24MHz, 318MHz. 166MHz 9248AG-92 9248AG-92LF
2114D

Abstract:
Text: = +25°C, 50Q System C h a ra c te ristic s Frequency Range Power Output Power Added Efficiency , Fin=2440 MHz, Pin= 8.0 dBm Page 2 PM2114 Absolute Maximum Ratings C h a ra c te ristic s , Scattering Parameters, VD D = 5.0V, TA = +25°C, 50Q System F req. (M H z) 500 1000 1500 1600 2000 2100 2200 , 123.29 117.84 101.19 100.84 76.67 72.30 64.35 61.00 41.76 24.50 7.44 -7.99 - 21.11 -26.08 -28.08 , Drawing Bottom View -.180"- H 2 60" r - .202" -« RRRR iL r · H H R FI I * f u


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PDF PM2114 PM2114 2400MHz ri137 -020--H 2114DS 2114D 2114-d h 7667 IC 7667
2006 - h 7667

Abstract:
Text: 9.40 10.16 wt grams 5.2 25 80 60 40 20 0 1 10 69.97 79.30 76.67 76.75 74.46 , .770 .800 19.56 20.32 G H .200 .20 5.08 5.08 inch mm Frequency (MHz) 15 10 5 0


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PDF PHP-700 TB-305 M97270 h 7667 PHP-700
Not Available

Abstract:
Text: PHENOLIC SPACERS/STANDOFFS LENGTH 7661 7662 7663 7664 7665 7666 7667 7668 7669 7670 7671 , S c re w .1 2 0 H o le CAT. NO. #6 S c re w .1 4 0 H o le CAT. NO. #8 S c re w .171 H o , 2 0 H o le CAT. NO. 312 O.D 1 6 S c re w .1 4 0 H o le CAT. NO. * 8 S c re w .171 H o , 1491 454 x h (.500) 362 369 1492 (.750) 363 370 1493 (1.000) 364 , #10 S c re w .2 0 0 H o le CAT. NO. 74 (.125) 74 7a - j HEX THREADED STANDOFFS


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PDF MIL-1-010, 8442D 8441E 8442E 8440F 8441F 8442F 8440G 8441G 8442G
2003 - Not Available

Abstract:
Text: t c h e d a t p ow e r o n . 3.3V PCI clock outputs, with Synchronous CPUCLKS L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V PCI clock , latency of the p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s. Clock input of I2C input , n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V fixed 24MHz output 3.3V


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PDF ICS9248-112 810/810E to150MHz 3V66MHz 48MHz, 24MHz, 318MHz. 166MHz ICS9248yF-112-T 0326C--09/18/03
Supplyframe Tracking Pixel