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SparkFun-MicroMod-DA16200-Function-Board SparkFun-MicroMod-DA16200-Function-Board ECAD Model Renesas Electronics Corporation SparkFun MicroMod Wi-Fi Function Board Featuring the Ultra-Low Power DA16200 Wi-Fi Module
SNJ54S181FK SNJ54S181FK ECAD Model Texas Instruments Arithmetic Logic Units/Function Generators 28-LCCC -55 to 125
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SNJ54LS181FK SNJ54LS181FK ECAD Model Texas Instruments Arithmetic Logic Units/Function Generators 28-LCCC -55 to 125

generation function gps 2105 Datasheets Context Search

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2008 - 2105

Abstract: arm 2106 LPC2104 LPC2106BBD48 16C550 LPC2104BBD48 LPC2105BBD48 LQFP48
Text: its features, although only the PWM function is pinned out on the LPC2104/ 2105 /2106. The Timer is , LPC2104/ 2105 /2106 Single-chip 32-bit microcontrollers; 128 kB ISP/IAP flash with 16/32/64 kB RAM , sheet, the term LPC2104/ 2105 /2106 will apply to devices with and without /00 and /01 suffixes. Suffixes , features implemented in LPC2104/ 2105 /2106/01 devices I Fast GPIO port enables port pin toggling up to 3.5 , of its function . I UART 0/1 include fractional baud rate generator, autobauding capabilities, and


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PDF LPC2104/2105/2106 32-bit 16/32-bit 128-bit 16-bit LPC2104 2105 arm 2106 LPC2106BBD48 16C550 LPC2104BBD48 LPC2105BBD48 LQFP48
2008 - Not Available

Abstract: No abstract text available
Text: LPC2104/ 2105 /2106 NXP Semiconductors Single-chip 32-bit microcontrollers Table 7. Pin function , LPC2104/ 2105 /2106 Single-chip 32-bit microcontrollers; 128 kB ISP/IAP flash with 16/32/64 kB RAM , sheet, the term LPC2104/ 2105 /2106 will apply to devices with and without /00 and /01 suffixes , features implemented in LPC2104/ 2105 /2106/01 devices I Fast GPIO port enables port pin toggling up to 3.5 , of its function . I UART 0/1 include fractional baud rate generator, autobauding capabilities, and


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PDF LPC2104/2105/2106 32-bit 16/32-bit 128-bit 16-bit LPC2104
philips lpc arm7 spi

Abstract: LPC2104 LPC2104BBD48 LPC2105 LPC2105FBD48 LPC2106 LPC2106BBD48
Text: Pin Name 11:10 P0.5 LPC2104/ 2105 /2106 Value Function 0 Match 0.1 (Timer 0) 0 , -bit microcontroller LPC2104/ 2105 /2106 Pin Function Select Register 1 (PINSEL1 - 0xE002C004) The PINSEL1 , LPC2104/ 2105 /2106 TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . 14 Pin Function Select Register 0 (PINSEL0 - 0xE002C000) . . . . . . . . . . . , CMOS single-chip 32-bit microcontroller LPC2104/ 2105 /2106 GENERAL DESCRIPTION The LPC 2104, 2105


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PDF LPC2106/LPC2105/LPC2104 32-bit 128kB 64kB/32kB/16kB LPC2104/2105/2106 philips lpc arm7 spi LPC2104 LPC2104BBD48 LPC2105 LPC2105FBD48 LPC2106 LPC2106BBD48
2006 - LPC2106FBD

Abstract: No abstract text available
Text: Semiconductors LPC2104/ 2105 /2106 Single-chip 32-bit microcontrollers Pin function select register 0 (PINSEL0 , LPC2104/ 2105 /2106 Single-chip 32-bit microcontrollers Pin function select register 1 (PINSEL1 - 0xE002 , only the PWM function is pinned out on the LPC2104/ 2105 /2106. The Timer is designed to count cycles of , LPC2104/ 2105 /2106 Single-chip 32-bit microcontrollers; 128 kB ISP/IAP flash with 16/32/64 kB RAM Rev. 06 - 25 July 2006 Product data sheet 1. General description The LPC2104/ 2105 /2106 are based


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PDF LPC2104/2105/2106 32-bit LPC2104/2105/2106 16/32-bit 128-bit 16-bit LPC2104 LPC2106FBD
2004 - circuit diagram of voice recognition

Abstract: block diagram of voice recognition device jedec package MO-220 ARM 7 lpc2106 Specification Quartz Crystals 1.6 Mhz 32-64 bit microprocessor architecture ic tms 1000 ARM microcontroller ARM7TDMI-S external bus interface unit ARM7TDMI-S voltage level
Text: LPC2104/ 2105 /2106 Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM Rev. 05 - 22 December 2004 Product data 1. General description The LPC2104/ 2105 /2106 , thirty-two 5 V tolerant general purpose I/O pins in a tiny LQFP48 (7 × 7 mm2) package. LPC2104/ 2105 /2106 , reserved. 9397 750 14476 Product data Rev. 05 - 22 December 2004 2 of 32 LPC2104/ 2105 /2106 , interface is used, GPIO/other function sharing these pins are not available. (2) APB with Ready signal


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PDF LPC2104/2105/2106 32-bit kB/32 kB/16 LPC2104/2105/2106 16-bit circuit diagram of voice recognition block diagram of voice recognition device jedec package MO-220 ARM 7 lpc2106 Specification Quartz Crystals 1.6 Mhz 32-64 bit microprocessor architecture ic tms 1000 ARM microcontroller ARM7TDMI-S external bus interface unit ARM7TDMI-S voltage level
2004 - LPC2106BBD48

Abstract: arm 2106 16C550 HVQFN48 LPC2104 LPC2104BBD48 LPC2105BBD48 LPC2106FHN48 LQFP48
Text: LPC2104/ 2105 /2106 Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM Rev. 04 - 05 February 2004 Product data 1. General description The LPC2104, 2105 and , thirty-two 5 V tolerant general purpose I/O pins in a tiny LQFP48 (7 × 7 mm2) package. LPC2104/ 2105 /2106 , 12792 Product data Rev. 04 - 05 February 2004 2 of 32 LPC2104/ 2105 /2106 Philips , used, GPIO/other function sharing these pins are not available. (2) APB with Ready signal. Fig 1


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PDF LPC2104/2105/2106 32-bit kB/32 kB/16 LPC2104, 16-bit LPC2106BBD48 arm 2106 16C550 HVQFN48 LPC2104 LPC2104BBD48 LPC2105BBD48 LPC2106FHN48 LQFP48
2003 - LPC2106BBD48

Abstract: 16C550 LPC2104 LPC2104BBD48 LPC2105BBD48 LQFP48
Text: LPC2104/ 2105 /2106 Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM Rev. 02 - 11 June 2003 Product data 1. General description The LPC2104, 2105 and 2106 , thirty-two 5 V tolerant general purpose I/O pins in a tiny LQFP48 (7 × 7 mm2) package. LPC2104/ 2105 /2106 , reserved. 9397 750 11499 Product data Rev. 02 - 11 June 2003 2 of 34 LPC2104/ 2105 /2106 , interface is used, GPIO/other function sharing these pins are not available. (2) APB with Ready signal


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PDF LPC2104/2105/2106 32-bit kB/32 kB/16 LPC2104, 16-bit LPC2106BBD48 16C550 LPC2104 LPC2104BBD48 LPC2105BBD48 LQFP48
2003 - 16C550

Abstract: LPC2104 LPC2104BBD48 LPC2105BBD48 LPC2106BBD48 LQFP48 0xE002C004 Lpc2104 example
Text: LPC2104/ 2105 /2106 Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM Rev. 03 - 07 October 2003 Product data 1. General description The LPC2104, 2105 and , thirty-two 5 V tolerant general purpose I/O pins in a tiny LQFP48 (7 × 7 mm2) package. LPC2104/ 2105 /2106 , reserved. 9397 750 12142 Product data Rev. 03 - 07 October 2003 2 of 34 LPC2104/ 2105 /2106 , interface is used, GPIO/other function sharing these pins are not available. (2) APB with Ready signal


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PDF LPC2104/2105/2106 32-bit kB/32 kB/16 LPC2104, 16-bit 16C550 LPC2104 LPC2104BBD48 LPC2105BBD48 LPC2106BBD48 LQFP48 0xE002C004 Lpc2104 example
LT 2105

Abstract: adsp 21xx processor advantages ADSP-2105BP-40 ADSP2105KP40 ADSP-2105 data address generator 2105 ADSP-2105 ADSP-2101 ADSP-2105KP-40 ADSP2105BP40
Text: available in a 68-lead PLCC. Table I. ADSP- 2105 Pin List Pin # Group of Name Pins Function Address 14 , ► ANALOG DEVICES DSP Microcomputer ADSP- 2105 FEATURES Complete DSP Microcomputer 100 ns , with Prescaler Programmable Wait State Generation Automatic Boot of Internal Program Memory from , DESCRIPTION The ADSP- 2105 is a single-chip microcomputer optimized for digital signal processing (DSP) and , , extensive interrupt capabilities and on-chip program and data memory RAM. The ADSP- 2105 has 512 words of (16


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PDF ADSP-2105 ADSP-2100 ADSP-2101 16-Bit Wai41 LT 2105 adsp 21xx processor advantages ADSP-2105BP-40 ADSP2105KP40 ADSP-2105 data address generator 2105 ADSP-2105 ADSP-2105KP-40 ADSP2105BP40
ADSP-2105KP-40

Abstract: and/ADSP-2105KP-40
Text: /z-o9 DSP Microcomputer ADSP- 2105 FEATURES Complete DSP Microcomputer 100 ns Instruction Cycle , Prescaler Programmable W ait State Generation Automatic Boot of Internal Program Memory from Byte-Wide , The ADSP- 2105 is a single-chip microcomputer optimized for .digital signal processing (DSP) and other , capabilities and onchip program and data memory RAM. The ADSP- 2105 has 512 words of (16-bit) data memory RAM and IK words of (24-bit) program memory RAM on chip. The ADSP- 2105 is a pin-for-pin and


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PDF ADSP-2105 ADSP-2100 ADSP-2101 ADSP-2105KP-40 and/ADSP-2105KP-40
2006 - TU08

Abstract: of S12X microcontroller AN1734 AN2612 AN2685 S12X pwm driver pit and interrupt XGate
Text: . . . . . . . . . . . . . . . . . . . . . . . 1 Principle of PWM Generation Using XGATE . . . . 2 , Implementation . . . . . . . . . . . . . . . . . 7 8 Features of PWM Generation by XGATE . . . . . . . 9 9 , Generation Using XGATE 2 Principle of PWM Generation Using XGATE Generation of the PWM signal is , in PWM Generation PIT & XGATE Init @ Power On PIT Generates Periodic Interrupt Service , . Principle of PWM Generation Using the XGATE 3 PWM Timing Example To demonstrate the principle of


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PDF AN3225 AN2612 AN1734) TU08 of S12X microcontroller AN1734 AN2685 S12X pwm driver pit and interrupt XGate
2003 - str 2105

Abstract: 0xE01FC084 2105 ARM 7TDMI 32 BIT MICROPROCESSOR ENA6 ARM 7 lpc2106 ARM microcontroller LPC2104 LPC2105 LPC2106
Text: INTEGRATED CIRCUITS LPC2106/ 2105 /2104 USER MANUAL Preliminary Philips Semiconductors , LPC2106/ 2105 //2104 2 September 17, 2003 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2106/ 2105 /2104 Table of Contents List of Figures . . . . . . . . . . . . , LPC2106/ 2105 /2104 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 16 16 16 17 18 19 LPC2106/ 2105 /2104 Memory Addressing . .


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PDF LPC2106/2105/2104 LPC2106/2105//2104 LPC2106/2105/2104 str 2105 0xE01FC084 2105 ARM 7TDMI 32 BIT MICROPROCESSOR ENA6 ARM 7 lpc2106 ARM microcontroller LPC2104 LPC2105 LPC2106
2003 - str 2105

Abstract: vpbdiv register ARM 7TDMI 32 BIT MICROPROCESSOR LPC2106 2105 ARM 7 lpc2106 ARM 7TDMI MICROPROCESSOR ARM microcontroller LPC2106/LPC2105 manual semiconductor
Text: INTEGRATED CIRCUITS LPC2106/ 2105 /2104 USER MANUAL Preliminary Supersedes data of 2003 Sep 17 , Microcontroller LPC2106/ 2105 //2104 2 October 02, 2003 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2106/ 2105 /2104 Table of Contents List of Figures . . . . . , . . . . . . . . . . LPC2106/ 2105 /2104 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 16 16 16 17 18 19 LPC2106/ 2105


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PDF LPC2106/2105/2104 LPC2106/2105//2104 LPC2106/2105/2104 str 2105 vpbdiv register ARM 7TDMI 32 BIT MICROPROCESSOR LPC2106 2105 ARM 7 lpc2106 ARM 7TDMI MICROPROCESSOR ARM microcontroller LPC2106/LPC2105 manual semiconductor
2004 - 3 pins LDR

Abstract: LDR SPECIFICATION str 2105 LDR 07 2105 LDR Datasheet LPC210X specification of ldr LDR -03 RTCK
Text: alternate function 1,which is the secondary JTAG interface (Please refer to the Pin Configuration and Pin Connect Block chapters in the LPC2106/ 2105 /2104 User Manual where the port pins P0.27­P0.31 are shown to , Programming chapter in the LPC2106/ 2105 /2104 User Manual) then user application in Flash will run and the , most of the debuggers handles the signature generation automatically. 6. User should then be able to , Philips LPC210x microcontroller family AN10255 ; LPC2106/ 2105 /2104 User Manual


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PDF LPC210x AN10255 LPC210x 3 pins LDR LDR SPECIFICATION str 2105 LDR 07 2105 LDR Datasheet specification of ldr LDR -03 RTCK
1999 - STEL-2105

Abstract: 2105 LINEAR STEL-2110A STEL-2130A STEL-2130 2105 STEL-2100A receiver timing recovery discriminator integrat
Text: )} This is a linear function of the symbol timing error that PRODUCT INFORMATION 7 STEL- 2105 , Integrator Block are used as the inputs for the Carrier Discriminator function . The STEL- 2105 incorporates , slowly the STEL- 2105 is provided with the Freeze Status Registers function . This is implemented by , STEL- 2105 Data Sheet STEL- 2105 Digital Downconverter & Bit Synchronizer/QPSK Demodulator , . FUNCTION BLOCKS Ð DESCRIPTION


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PDF STEL-2105 STEL-2105 2105 LINEAR STEL-2110A STEL-2130A STEL-2130 2105 STEL-2100A receiver timing recovery discriminator integrat
ADSP-2105

Abstract: No abstract text available
Text: ADSP- 2105 March 1990 For current information contact Analog Devices at (617) 461-3881 ADSP- 2105 , Prescaler Programmable W'pt StSte Generation Automatiç Boot of Internal Program Memory From Byte-Wide , On-Chip Clock Generation C 68-Lead PLCC \3- K\ \ \ y ANALOG DEVICES This information , agreed to in writing. 1 ADSP- 2105 For current information contact Analog Devices at (617) 461-3881 , W E E N ADSP-2101 AND ADSP- 2105


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PDF ADSP-2105 ADSP-2100 ADSP-2101 ADSP-2101. ADSP-2105. P-2105 ADSP-2105
addressing modes in adsp-21xx

Abstract: ADSP21XX block diagram addressing modes of adsp 21xx processors direct addressing mode in adsp-21xx EPROM 2764 ADSP-21xx block diagram ADSP-2106
Text: following ADSP-2100 Family processors: ADSP-2101 ADSP-2103 3.3 V Version of ADSP-2101 ADSP- 2105 Low Cost DSP , transmit data via the host interface port (ADSP-2111 only) The ADSP-2101, ADSP- 2105 , and ADSP-2115 comprise , . 15 SPECIFICATIONS (ADSP-2101/ 2105 /2115/2161/2163) . 17 Recommended , PARAMETERS (ADSP-2101/ 2105 /2111/2115/2161/2163) . 29 Clock Signals , -2101/2103/ 2105 /2115/216x) . . . . 52 80-Lead PQFP (ADSP-2101/2103/2115/216x) .53 80


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PDF 16-Bit ADSP-2111 addressing modes in adsp-21xx ADSP21XX block diagram addressing modes of adsp 21xx processors direct addressing mode in adsp-21xx EPROM 2764 ADSP-21xx block diagram ADSP-2106
2005 - ATR0620

Abstract: EMA8 atmel cpga CPGA144 EMA23
Text: Function GPSMODE0-12 SIGHI SIGLO GPS GPS mode Comment 1PPS ­ Output ­ ­ MSOUT , Programmable 8-/16-bit External Data Bus 16-channel GPS Correlator ­ Accuracy: TBD ­ Time to First Fix: TBD , GPS Format and 15-bit Fractional Part of a Second ­ Programmable Interrupt ­ Timer with a 8 , Battery Backup Memory 9 mm × 9 mm 100-pin BGA Package GPS Baseband Processor ATR0620 Summary Preliminary Rev. 4574CS­ GPS ­05/05 1. Description The GPS baseband processor ATR0620 includes a 16


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PDF 32-bit 16-bit 8-/16-bit 16-channel 4574CS ATR0620 EMA8 atmel cpga CPGA144 EMA23
2002 - ATR0620

Abstract: SCK-0120 gps m 89 pin configuration MAKING A10 BGA GPS BASEBAND PROCESSOR EMA18 EMA23 EMA8
Text: function of boot memory · Two different read protocols · Programmable wait state generation , Software Programmable 8-/16-bit External Data Bus 16-channel GPS Correlator ­ Accuracy: TBD ­ Time to , ) ­ Time in GPS Format and 15-bit Fractional Part of a Second ­ Programmable Interrupt ­ Timer with , Includes Power Supervisor Battery Backup Memory 9 mm × 9 mm 100-pin BGA Package GPS Baseband Processor ATR0620 Preliminary Description The GPS baseband processor ATR0620 includes a 16-channel GPS


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PDF 32-bit 16-bit 8-/16-bit 16-channel 4574B ATR0620 SCK-0120 gps m 89 pin configuration MAKING A10 BGA GPS BASEBAND PROCESSOR EMA18 EMA23 EMA8
2002 - ATR0620

Abstract: TXD02 EMA18 EMA8
Text: Function 10 ATR0620 4574A­ GPS ­11/02 ATR0620 PWM RTC The PWM includes two PWM channels. They , to Four Chip Selects ­ Software Programmable 8-/16-bit External Data Bus 16-channel GPS Correlator ­ , Time Clock (RTC) ­ Time in GPS Format and 15-bit Fractional Part of a Second ­ Programmable Interrupt ­ , GPS Baseband Processor ATR0620 Preliminary · · · · · · · · · Description The GPS baseband processor ATR0620 includes a 16-channel GPS correlator and is based on the ARM7TDMI processor core. This


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PDF 32-bit 16-bit 8-/16-bit 16-channel ATR0620 TXD02 EMA18 EMA8
2011 - Not Available

Abstract: No abstract text available
Text: BUFFALO B1919 GNSS RECEIVER MODULE TECHNICAL NOTES BUFFALO B1919 GNSS ( GPS /GLONASS) RECEIVER MODULE TECHNICAL HIGHLIGHTS Supports GPS L1 signal frequency (1575.42 MHz), C/A code Trimble’s Buffalo B1919 GNSS receiver module delivers top performance and Trimble quality in a new generation of , receiver provides L1 Frequency GPS and GLONASS - using the NMEA protocol from two serial ports, and also a PPS timing output. Buffalo can acquire and track GPS and GLONASS separately or use a combined


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PDF B1919 B1919 2002/95/EC PN022542-036A
2011 - C1919

Abstract: GPS GLONASS Antenna antenna mm size usb port amplifier circuit diagram 87777-00 Buffalo B1919 GNSS Carrier Board GGA5 glonass gps glonass antenna GPS receiver module Trimble sbas B1919
Text: Buffalo B1919 GNSS receiver module technical notes Buffalo B1919 GNSS ( gps /glonass) receiver module TECHNICAL HIGHLIGHTS Supports GPS L1 signal frequency (1575.42 MHz), C/A code Supports GLONASS L1 , performance and Trimble quality in a new generation of positioning products. Use the B1919 to bring innovative products to market. The Buffalo B1919 GNSS receiver provides L1 Frequency GPS and GLONASS - using the NMEA protocol from two serial ports, and also a PPS timing output. Buffalo can acquire and track GPS and GLONASS


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PDF B1919 B1919 2002/95/EC PN022542-036A C1919 GPS GLONASS Antenna antenna mm size usb port amplifier circuit diagram 87777-00 Buffalo B1919 GNSS Carrier Board GGA5 glonass gps glonass antenna GPS receiver module Trimble sbas
Not Available

Abstract: No abstract text available
Text: generation allows the processor to interface eas­ ily to slow memories. The ADSP- 2105 also provides one , ANALOG ► DEVICES DSP Microcomputer ADSP- 2105 FEATURES Complete DSP Microcomputer 100 ns , Timer with Prescaler Programmable W ait State Generation Automatic Boot of Internal Program Memory , = > DATA MEMORY DATA EXTERNAL ARITHMETIC UNITS ADSP-2100 BASE ARCHITECTURE j The ADSP- 2105 , sub­ set of the ADSP-2101. Users selecting the ADSP- 2105 will be able to preserve their investment


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PDF ADSP-2105 ADSP-2100 ADSP-2101 16-Bit
kalman gyro

Abstract: Inertial navigation system MNAV100CA RGA300CA AHRS400CD IMU gyro MEMS gyro sensor gps aided inertial navigation sensor IMU700CB inertial
Text: systems In 2005, Crossbow introduced the second generation MEMS Inertial systems combining GPS and , san jose, ca 95134-2109 GPS Navigation and AHRS Systems A GPS /AHRS System combines the features of an Attitude & Heading Reference with the Navigation capabilities of GPS to provide a high , Crossbow's NAV420 family of products utilizes MEMS-based inertial sensors and GPS technology to provide an , an IMU, VG, GPS and AHRS in a compact environmentally sealed enclosure. Attitude and Heading


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PDF AHRS510GA AHRS420CA NAV420CA MNAV100CA kalman gyro Inertial navigation system MNAV100CA RGA300CA AHRS400CD IMU gyro MEMS gyro sensor gps aided inertial navigation sensor IMU700CB inertial
Not Available

Abstract: No abstract text available
Text: GPS INFORMATION IN CONFIDENCE 5 Pin Function ADDR<6> PGA 257 157 M20 T Q F P 160 T Q , . GPS INFORMATION IN CONFIDENCE 8 Block Pin Name Pin Function SIM Card Interface SMCLK , the following table. GPS INFORMATION IN CONFIDENCE 11 CHANNEL Interrupt Source Function , Bit Function 12 11 10 9 8 7 6 5 4 3 2 1 0 GPS INFORMATION IN CONFIDENCE 12 System , gating and use of GPS 's low power sub-m icron CMOS technology and cell libraries. A TDM A system tim


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PDF GEM301 GEM301
Supplyframe Tracking Pixel