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Part Manufacturer Description Datasheet Download Buy Part
CLP0212FPXX5Z03A GE Critical Power CLP0212 Open Frame Power Supply, 90 - 264Vac input; 12Vdc output; 200W Output Power
CLP0212FPEX5Z02A GE Critical Power CLP0212 Open Frame Power Supply, 90 - 264Vac input; 12Vdc output; 200W Output Power
CLP0412FPXXXZ01A GE Critical Power CLP0412 Open Frame Power Supply, 90 - 265Vac Input; 12Vdc Output; 450W Output Power
CLP0212FPEX5Z03A GE Critical Power CLP0212 Open Frame Power Supply, 90 - 264Vac input; 12Vdc output; 200W Output Power
CLP0412FPXXXZ03A GE Critical Power CLP0412 Open Frame Power Supply, 90 - 265Vac Input; 12Vdc Output; 450W Output Power
CLP0112FPXXXZ02A GE Critical Power CLP0112 Open Frame Power Supply, 90 - 265Vac input; 12Vdc output; 150W Output Power, Conformal Coated

frame_ecc Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2010 - RAMB36SDP

Abstract:
Text: content. After the CRC indicates an error, then the FRAME_ECC is used to determine if a (correctable


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PDF XAPP1073 RAMB36SDP frame_ecc FIFO36 BA284 XAPP864 SelectMAP RAMB36E1 read back RAMB36E1 JESD89A adiru
2009 - NUMONYX xilinx bpi P30 virtex-6

Abstract:
Text: SIM_EFUSE_VALUE in Table 4-8. Removed references to cores in fourth paragraph of FRAME_ECC_VIRTEX6. Added , . . . . . . . . . . . . . . FRAME_ECC_VIRTEX6 . . . . . . . . . . . . . . . . . . . . . . . . . . .


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PDF UG360 NUMONYX xilinx bpi P30 virtex-6 FPGA Virtex 6 S29GLXXXP UG360 sha256 M25P128 LX240T NUMONYX j3d frame_ecc LX195T
2009 - xcf128x

Abstract:
Text: SIM_EFUSE_VALUE in Table 4-8. Removed references to cores in fourth paragraph of FRAME_ECC_VIRTEX6. Added , . . . . . . . . . . . . . . . FRAME_ECC_VIRTEX6 . . . . . . . . . . . . . . . . . . . . . . . . . .


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PDF UG360 xcf128x UG628 FPGA Virtex 6 SX475 UG438 v3.0 frame_ecc UG360 fpga radiation BGA LX760 spi flash programmer schematic
2004 - ug071

Abstract:
Text: No file text available


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PDF UG071 X8Y15 SRL16 ug071 LVCMOS12 TLR 308 XC4VFX20 DSP48 DS071 SelectMAP CRC32C CRC32-C Virtex-4 User Guide
2009 - HW-USB-II-G

Abstract:
Text: FRAME_ECC_VIRTEX6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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PDF UG360 HW-USB-II-G NUMONYX xilinx bpi spi flash programmer schematic NUMONYX xilinx spi virtex 5 UG628 XAPP974 XILINX/FPGA Virtex 6 FPGA Virtex 6 spi flash parallel port UG360
2006 - Virtex-5 LX50T

Abstract:
Text: . . . . . FRAME_ECC_VIRTEX5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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PDF UG191 Virtex-5 LX50T VIRTEX-5 LX110 VIRTEX-5 FX70T SVF pcf Virtex 5 CF UG191 TX240T fx130 frame_ecc XC5VLX85T
2006 - xcf128x

Abstract:
Text: . . . . . . . . . . . . . . . . . . . . . . . . . 100 FRAME_ECC_VIRTEX5 . . . . . . . . . . . . . .


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PDF UG191 xcf128x VIRTEX-5 FX70T MultiBoot ug191 VIRTEX-5 LX110 Virtex-5 TX240T SelectMAP FX70T DSP48E
2006 - UG191

Abstract:
Text: . . . . . FRAME_ECC_VIRTEX5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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PDF UG191 UG191 VIRTEX-5 FX70T frame_ecc Virtex 5 LX50T controllers XC5VLX MultiBoot VIRTEX-5 LX110 XC5VFX70 Virtex-5 LX50 DSP48E
2006 - FF1148 raw material properties

Abstract:
Text: No file text available


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PDF DS595 10CESnL 10CESnR 10CES 10CESn UG075 FF1148 raw material properties BIM G18 Y1 xc4vlx25-10ffg668 XQ4VSX55 H8 hitachi programming manual frame_ecc EE16 ecg semiconductor replacement guide ecg master replacement guide byb 504
2012 - XC7K325TFFG900

Abstract:
Text: EFUSE_USRs: Number of FRAME_ECCs : Number of GTXE2_CHANNELs: Number of GTXE2_COMMONs: Number of ICAPs , DNA_PORTs: Number of DSP48E1s: Number of EFUSE_USRs: Number of FRAME_ECCs : Number of GTXE2_CHANNELs


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PDF KC705 DS669 KC705 XC7K325TFFG900 kintex7 XC7K325TFFG900 -2 XC7K325TFFG900-2
2009 - XAPP864

Abstract:
Text: CRCERROR output of the FRAME_ECC_VIRTEX5 primitive. Reaction to the disturbance varies according to the , Programmable Interconnect) (DW = Dedicated Wire) User Design to Observe Readback CRC FRAME_ECC_VIRTEX5 , : Readback CRC Arrangement in a Virtex-5 FPGA The optional FRAME_ECC_VIRTEX5 primitive provides internal , possible to disable the INIT_B pin using a POST_CRC_SIGNAL = FRAME_ECC_ONLY constraint so that only the , SEUs The FRAME_ECC_VIRTEX5 primitive also provides access to the SYNDROMEVALID signal. While the


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PDF XAPP864 XAPP864 verilog hdl code for triple modular redundancy ML507 frame_ecc xilinx uart verilog code for spartan 3a Xilinx VIRTEX-5 xc5vlx50 RAM SEU uart verilog testbench UG-116 ug191
2009 - XAPP864

Abstract:
Text: of the FRAME_ECC_VIRTEX5 primitive. Reaction to the disturbance varies according to the , Programmable Interconnect) (DW = Dedicated Wire) User Design to Observe Readback CRC FRAME_ECC_VIRTEX5 , _01_011409 Figure 1: Readback CRC Arrangement in a Virtex-5 FPGA The optional FRAME_ECC_VIRTEX5 primitive , application. It is possible to disable the INIT_B pin using a POST_CRC_SIGNAL = FRAME_ECC_ONLY constraint so , errors. The FRAME_ECC_VIRTEX5 primitive also provides access to the SYNDROMEVALID signal. While the


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PDF XAPP864 ML505 XAPP864 icap UG332 pixel vhdl sequential logic circuit experiments UG191 verilog syndrome WP286
2011 - UG470

Abstract:
Text: No file text available


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PDF UG470 UG470
2012 - XC7K325TFFG900-2

Abstract:
Text: CAPTUREs: Number of DNA_PORTs: Number of DSP48E1s: Number of EFUSE_USRs: Number of FRAME_ECCs : Number of , DSP48E1s: Number of EFUSE_USRs: Number of FRAME_ECCs : Number of GTXE2_CHANNELs: Number of GTXE2_COMMONs


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PDF KC705 DS669 XC7K325TFFG900-2 XC7K325TFFG900 PC28F00AP30TF XC7K325T-ffg900 pc28f00ap30 adv7511 pcie microblaze RS232-UART pc28f00 DSP48E1s
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